PT6955 LED Driver IC DESCRIPTION PT6955 is an LED Controller driven on a 1/4 to 1/7 duty factor. Twelve/nine segment output lines, 4 to 7 grid output lines, one display memory, control circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip microcomputer. Serial data is fed to PT6955 via a three-line serial interface. Housed in a 24-pin SOP, PT6955’s pin assignments and application circuit are optimized for easy PCB Layout and cost saving advantages. FEATURES • • • • • CMOS Technology Low Power Consumption 8-Step Dimming Circuitry Serial Interface for Clock, Data Input, Strobe Pins Available in 24-pin, SOP APPLICATION • Micro-computer Peripheral Device BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6955 APPLICATION CIRCUIT Notes: 1. The capacitor (0.1μF) connected between the GND and VDD Pins must be located as near as possible to the PT6955 chip. 2. The PT6955 power supply is separate from the application system power supply. COMMON CATHODE TYPE LED PANEL V1.6 2 November 2012 PT6955 ORDER INFORMATION Valid Part Number PT6955 Package Type 24pins, SOP, 300mil Top Code PT6955 PIN CONFIGURATION PIN DESCRIPTION Pin Name I/O OSC I DIN I CLK I STB I VDD - SG1 ~ SG9 O SG10/GR7 ~ SG12/GR5 O GND GR4 ~ GR1 O V1.6 Description Oscillator Input Pin A resistor is connected to this pin to determine the oscillation frequency Data Input Pin This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit) Clock Input Pin This pin reads serial data at the rising edge. Serial Interface Strobe Pin The data input after the STB has fallen is processed as a command. When this pin is "HIGH", CLK is ignored. Power Supply Segment Output Pins (p-channel, open drain) Segment Output Pin/Grid Output Pin (CMOS Output) Ground Pin Grid Output Pins (n-channel, open drain) 3 Pin No. 1 2 3 4 5, 18 6 ~ 14 15 ~ 17 19, 24 20 ~ 23 November 2012 PT6955 INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below. Input Pins: CLK, STB & DIN Output Pins: SG10/GR7, SG11/GR6, SG12/GR5 Output Pins: GR1 to GR4 Output Pins: SG1 to SG9 V1.6 4 November 2012 PT6955 FUNCTION DESCRIPTION COMMANDS A command is the first byte (b0 to b7) inputted to PT6955 via the DIN Pin after STB Pin has changed from “HIGH” to “LOW” State. If for some reason the STB Pin is set to “HIGH” while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. COMMAND 1: DISPLAY MODE SETTING COMMANDS PT6955 provides 4 display mode settings as shown in the diagram below: As stated earlier a command is the first one byte (b0 to b7) transmitted to PT6955 via the DIN Pin when STB is “LOW”. However, for these commands, Bit No. 3 to Bit No.6 (b2 to b5) are ignored, Bit No.7 & Bit No.8 (b6 to b7) are given a value of “0”. The Display Mode Setting Commands determine the number of segments and grids to be used (1/4 to 1/7 duty, 12 to 9 segments). When these commands are executed, the display is forcibly turned off. A display command “ON” must be executed in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned “ON”, the 7-Grid, 9-Segment Mode is selected. MSB 0 0 - - - Not Relevant - b1 LSB b0 Display Mode Settings: 00: 4 digits, 12 segments 01: 5 digits, 11 segments 10: 6 digits, 10 segments 11: 7 digits, 9 segments COMMAND 2: DATA SETTING COMMANDS The Data Setting Commands executes the Data Write Mode for PT6955. The Data Setting Command, the bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of “1” while bit 8 (b7) is given the value of “0”. Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of “0”. MSB 0 1 - - Not Relevant b3 b2 b1 LSB b0 Data Write Mode Settings: 00: Write Data to Display Mode Address Increment Mode Settings (Display Mode) 0: Increment Address after Data has been Written 1: Fixed Address Mode Settings: 0: Normal Operation Mode 1: Test Mode V1.6 5 November 2012 PT6955 COMMAND 3: ADDRESS SETTING COMMANDS Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of “00H” to 0DH”. If the address is set to 0EH or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at “00H”. Please refer to the diagram below. MSB 1 1 - - b3 b2 b1 Not Relevant LSB b0 Address: 00H to 0DH DISPLAY MODE AND RAM ADDRESS Data transmitted from an external device to PT6955 via the serial interface are stored in the Display RAM and are assigned addresses. The RAM Addresses of PT6955 are given below in 8 bits unit. SG1 SG4 SG5 00HL 02HL 04HL 06HL 08HL 0AHL 0CHL SG8 SG9 SG12 00HU 02HU 04HU 06HU 08HU 0AHU 0CHU b0 01HL 03HL 05HL 07HL 09HL 0BHL 0DHL b3 xxHL Lower 4 bits b4 DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 b7 xxHU Higher 4 bits COMMAND 4: DISPLAY CONTROL COMMANDS The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF. MSB 1 0 - - Not Relevant b3 b2 b1 LSB b0 Dimming Quantity Settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width = 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display Settings: 0: Display Off 1: Display On V1.6 6 November 2012 PT6955 DISPLAY TIMING WAVEFORM SERIAL COMMUNICATION FORMAT The following diagram shows the PT6955 serial communication format. RECEPTION (DATA/COMMAND WRITE) V1.6 7 November 2012 PT6955 SWITCHING CHARACTERISTICS WAVEFORM where: PWCLK (Clock Pulse Width) ≥ 400ns tsetup (Data Setup Time) ≥100ns tCLK-STB (Clock - Strobe Time) ≥ 1µs tTZH (Rise Time) ≤ 1 µs tTZL ≤ 1µs V1.6 PWSTB (Strobe Pulse Width) ≥ 1µs thold (Data Hold Time) ≥ 100ns tTHZ (Fall Time) ≤ 10µs fosc = Oscillation Frequency tTLZ ≤ 10µs 8 November 2012 PT6955 APPLICATIONS Display memory is updates by incrementing addresses. Please refer to the following diagram. where: Command 1: Display Mode Setting Command Command 2: Data Setting Command Command 3: Address Setting Command Data 1 to n: Transfer Display Data (14 Byte max.) Command 4: Display Control Command The following diagram shows the waveforms when updating specific addresses. where: Command 2: Data Setting Command Command 3: Address Setting Command Data: Display Data V1.6 9 November 2012 PT6955 RECOMMENDED SOFTWARE FOLWCHART Notes: 1. Command 1: Display Mode Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting. V1.6 10 November 2012 PT6955 SOP 24L (300MIL) THERMAL PERFORMANCE IN STILL AIR JUNCTION TEMPERATURE: 100℃ V1.6 11 November 2012 PT6955 ABSOLUTE MAXIMUM RATINGS (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Supply Voltage Logic Input Voltage Driver Output Current/Pin Maximum Driver Output Current/Total Operating Temperature Symbol VDD VI IOLGR IOHSG ITOTAL Topr Rating -0.3 to +7.0 -0.3 to VDD+0.3 +250 -50 400 -40 ~ +85 Units V V mA mA mA Tstg -40 ~ +150 ℃ Storage Temperature ℃ RECOMMANDED OPERATING RANGE (Unless otherwise stated, Topr=-40 to +85℃, GND=0V) Parameter Symbol Logic Supply Voltage VDD Dynamic Current (see note) IDDdyn High-Level Input Voltage VIH Low-Level Input Voltage VIL Min. 4.5 0.8VDD 0 Typ. 5 - Max. 5.5 5 VDD 0.3VDD Unit V mA V V Note: Test Condition: Set Display Control Commands=80H (Display Turn Off State) ELECTRICAL CHARACTERISTICS (Unless otherwise stated, VDD=5V, GND=0V, Ta=25℃) Parameter Symbol Test Condition VO=VDD-1V IOHSG(1) SG1 to SG9, SG10/GR7 to SG12/GR5 High-Level Output Current VO=VDD-2V IOHSG(2) SG1 to SG9, SG10/GR7 to SG12/GR5 VO=0.3V Low-Level Output Current IOLGR GR1 to GR4, SG10/GR7 to SG12/GR5 VO=VDD-1V Segment High-Level Output ITOLSG SG1 to SG9, Current Tolerance SG10/GR7 to SG12/GR5 High-Level Input Voltage VIH Low-Level Input Voltage VIL Oscillation Frequency fosc R=51KΩ V1.6 12 Min. Typ. Max. Unit -10 -14 -30 mA -20 -25 -50 mA 100 140 - mA - - ±5 % 0.8VDD 350 500 0.3VDD 650 V V KHz November 2012 PT6955 PACKAGE INFORMATION 24-PIN, SOP, 300MIL Symbol A A1 b c D E E1 e L θ Min. 2.35 0.10 0.33 0.23 15.20 10.00 7.40 Nom. 1.27 BSC. - 0.40 0° Max. 2.65 0.30 0.51 0.32 15.60 10.65 7.60 1.27 8° Notes: 1. All controlling dimensions are in millimeters. 2. Refer to JEDEC MS-013 AD. V1.6 13 November 2012 PT6955 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.6 14 November 2012