PT6959 LED Driver IC DESCRIPTION PT6959 is an LED Controller driven on a 1/4 to 1/7 duty factor. Fourteen to eleven segment output lines, 4 to 7 grid output lines, one display memory, control circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip microcomputer. Serial data is fed to PT6959 via a three-line serial interface. Housed in a 28-pin SOP, PT6959’s pin assignments and application circuit are optimized for easy PCB Layout and cost saving advantages. FEATURES CMOS technology Low power consumption 8-step dimming circuitry Serial interface for clock, data input, strobe pins Available in 28-pin, SOP APPLICATION Microcomputer peripheral devices BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6959 APPLICATION CIRCUIT Notes: 1. The capacitor (0.1µF) connected between the GND and VDD Pins must be located as near as possible to the PT6959 chip. 2. The PT6959 power supply is separate from the application system power supply. COMMON CATHODE TYPE LED PANEL V1.7 2 October 2013 PT6959 ORDER INFORMATION Valid Part Number Package Type Top Code PT6959-S 28-pin, SOP, 300mil PT6959-S PIN CONFIGURATION PIN DESCRIPTION Pin Name I/O OSC I DIN I CLK I STB I VDD Description Pin No. - Oscillator input pin A resistor is connected to this pin to determine the oscillation frequency. Data input pin This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit). Clock input pin This pin reads serial data at the rising edge. Serial interface strobe pin The data input after the STB has fallen is processed as a command. When this pin is “HIGH”, CLK is ignored. Power supply 5, 20 SG1 ~ SG11 O Segment output pins (p-channel, open drain) 6 ~ 16 SG12/GR7 ~ SG14/GR5 O Segment output pin/Grid output pin (CMOS output) 17 ~ 19 GND - Ground pin 21, 26 GR4 ~ GR1 O Grid output pins (n-channel, open drain) 22 ~ 25 NC - No connection 27, 28 V1.7 3 1 2 3 4 October 2013 PT6959 INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below. Input Pins: CLK, STB & DIN Output Pins: SG14/GR5 to SG12/GR7 Output Pins: GR1 to GR4 Output Pins: SG1 to SG11 V1.7 4 October 2013 PT6959 FUNCTION DESCRIPTION COMMANDS A command is the first byte (b0 to b7) inputted to PT6959 via the DIN Pin after STB Pin has changed from “HIGH” to “LOW” State. If for some reason the STB Pin is set to “HIGH” while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. COMMAND 1: DISPLAY MODE SETTING COMMANDS PT6959 provides 4 display mode settings as shown in the diagram below: As stated earlier a command is the first one byte (b0 to b7) transmitted to PT6959 via the DIN Pin when STB is “LOW”. However, for these commands, Bit No. 3 to Bit No.6 (b2 to b5) are ignored, Bit No. 7 & Bit No. 8 (b6 to b7) are given a value of “0”. The Display Mode Setting Commands determine the number of segments and grids to be used (1/4 to 1/7 duty, 14 to 11 segments). When these commands are executed, the display is forcibly turned off. A display command “ON” must be executed in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned “ON”, the 7-Grid, 11-Segment Mode is selected. MSB 0 0 - - Not Relevant - - b1 LSB b0 Display Mode Settings: 00: 4 digits, 14 segments 01: 5 digits, 13 segments 10: 6 digits, 12 segments 11: 7 digits, 11 segments COMMAND 2: DATA SETTING COMMANDS The Data Setting Commands executes the Data Write Mode for PT6959. The Data Setting Command, the bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of “1” while bit 8 (b7) is given the value of “0”. Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of “0”. MSB 0 1 - - Not Relevant b3 b2 b1 LSB b0 Data Write Mode Setting: 00: Write Data to Display Mode Address Increment Mode Settings (Display Mode) 0: Increment Address after Data has been Written 1: Fixed Address Mode Settings: 0: Normal Operation Mode 1: Test Mode V1.7 5 October 2013 PT6959 COMMAND 3: ADDRESS SETTING COMMANDS Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of “00H” to 0DH”. If the address is set to 0EH or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at “00H”. Please refer to the diagram below. MSB 1 1 - - b3 b2 b1 Not Relevant LSB b0 Address: 00H to 0DH Display Mode and RAM Address Data transmitted from an external device to PT6959 via the serial interface are stored in the Display RAM and are assigned addresses. The RAM Addresses of PT6959 are given below in 8 bits unit. SG1 SG4 SG5 SG8 SG9 SG12 SG13 SG14 00HL 00HU 01HL 01HU DIG1 02HL 02HU 03HL 03HU DIG2 04HL 06HL 08HL 04HU 06HU 08HU 05HL 07HL 09HL 05HU 07HU 09HU DIG3 DIG4 DIG5 0AHL 0AHU 0BHL 0BHU DIG6 0CHL 0CHU 0DHL 0DHU DIG7 b0 b3 b4 b7 xxHL xxHU Lower 4 bits Higher 4 bits COMMAND 4: DISPLAY CONTROL COMMANDS The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF. MSB 1 0 - - Not Relevant b3 b2 b1 LSB b0 Dimming Quantity Settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width = 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display Settings: 0: Display Off 1: Display On V1.7 6 October 2013 PT6959 DISPLAY TIMING WAVRFORM SERIAL COMMUNICATION FORMAT The following diagram shows the PT6959 serial communication format. RECEPTION (DATA/COMMAND WRITE) V1.7 7 October 2013 PT6959 SWITCHING CHARACTERISTIC WAVEFORM PT6959 Switching Characteristic Waveform s given below. where: PW CLK (Clock Pulse Width) ≥ 400ns tsetup (Data Setup Time) ≥ 100ns tCLK-STB (Clock - Strobe Time) ≥ 1µs tTZH (Rise Time) ≤ 1µs tTZL < 1µs V1.7 PW STB (Strobe Pulse Width) ≥ 1µs thold (Data Hold Time) ≥ 100ns tTHZ (Fall Time) ≤ 10µ fosc=Oscillation Frequency tTLZ < 10µs 8 October 2013 PT6959 APPLICATIONS Display memory is updated by incrementing addresses. Please refer to the following diagram. where: Command 1: Display Mode Setting Command Command 2: Data Setting Command Command 3: Address Setting Command Data 1 to n : Transfer Display Data (14 Bytes max.) Command 4: Display Control Command The following diagram shows the waveforms when updating specific addresses. where: Command 2: Data Setting Command Command 3: Address Setting Command Data: Display Data V1.7 9 October 2013 PT6959 RECOMMENDED SOFTWARE PROGRAMMING FLOWCHART START Delay 200 ms SET COMMAND 2 (Write Data) SET COMMAND 3 Clear Display RAM (See Note 5) INITIAL SETTING SET COMMAND 1 SET COMMAND 4 (88H ~ 8FH: Display ON) MAIN PROGRAM SET COMMAND 2 (READ KEY & WRITE DATA INCLUDED) MAIN LOOP SET COMMAND 3 SET COMMAND 1 SET COMMAND 4 END Notes: 1. Command 1: Display Mode Setting Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting. V1.7 10 October 2013 PT6959 SOP 28 (300MIL) THERMAL PERFORMANCE IN STILL AIR AT TJ=100℃ 1200 Power Dissipation Pd (mW) 1101 1000 IC Mounted on Glass Epoxy PCB 800 751 600 400 IC Single 200 0 -25 0 25 50 75 100 O Ambient Temperature, Ta ( C) V1.7 11 October 2013 PT6959 ABSOLUTE MAXIMUM RATINGS (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Symbol Rating Units VDD -0.3 to +7.0 V VI IOLGR IOHSG ITOTAL -0.3 to VDD+0.3 +250 -50 400 V mA mA mA Operating Temperature Topr -40 ~ +85 ℃ Storage Temperature Tstg -40 ~ +150 ℃ Supply Voltage Logic Input Voltage Driver Output Current/Pin Maximum Driver Output Current/Total RECOMMANDED OPERATING RANGE (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Logic Supply Voltage Dynamic Current (see note) High-Level Input Voltage Low-Level Input Voltage Symbol Min. Typ. Max. Unit VDD IDDdyn VIH VIL 4.5 0.8VDD 0 5 - 5.5 5 VDD 0.3VDD V mA V V Note: Test Condition: Set Display Control Commands = 80H (Display Turn Off State) ELECTRICAL CHARACTERISTICS (Unless otherwise stated, VDD=5V, GND=0V, Ta=25℃) Parameter Symbol Test Condition IOHSG(1) High-Level Output Current IOHSG(2) VO=VDD-1V, SG1 to SG11, SG12/GR7 to SG14/GR5 VO=VDD-2V, SG1 to SG11, SG12/GR7 to SG14/GR5 VO=0.3V, GR1 to GR4, SG12/GR7 to SG14/GR5 Low-Level Output Current IOLGR Segment High-Level Output Current Tolerance ITOLSG High-Level Input Voltage VIH VO=VDD-1V, SG1 to SG11, SG12/GR7 to SG14/GR5 - Low-Level Input Voltage Oscillation Frequency VIL fosc R=51KΩ V1.7 12 Min. Typ. Max. Unit -10 -14 -30 mA -20 -25 -50 mA 100 140 - mA - - ±5 % 0.8VDD - - V 350 500 0.3VDD 650 V KHz October 2013 PT6959 PACKAGE INFORMATION 28 PINS, SOP, 300MIL Symbol A A1 b c D E E1 e L θ Min. 2.35 0.10 0.33 0.23 17.7 10.00 7.40 Nom. - 1.27 BSC - 0.40 0° Max. 2.65 0.30 0.51 0.32 18.10 10.65 7.60 1.27 8° Notes: 1. All dimensions are in millimeter. 2. Refer to JEDEC MS-012AE V1.7 13 October 2013 PT6959 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.7 14 October 2013