PT6324 VFD Driver/Controller IC DESCRIPTION PT6324 is a Vacuum Fluorescent Display (VFD) Controller driven on a 1/8 to 1/16 duty factor housed in 52-pin plastic LQFP. 24 segment output lines, 16 grid output lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip micro computer. Serial data is fed to PT6324 via a three-line serial interface. APPLICATIONS FEATURES • • • • • CMOS technology Low power consumption Wide operating voltage VDD=2.7V~5.5V Key scanning (16 x 2 matrix) Display modes: (24 segments, 8 digits to 24 segments, 16 digits) • 8-Step dimming circuitry • Serial interface for Clock, Data Input, Data Output, Strobe pins • No external resistors needed for driver outputs • Microcomputer peripheral devices • Digital Audio/Video system: CD/MD/VCD/DVD players • Car audio • VCR • Electric scale meter • P.O.S. • Electronic equipment with instructional display BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6324 16-GRID X 24-SEGMENT VFD APPLICATION CIRCUIT Notes: 1. The value of Rosc is depend on PT6324 IC chip supply voltage of VDD (Rosc=82KΩ, when VDD=5V; Rosc=100KΩ, when VDD=3.3V). 2. Z1, Z2=Zener diode 5.1V 3. Please adding the current amplifying circuit as following figure when IOHGR>15mA on VFD panel for high brightness issue. *=C.A. Circuit=Current amplifying circuit C.A. Circuit-1 & C.A. Circuit-2 Ex.: Parts recommended: • Q=SAMSUNG-KSR1105 (General fast switching transistor) • D=HITACHI-HSM221C (General fast recovery diode) V1.5 2 June 2010 PT6324 ORDER INFORMATION Valid Part Number PT6324-LQ Package Type 52-Pin, LQFP Top Code PT6324-LQ PIN CONFIGURATION V1.5 3 June 2010 PT6324 PIN DESCRIPTION Pin Name I/O CLK I DIN I STB I DOUT O K1 to K2 I OSC I GND VDD SG1/KS1 to SG16/KS16 SG17 to SG24 GR1 to GR16 VEE - V1.5 O O O - Description Clock input pin This pin reads serial data at the rising edge and outputs data at the falling edge. Data input pin When this pin acts as input pin, serial data is inputted at the rising edge of the shift clock (starting from the lower bit) Serial interface strobe pin The data input after the STB has fallen is processed as a command. When this in is “HIGH”, CLK is ignored. Data output pin (N-channel, Open-drain) When this pin acts as output pin, serial data is outputted at the falling edge of the shift clock (starting from the lower bit) Key data input pins The data inputted to these pins is latched at the end of the display cycle. Oscillator input pin A resistor is connected to this pin to determine the oscillation frequency. Ground pin Logic power supply High-voltage segment output pins Also acts as the key source High-voltage segment output pins High-voltage grid output pins Pull-down level 4 Pin No. 1 2 3 4 5, 6 7 8, 52 9, 51 10 to 25 26 to 33 34 to 49 50 June 2010 PT6324 INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below: Output Pins: SGn/GRn Input Pins: DIN, CLK, STB Input Pins: K1, K2 Output Pin: DOUT V1.5 5 June 2010 PT6324 FUNCTION DESCRIPTION COMMANDS Commands determine the display mode and status of PT6324. A command is the first byte (b0 to b7) inputted to PT6324 via the DIN Pin after STB Pin has changed from “HIGH” to “LOW” State. If for some reason the STB Pin is set to “HIGH” while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. COMMAND 1: DISPLAY MODE SETTING COMMANDS PT6324 provides 8 display mode settings as shown in the diagram below: As stated earlier a command is the first one byte (b0 to b7) transmitted to PT6324 via the DIN Pin when STB is “LOW”. However, for these commands, the bits 5 to 8 (b4 to b7) are given a value of “0”. The Display Mode Setting Commands determine the number of segments and grids to be used (1/8 to 1/16 duty, 24 segments). When these commands are executed, the display is forcibly turned off. A display command “ON” must be executed in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned “ON”, the 16-digit, 24-segment modes is selected. MSB 0 0 0 0 b3 b2 b1 LSB b0 Display mode settings: 0000: 8 digits, 24 segments 1000: 9 digits, 24 segments 1001: 10 digits, 24 segments 1010: 11 digits, 24 segments 1011: 12 digits, 24 segments 1100: 13 digits, 24 segments 1101: 14 digits, 24 segments 1110: 15 digits, 24 segments 1111: 16 digits, 24 segments V1.5 6 June 2010 PT6324 DISPLAY MODE AND RAM ADDRESS Data transmitted from an external device to PT6324 via the serial interface are stored in the Display RAM and are assigned addresses. The RAM Addresses of PT6324 are given below in 8 bits unit. SG1 SG4 SG5 SG8 SG9 SG12 SG16 SG17 SG20 SG21 SG24 00HL 00HU 01HL 01HU 02HL 02HU 03HL 03HU 04HL 04HU 05HL 05HU DIG1 DIG2 06HL 06HU 07HL 07HU 08HL 08HU DIG3 09HL 09HU 0AHL 0AHU 0BHL 0BHU DIG4 0CHL 0CHU 0DHL 0DHU 0EHL 0EHU DIG5 0FHL 0FHU 10HL 10HU 11HL 11HU DIG6 12HL 12HU 13HL 13HU 14HL 14HU DIG7 15HL 15HU 16HL 16HU 17HL 17HU DIG8 18HL 18HU 19HL 19HU 1AHL 1AHU DIG9 1BHL 1BHU 1CHL 1CHU 1DHL 1DHU DIG10 1EHL 1EHU 1FHL 1FHU 20HL 20HU 21HL 21HU 22HL 22HU 23HL 23HU DIG11 DIG12 24HL 24HU 25HL 25HU 26HL 26HU DIG13 27HL 27HU 28HL 28HU 29HL 29HU DIG14 2AHL 2AHU 2BHL 2BHU 2CHL 2CHU DIG15 2DHL 2DHU 2EHL 2EHU 2FHL 2FHU DIG16 b0 V1.5 SG13 b3 b4 b7 xxHL xxHU Lower 4 bits Higher 4 bits 7 June 2010 PT6324 COMMAND 2: DATA SETTING COMMANDS The Data Setting Commands executes the Data Write or Data Read Modes for PT6324. The data Setting Command, the bits 5 and 6 (b4, b5) are given the value of “0”, bit 7 (b6) is given the value of “1” while bit 8 (b7) is given the value of “0”. Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of “0”. MSB 0 1 0 0 b3 b2 b1 LSB b0 Data write & read mode settings: 00: Write data to display mode 01: Reset function (one time reset) 10: Read key data 11: Not relevant Address increment mode settings (Display mode): 0: Increment address after data has been written 1: Fixed address Mode settings: 0: Normal operation mode 1: Test mode PT6324 KEY MATRIX & KEY INPUT DATA STORAGE RAM PT6324 Key Matrix consists of 16 x 2 array as shown below: Each data inputted by each key are stored as follows. They are read by a READ Command, starting from the last significant bit. When the most significant bit of the data (SG16, b7) has been read, the least significant bit of the next data (SG1, b0) is read. K1……………….K2 SG1/KS1 SG5/KS5 SG9/KS9 SG13/KS13 b0………………..b 1 V1.5 K1………………..K2 SG2/KS2 SG6/KS6 SG10/KS10 SG14/KS14 b2…………………b 3 K1……………….K2 SG3/KS3 SG7/KS7 SG11/KS11 SG15/KS15 b4………………..b 5 8 K1……………….K2 SG4/KS4 SG8/KS8 SG12/KS12 SG16/KS16 b6………………..b 7 Reading Sequence June 2010 PT6324 COMMAND 3: ADDRESS SETTING COMMANDS Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of “00H” to “2FH”. If the address is set to 30H or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at “00H”. Please refer to the diagram below. MSB 1 1 b5 b4 b3 b2 b1 LSB b0 Address: 00H to 2FH COMMAND 4: DISPLAY CONTROL COMMANDS The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF. MSB 1 0 0 0 b3 b2 b1 LSB b0 Dimming quantity settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width = 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display settings: 0: Display off (Key scan continues) 1: Display on V1.5 9 June 2010 PT6324 DISPLAY TIMING The Key Scanning and display timing diagram is given below. One cycle of key scanning consists of 2 frames. The data of the 16 x 2 matrix is stored in the RAM. Internal Operating Frequency (fosc) = 224/T Note: T is the width of Segment only SERIAL COMMUNICATION FORMAT The following diagram shows the PT6324 serial communication format. The DIN/DOUT Pin is an Schmitt trigger circuit and N-channel, open-drain output pin, therefore, it is highly recommended that an external pull-up resistor (1KΩ to 10KΩ) must be connected to DIN/DOUT when using key scan function. where: twait (waiting time) ≥ 1µs It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data is greater or equal to 1µs. V1.5 10 June 2010 PT6324 SWITCHING CHARACTERISTIC WAVEFORM PT6324 Switching Characteristics Waveform is given below. APPLICATIONS Display memory is updated by incrementing addresses. Please refer to the following diagram. The following diagram shows the waveforms when updating specific addresses. V1.5 11 June 2010 PT6324 RECOMMENDED SOFTWARE FLOWCHART Notes: 1. Command 1: Display Mode Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting. V1.5 12 June 2010 PT6324 ABSOLUTE MAXIMUM RATINGS (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Logic supply voltage Driver supply voltage Logic input voltage VFD driver output voltage VFD driver output current Symbol VDD VEE VI VO IOVFD Ratings -0.3 to +7 VDD +0.3 to VDD -40 -0.3 to VDD +0.3 VEE -0.3 to VDD +0.3 -40 (Grid); -15 (Segment) Unit V V V V mA Operating temperature Topr -40 to +85 ℃ Storage temperature Tstg -65 to +150 ℃ RECOMMENDED OPERATING RANGE (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Logic supply voltage High-level input voltage (VDD=5V) Low-level input voltage (VDD=5V) High-level input voltage (VDD=3.3V) Low-level input voltage (VDD=3.3V) Driver supply voltage Symbol VDD VIH VIL VIH VIL VEE Min. 2.7 0.75VDD 0 0.8VDD 0 VDD -35 Typ. 5 - Max. 5.5 VDD 0.25VDD VDD 0.2VDD 0 Unit V V V V V V ELECTRICAL CHARACTERISTICS (Unless otherwise stated, VDD=5V, GND=0V, VEE=VDD-35 V, Ta=25℃) Parameter Symbol Test Condition DOUT Low-level output voltage VOLDOUT IOLDOUT=4mA High-level output current IOHSG VO=VDD -2V, SG1 to SG24 High-level output current IOHGR VO=VDD -2V, GR1 to GR16 High-level input voltage VIH Low-level input voltage VIL Input current Dynamic current consumption II IDDdyn Min. Typ. Max. Unit - - 0.4 V -3 -15 0.75VDD - - 0.25VDD mA mA V V VDD or GND - - Under no load, Display OFF - - ±1 5 μA mA Min. Typ. Max. Unit - - 0.4 V -1.5 -6 0.8VDD - - 0.2VDD mA mA V V ±1 3 μA mA (Unless otherwise stated, VDD=3.3V, GND=0V, VEE=VDD-35 V, Ta=25℃) Parameter Symbol Test Condition DOUT Low-level output voltage VOLDOUT IOLDOUT=4mA High-level output current IOHSG VO=VDD -2V, SG1 to SG24 High-level output current IOHGR VO=VDD -2V, GR1 to GR16 High-level input voltage VIH Low-level input voltage VIL Input current Dynamic current consumption V1.5 II IDDdyn VDD or GND - - Under no load, Display OFF - - 13 June 2010 PT6324 TIMING CHARACTERISTICS (Unless otherwise specified, VDD=5V, GND=0V, VEE=VDD-35V, Ta=25℃) Min. Typ. Max. Unit Clock pulse width Parameter PWCLK 400 - - ns Strobe pulse width PWSTB 1000 - - ns Data setup time tsetup 100 - - ns Data hold time thold 100 - - ns 1000 - - ns - - 100 ns - - 400 ns Min. Typ. Max. Unit Clock-strobe time Propagation delay time Symbol tCLK-STB tPZL tPLZ Conditions CLK↑ → STB↑ RL=10KΩ, CL=15pF (Unless otherwise specified, VDD=3.3V, GND=0V, VEE=VDD-35V, Ta=25℃) Parameter Symbol Conditions Clock pulse width PWCLK 400 - - ns Strobe pulse width PWSTB 1000 - - ns Data setup time tsetup 100 - - ns Data hold time thold 100 - - ns 1000 - - ns - - 100 ns - - 600 ns Clock-strobe time Propagation delay time tCLK-STB tPZL tPLZ CLK↑ → STB↑ RL=10KΩ, CL=15pF SWITCHING CHARACTERISTICS (Unless otherwise specified, VDD=5V, GND=0V, VEE=VDD-35V, Ta=25℃) Parameter Symbol Grid rise time tGLH Segment rise time tSLH Grid fall time tGHL Segment fall time tSHL Oscillation frequency fOSC Conditions CL=300pF R=82KΩ Min. Typ. Max. Unit - - 0.5 µs - - 2.0 µs - - 150 µs - - 150 µs 350 500 650 KHz Min. Typ. Max. Unit - - 1.2 µs - - 4.0 µs - - 150 µs - - 150 µs 350 500 650 KHz (Unless otherwise specified, VDD=3.3V, GND=0V, VEE=VDD-35V, Ta=25℃) Parameter Grid rise time Symbol tGLH Segment rise time tSLH Grid fall time tGHL Segment fall time tSHL Oscillation frequency fOSC V1.5 Conditions CL=300pF R=100KΩ 14 June 2010 PT6324 PACKAGE INFORMATION 52-PIN, LQFP PACKAGE (BODY SIZE=14MM X 14MM, PITCH=1.00MM) Symbol A A1 A2 b c D D1 E E1 e θ L L1 Min. 0.05 1.35 0.35 0.09 0° 0.70 Dimensions (mm) Nom. 1.40 16.60 BSC 14.00 BSC 16.60 BSC 14.00 BSC 1.00 BSC 3.5° 0.85 1.30 REF Max. 1.60 0.15 1.45 0.50 0.20 7° 1.00 Note: Refer to JEDEC MS-026 V1.5 15 June 2010 PT6324 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.5 16 June 2010