Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 LMZ22005 5-A SIMPLE SWITCHER® Power Module With 20-V Maximum Input Voltage 1 Features 2 Applications • • • • • • 1 • • • • • • • • • Integrated Shielded Inductor Simple PCB Layout Frequency Synchronization Input (650 kHz to 950 kHz) Flexible Start-up Sequencing Using External Soft-Start, Tracking and Precision Enable Protection Against Inrush Currents and Faults Such as Input UVLO and Output Short Circuit Junction Temperature Range –40°C to 125°C Single Exposed Pad for Easy Mounting and Manufacturing Fast Transient Response for Powering FPGAs and ASICs Fully Enabled for WEBENCH® Power Designer Pin Compatible With LMZ23605/LMZ23603/LMZ22003 Electrical Specifications – 30-W Maximum Total Output Power – Up to 5-A Output Current – Input Voltage Range 6 V to 20 V – Output Voltage Range 0.8 V to 6 V – Efficiency up to 92% Performance Benefits – High Efficiency Reduces System Heat Generation – Tested to EN55022 Class B(1) – Low Component Count, Only 5 External Components – Low Output Voltage Ripple – Uses PCB as Heat Sink, No Airflow Required (1) • Point-of-load Conversions from 12V Input Rail Time-Critical Projects Space Constrained/High Thermal Requirement Applications Negative Output Voltage Applications (see AN-2027 SNVA425) 3 Description The LMZ22005 SIMPLE SWITCHER® power module is an easy-to-use step-down DC-DC solution capable of driving up to 5-A load. The LMZ22005 is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ22005 can accept an input voltage rail between 6 V and 20 V and can deliver an adjustable and highly accurate output voltage as low as 0.8 V. The LMZ22005 only requires two external resistors and three external capacitors to complete the power solution. The LMZ22005 is a reliable and robust design with the following protection features: thermal shutdown, input undervoltage lockout, output overvoltage protection, short circuit protection, output current limit, and the device allows start-up into a prebiased output. The sync input allows synchronization over the 650- to 950-kHz switching frequency range. Device Information(1)(2) PART NUMBER PACKAGE LMZ22005 NDW (7) BODY SIZE (NOM) 10.16 mm × 9.85 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Peak reflow temperature equals 245°C. See SNAA214 for more details. EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2125 SNVA473 and layout for information on device under test. Vin = 12 V, Vo = 3.3 V, Io = 5 A Simplified Application Schematic Efficiency 5-V Output at 25°C Ambient 100 90 VOUT @ 5A RFBT Enable CIN See Table CSS 22 PF 0.47 PF RFBB See Table Co 220 PF EFFICIENCY (%) VOUT SS/TRK FB PGND EN AGND VIN VIN SYNC LMZ22005 80 70 60 50 9 VIn 12 Vin 20 Vin 40 0 1 2 3 4 OUTPUT CURRENT (A) 5 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 14 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 14 14 14 16 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Application ................................................. 17 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 23 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Examples................................................... Power Dissipation and Thermal Considerations ... Power Module SMT Guidelines ............................ 23 23 25 26 11 Device and Documentation Support ................. 27 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 27 27 12 Mechanical, Packaging, and Orderable Information ........................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (October 2013) to Revision J • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Changes from Revision H (March 2013) to Revision I Page • Changed 10 mils................................................................................................................................................................... 23 • Changed 10 mils................................................................................................................................................................... 25 • Added Power Module SMT Guidelines................................................................................................................................. 26 2 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 5 Pin Configuration and Functions NDW Package 7-Pin Top View PGND/EP Connect to AGND VOUT SS/TRK FB AGND EN SYNC VIN 7 6 5 4 3 2 1 Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 4 Ground Analog Ground — Reference point for all stated voltages. Must be externally connected to EP/PGND. EN 3 Analog Enable — Input to the precision enable comparator. Rising threshold is 1.279 V typical. Once the module is enabled, a 20-µA source current is internally activated to accommodate programmable hysteresis. FB 5 Analog Feedback — Internally connected to the regulation, overvoltage, and short circuit comparators. The regulation reference point is 0.796 V at this input pin. Connect the feedback resistor divider between the output and AGND to set the output voltage. PGND — Ground Exposed Pad / Power Ground Electrical path for the power circuits within the module. — NOT Internally connected to AGND / pin 4. Used to dissipate heat from the package during operation. Must be electrically connected to pin 4 external to the package. SS/TRK 6 Analog Soft-Start/Track — To extend the 1.6-ms internal soft-start connect an external soft -start capacitor. For tracking connect to an external resistive divider connected to a higher priority supply rail. See Design Steps. SYNC 2 Analog Sync Input — Apply a CMOS logic level square wave whose frequency is between 650 kHz and 950 kHz to synchronize the PWM operating frequency to an external frequency source. When not using synchronization connect to ground. The module free running PWM frequency is 812 kHz (typical) VIN 1 Power Supply input — Nominal operating range is 6 V to 20 V. A small amount of internal capacitance is contained within the package assembly. Additional external input capacitance is required between this pin and exposed pad (PGND). VOUT 7 Power Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and exposed pad. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 3 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT VIN to PGND –0.3 24 V EN, SYNC to AGND –0.3 5.5 V SS/TRK, FB to AGND –0.3 2.5 V AGND to PGND –0.3 0.3 V Junction temperature 150 °C Peak reflow case temperature (30 sec) 245 °C 150 °C Storage temperature, Tstg (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. For soldering specifications, refer to the following document: SNOA549 6.2 ESD Ratings Electrostatic discharge V(ESD) (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN EN, SYNC Operation junction temperature MIN MAX 6 20 UNIT V 0 5 V –40 125 °C 6.4 Thermal Information LMZ22005 THERMAL METRIC (1) NDW UNIT 7 PINS Junction-to-ambient thermal resistance (2) RθJA RθJC(top) (1) (2) 4 Junction-to-case (top) thermal resistance 4-layer Evaluation Printed-Circuit-Board, 60 vias, No air flow 19.3 2-layer JEDEC Printed-Circuit-Board, No air flow 21.5 No air flow 1.9 °C/W °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Theta JA measured on a 3.5-in × 3.5-in 4-layer board, with 3-oz. copper on outer layers and 2-oz. copper on inner layers, sixty thermal vias, no air flow, and 1-W power dissipation. Refer to application note layout diagrams. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 6.5 Electrical Characteristics Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VOUT = 3.3 V. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT SYSTEM PARAMETERS ENABLE CONTROL VEN EN threshold trip point VEN-HYS EN input hysteresis current VEN rising, TJ = 25°C VEN rising, TJ = –40°C to +125°C 1.279 1.1 VEN > 1.279 V 1.458 21 V µA SOFT-START ISS SS source current tSS Internal soft-start interval VSS = 0 V, TJ = 25°C VSS = 0 V, TJ = –40°C to +125°C 50 40 60 1.6 µA ms CURRENT LIMIT ICL Current limit threshold DC average, TJ = –40°C to +125°C 5.4 Sync input connected to ground. 711 A INTERNAL SWITCHING OSCILLATOR fosc Free-running oscillator frequency fsync Synchronization range VIL-sync Synchronization logic zero amplitude Relative to AGND, TJ = –40°C to +125°C VIH-sync Synchronization logic one amplitude Relative to AGND, TJ = –40°C to +125°C Sync dc Synchronization duty cycle range Dmax Maximum Duty Factor 812 650 914 kHz 950 kHz 0.4 V 1.5 15% V 50% 85% 83% REGULATION AND OVERVOLTAGE COMPARATOR VSS >+ 0.8 V, IO = 3 A, TJ = 25°C VFB In-regulation feedback voltage VFB-OV Feedback overvoltage protection threshold IFB Feedback input bias current IQ Non-switching input current ISD Shutdown quiescent current VSS >+ 0.8 V, IO = 3 A, TJ = –40°C to +125°C 0.796 0.776 0.816 V 0.86 V 5 nA VFB = 0.86 V 2.6 mA VEN = 0 V 70 μA THERMAL CHARACTERISTICS TSD Thermal shutdown Rising 165 °C TSD-HYST Thermal shutdown hysteresis Falling 15 °C 9 mVPP PERFORMANCE PARAMETERS (3) ΔVO Output voltage ripple Cout = 220 µF with 7 mΩ ESR + 100 µF X7R + 2 x 0.047 µF BW at 20 MHz ΔVO/ΔVIN Line regulation VIN = 12 V to 20 V, IO= 0.001 A ΔVO/ΔIOUT Load regulation VIN = 12 V, IO= 0.001 A to 3 A η Peak efficiency VIN = 12 V, VO = 3.3 V, IO = 1 A 86% η Full load efficiency VIN = 12 V VO = 3.3 V, IO = 3 A 81.5% (1) (2) (3) ±0.02% 1 mV/A Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25°C and represent the most likely parametric norm. Refer to BOM in Table 1. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 5 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com 6.6 Typical Characteristics 100 6 90 5 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section. 80 70 60 50 0 1 2 3 4 OUTPUT CURRENT (A) 0 0 6 90 5 80 70 60 0 1 2 3 4 OUTPUT CURRENT (A) 3 2 0 0 90 5 DISSIPATION (W) 6 80 70 60 1 2 3 4 OUTPUT CURRENT (A) 5 20 Vin 12 Vin 9 Vin 6 Vin 4 3 2 1 9 Vin 12 Vin 20 Vin 0 1 2 3 4 OUTPUT CURRENT (A) Figure 4. Dissipation 5-V Output at 25°C Ambient 100 40 20 Vin 12 Vin 9 Vin 4 5 Figure 3. Efficiency 5-V Output at 25°C Ambient 50 5 1 9 VIn 12 Vin 20 Vin 40 1 2 3 4 OUTPUT CURRENT (A) Figure 2. Dissipation 6-V Output at 25°C Ambient DISSIPATION (W) EFFICIENCY (%) 2 100 50 EFFICIENCY (%) 3 5 Figure 1. Efficiency 6-V Output at 25°C Ambient 0 5 Figure 5. Efficiency 3.3-V Output at 25°C Ambient 6 4 1 10 Vin 12 Vin 20 Vin 40 20 Vin 12 Vin 10 Vin 0 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 6. Dissipation 3.3-V Output at 25°C Ambient Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 Typical Characteristics (continued) 90 6 80 5 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section. 70 60 50 6 Vin 9 Vin 12 Vin 20 Vin 40 30 0 1 2 3 4 OUTPUT CURRENT (A) 2 0 5 0 6 80 5 70 60 50 6 Vin 9 Vin 12 Vin 20 Vin 0 1 2 3 4 OUTPUT CURRENT (A) 3 2 0 5 0 5 DISSIPATION (W) 75 65 55 45 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 10. Dissipation 1.8-V Output at 25°C Ambient 6 6 Vin 9 Vin 12 Vin 20 Vin 20 Vin 12 Vin 9 Vin 6 Vin 4 3 2 1 0 25 1 2 3 4 OUTPUT CURRENT (A) 20 Vin 12 Vin 9 Vin 6 Vin 4 85 0 5 1 Figure 9. Efficiency 1.8-V Output at 25°C Ambient 35 1 2 3 4 OUTPUT CURRENT (A) Figure 8. Dissipation 2.5-V Output at 25°C Ambient DISSIPATION (W) EFFICIENCY (%) 3 90 30 EFFICIENCY (%) 4 1 Figure 7. Efficiency 2.5-V Output at 25°C Ambient 40 20 Vin 12 Vin 9 Vin 6 Vin 5 Figure 11. Efficiency 1.5-V Output at 25°C Ambient 0 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 12. Dissipation 1.5-V Output at 25°C Ambient Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 7 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) 80 6 70 5 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section. 60 50 40 6 Vin 9 Vin 12 Vin 20 Vin 30 20 0 0 0 6 70 5 60 50 40 6 Vin 9 Vin 12 Vin 20 Vin 0 1 2 3 4 OUTPUT CURRENT (A) 3 2 0 5 0 5 DISSIPATION (W) 60 50 40 30 6 Vin 9 Vin 12 Vin 20 Vin* 1 2 3 4 OUTPUT CURRENT (A) 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 16. Dissipation 1-V Output at 25°C Ambient 6 0 20 Vin 12 Vin 9 VIn 6 Vin 4 70 10 5 1 Figure 15. Efficiency 1-V Output at 25°C Ambient 20 1 2 3 4 OUTPUT CURRENT (A) Figure 14. Dissipation 1.2-V Output at 25°C Ambient DISSIPATION (W) EFFICIENCY (W) 2 80 20 EFFICIENCY (%) 3 5 Figure 13. Efficiency 1.2-V Output at 25°C Ambient 20 Vin* 12 Vin 9 Vin 6 Vin 4 3 2 1 0 5 Figure 17. Efficiency 0.8-V Output at 25°C Ambient 8 4 1 1 2 3 4 OUTPUT CURRENT (A) 30 20 Vin 12 Vin 9 Vin 6 Vin 0 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 18. Dissipation 0.8-V Output at 25°C Ambient Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 Typical Characteristics (continued) 100 6 90 5 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section. 80 70 60 50 0 1 2 3 4 OUTPUT CURRENT (A) 2 0 0 100 6 90 5 80 70 60 50 0 1 2 3 4 OUTPUT CURRENT (A) 3 2 0 0 80 5 DISSIPATION (W) 6 70 60 50 1 2 3 4 OUTPUT CURRENT (A) 5 20 Vin 12 Vin 9 Vin 4 3 2 1 9 Vin 12 Vin 20 Vin 0 1 2 3 4 OUTPUT CURRENT (A) Figure 22. Dissipation 5-V Output at 85°C Ambient 90 30 20 Vin 12 Vin 9 Vin 4 5 Figure 21. Efficiency 5-V Output at 85°C Ambient 40 5 1 9 Vin 12 Vin 20 Vin 40 1 2 3 4 OUTPUT CURRENT (A) Figure 20. Dissipation 6-V Output at 85°C Ambient DISSIPATION (W) EFFICIENCY (%) 3 5 Figure 19. Efficiency 6-V Output at 85°C Ambient EFFICIENCY (%) 4 1 10 Vin 12 Vin 20 Vin 40 20 Vin 12 Vin 10 Vin 0 5 Figure 23. Efficiency 3.3-V Output at 85°C Ambient 0 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 24. Dissipation 3.3-V Output at 85°C Ambient Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 9 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) 90 6 80 5 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section. 70 60 50 6 Vin 9 Vin 12 Vin 20 Vin 40 30 0 1 2 3 4 OUTPUT CURRENT (A) 0 5 0 80 5 70 60 50 6 Vin 9 Vin 12 Vin 20 Vin 1 2 3 4 OUTPUT CURRENT (A) 3 2 0 5 0 5 DISSIPATION (W) 70 60 50 40 6 Vin 9 Vin 12 Vin 20 Vin 1 2 3 4 OUTPUT CURRENT (A) 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 28. Dissipation 1.8-V Output at 85°C Ambient 6 0 20 Vin 12 Vin 9 Vin 6 Vin 4 80 20 5 1 Figure 27. Efficiency 1.8-V Output at 85°C Ambient 30 1 2 3 4 OUTPUT CURRENT (A) Figure 26. Dissipation 2.5-V Output at 85°C Ambient DISSIPATION (W) EFFICIENCY (%) 2 6 0 EFFICIENCY (%) 3 90 30 20 Vin 12 Vin 9 Vin 6 Vin 4 3 2 1 0 5 Figure 29. Efficiency 1.5-V Output at 85°C Ambient 10 4 1 Figure 25. Efficiency 2.5-V Output at 85°C Ambient 40 20 Vin 12 Vin 9 Vin 6 Vin 0 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 30. Dissipation 1.5-V Output at 85°C Ambient Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 Typical Characteristics (continued) 80 6 70 5 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section. 60 50 40 6 Vin 9 Vin 12 Vin 20 Vin 30 20 0 2 5 0 75 6 65 5 55 45 35 6 Vin 9 Vin 12 Vin 20 Vin 0 20 Vin 12 Vin 9 Vin 6 Vin 4 3 2 0 1 2 3 4 OUTPUT CURRENT (A) 5 0 6 DISSIPATION (W) 40 6 Vin 9 Vin 12 Vin 20 Vin* 0 1 2 3 4 OUTPUT CURRENT (A) 5 20 Vin* 12 Vin 9 Vin 6 Vin 5 60 50 1 2 3 4 OUTPUT CURRENT (A) Figure 34. Dissipation 1-V Output at 85°C Ambient 70 20 5 1 Figure 33. Efficiency 1-V Output at 85°C Ambient 30 1 2 3 4 OUTPUT CURRENT (A) Figure 32. Dissipation 1.2-V Output at 85°C Ambient DISSIPATION (W) EFFICIENCY (%) 3 0 1 2 3 4 OUTPUT CURRENT (A) 15 EFFICIENCY (%) 4 1 Figure 31. Efficiency 1.2-V Output at 85°C Ambient 25 20 Vin 12 Vin 9 Vin 6 Vin 4 3 2 1 0 5 Figure 35. Efficiency 0.8-V at 85°C Ambient 0 1 2 3 4 OUTPUT CURRENT (A) 5 Figure 36. Dissipation 0.8-V Output at 85°C Ambient Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 11 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section. 6 MAXIMUM OUTPUT CURRENT (A) MAXIMUM OUTPUT CURRENT (A) 6 5 4 3 2 1 JA=12°C/W 0 4 3 2 1 JA = 12 °C/W 0 30 40 50 60 70 80 90 100 110 120 130 AMBIENT TEMPERATURE (°C) VIN = 12 V, VOUT = 5 V 30 40 50 60 70 80 90 100 110 120 130 AMBIENT TEMPERATURE (°C) VIN= 12 V, VOUT = 3.3 V Figure 37. Thermal Derating NORMALLIZED OUTPUT VOLTAGE (V/V) 5 Figure 38. Thermal Derating 1.002 1.001 1.000 0.999 9 Vin 12 Vin 20 Vin 0.998 0 1 2 3 4 OUTPUT CURRENT (A) 5 10 mV/Div 500 ns/Div 12 VIN 3.3 VO at 5 A, BW = 20 MHz VOUT = 3.3 V Figure 40. Output Ripple Figure 39. Normalized — Line and Load Regulation 2A/Div 10 mV/Div 500 ns/Div 12 VIN 3.3 VO at 5 A BW = 250 MHz Figure 41. Output Ripple 12 100 mV/Div 500 µs/Div 12 VIN 3.3 VO 0.5- to 5-A Step Figure 42. Transient Response From Evaluation Board Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle skipping at light loads resulting is slightly higher output ripple – See Design Steps section. 9 8 CURRENT (A) 7 Output Current 6 5 4 3 2 Input Current 1 0 5 10 15 INPUT VOLTAGE (V) 20 Figure 43. Short Circuit Current vs Input Voltage Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 13 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com 7 Detailed Description 7.1 Overview The architecture used is an internally compensated emulated peak current mode control, based on a monolithic synchronous SIMPLE SWITCHER core capable of supporting high load currents. The output voltage is maintained through feedback compared with an internal 0.8-V reference. For emulated peak current-mode, the valley current is sampled on the down-slope of the inductor current. This is used as the DC value of current to start the next cycle. The primary application for emulated peak current-mode is high input voltage to low output voltage operating at a narrow duty cycle. By sampling the inductor current at the end of the switching cycle and adding an external ramp, the minimum ON-time can be significantly reduced, without the need for blanking or filtering which is normally required for peak current-mode control. 7.2 Functional Block Diagram Linear Regulator 2M VIN 1 3 3 CIN EN CBST CINint 1 SYNC CSS 2 800 kHz PWM SS/TRK 3.3 uH VOUT VREF 3 RFBT CO FB 1 2 Comp RFBB AGND Regulator IC EP/ PGND Internal Passives 7.3 Feature Description 7.3.1 Synchronization Input The PWM switching frequency can be synchronized to an external frequency source. If this feature is not used, connect this input either directly to ground, or connect to ground through a resistor of 1.5 kΩ or less. The allowed synchronization frequency range is 650 kHz to 950 kHz. The typical input threshold is 1.4-V transition level. Ideally the input clock must overdrive the threshold by a factor of 2, so direct drive from 3.3-V logic through a 1.5kΩ Thevenin source resistance is recommended. NOTE Applying a sustained logic 1 corresponds to zero Hz PWM frequency and will cause the module to stop switching. 7.3.2 Output Overvoltage Protection If the voltage at FB is greater than the 0.86-V internal reference the output of the error amplifier is pulled toward ground causing VO to fall. 14 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 Feature Description (continued) 7.3.3 Current Limit The LMZ22005 is protected by both low-side (LS) and high-side (HS) current limit circuitry. The LS current limit detection is carried out during the OFF-time by monitoring the current through the LS synchronous MOSFET. Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 5.4 A (typical) the current limit comparator disables the start of the next switching period. Switching cycles are prohibited until current drops below the limit. NOTE DC current limit is dependent on duty cycle as illustrated in the graph in the Typical Characteristics section. The HS current limit monitors the current of top side MOSFET. Once HS current limit is detected (7 A typical) , the HS MOSFET is shutoff immediately, until the next cycle. Exceeding HS current limit causes VO to fall. Typical behavior of exceeding LS current limit is that fSW drops to 1/2 of the operating frequency. 7.3.4 Thermal Protection The junction temperature of the LMZ22005 must not be allowed to exceed its maximum ratings. Thermal protection is implemented by an internal thermal shutdown circuit which activates at 165°C (typical) causing the device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for accidental device overheating. When the junction temperature falls back below 150°C (typical hysteresis = 15°C) the SS pin is released, VO rises smoothly, and normal operation resumes. Applications requiring maximum output current especially those at high input voltage may require additional derating at elevated temperatures. 7.3.5 Prebiased Start-Up The LMZ22005 will properly start up into a prebiased output. This start-up situation is common in multiple rail logic applications where current paths may exist between different power rails during the start-up sequence. Figure 44 shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.5-V prebias rising to 3.3 V. Rise time determined by CSS, trace three. Figure 44. Prebiased Start-Up Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 15 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com 7.4 Device Functional Modes 7.4.1 Discontinuous And Continuous Conduction Modes At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the critical conduction point, it will operate in continuous conduction mode (CCM). In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the OFF-time. When operating in DCM, inductor current is maintained to an average value equaling IOUT. Inductor current exhibits normal behavior for the emulated current mode control method used. Output voltage ripple typically increases during this mode of operation. Figure 45 is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes. VIN = 12 V, VO = 3.3 V, IO = 3 A / 0.3 A 2 μs/div Figure 45. CCM and DCM Operating Modes 16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMZ22005 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 5 A. The following design procedure can be used to select components for the LMZ22005. Alternately, the WEBENCH software may be used to generate complete designs. When generating a design, the WEBENCH software uses iterative design procedure and accesses comprehensive databases of components. Please go to www.ti.com for more details. 8.2 Typical Application U1 7V to 20V PGND/EP VIN Enable VOUT SS 3.3VO @ 5A 7 AGND EN FB 6 5 4 3 1 CIN6 OPT 150 PF 2 VIN + SYNC LMZ22005TZ RENT 42.2k SYNC D1 OPT 5.1V RENB 12.7k RENH OPT 100: CIN2,3 10 PF CIN1,5 0.047 PF RSNOPT 1.50 k: RFBT 3.32k CSS 0.47 PF RFBB 1.07k RFRA OPT 23.7: CO1,6 0.047 PF CO2 100 PF OPT + CO5 220 PF Figure 46. Typical Application Schematic 8.2.1 Design Requirements For this example the following application parameters exist: • VIN Range = Up to 20 V • VOUT = 0.8 V to 6 V • IOUT = 5 A Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 17 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com Typical Application (continued) 8.2.2 Detailed Design Procedure 8.2.2.1 Design Steps The LMZ22005 is fully supported by WEBENCH which offers: component selection, electrical and thermal simulations. Additionally there is are evaluation and demonstration boards that may be used a starting point for design. The following list of steps can be used to quickly design the LMZ22005 application. 1. 2. 3. 4. 5. 6. Select minimum operating VIN with enable divider resistors Program VO with resistor divider selection Select CO Select CIN Determine module power dissipation Layout PCB for required thermal performance 8.2.2.2 Enable Divider, RENT, RENB and RENH Selection Internal to the module is a 2-MΩ pullup resistor connected from VIN to Enable. For applications not requiring precision undervoltage lockout (UVLO), the Enable input may be left open circuit and the internal resistor will always enable the module. In such case, the internal UVLO occurs typically at 4.3 V (VIN rising). In applications with separate supervisory circuits Enable can be directly interfaced to a logic source. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ22005 output rail. Enable provides a precise 1.279-V threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as VIN. Additionally there is 21 μA (typical) of switched offset current allowing programmable hysteresis. See Figure 47. The function of the enable divider is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of programmable UVLO. The two resistors must be chosen based on the following ratio: RENT / RENB = (VIN UVLO / 1.279 V) – 1 (1) The LMZ22005 typical application shows 12.7 kΩ for RENB and 42.2 kΩ for RENT resulting in a rising UVLO of 5.46 V. NOTE A midpoint 5.1-V Zener clamp is present to allow setting UVLO to cover an extended range of operation. The Zener clamp is not required if the target application prohibits the maximum Enable input voltage from being exceeded. Additional enable voltage hysteresis can be added with the inclusion of RENH. It may be possible to select values for RENT and RENB such that RENH is a value of zero allowing it to be omitted from the design. Rising threshold can be calculated as follows: VEN(rising) = 1.279 ( 1 + RENT|| 2 meg/ RENB) (2) Whereas falling threshold level can be calculated using: VEN(falling) = VEN(rising) – 21 µA ( RENT|| 2 meg || RENTB + RENH ) 18 Submit Documentation Feedback (3) Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 Typical Application (continued) P/O LMZ22005 INT-VCC (5V) VIN 21 uA RENT 42.2k RENH 2.0M ENABLE RUN 100Ö RENB 12.7k 5.1V 1.279V Figure 47. Enable Input Detail 8.2.2.3 Output Voltage Selection Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of the divider is connected to the FB input. The regulated output voltage determined by the external divider resistors RFBT and RFBB is: VO = 0.8 V × (1 + RFBT / RFBB) (4) Rearranging terms; the ratio of the feedback resistors for a desired output voltage is: RFBT / RFBB = (VO / 0.796 V) – 1 (5) These resistors must generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ. For VO = 0.8 V the FB pin can be connected to the output directly and RFBB can be omitted. Table 1 lists the values for RFBT , and RFBB. Table 1. Typical Application Bill of Materials REF DES DESCRIPTION CASE SIZE MANUFACTURER U1 SIMPLE SWITCHER PFM-7 Texas Instruments MANUFACTURER P/N LMZ22005TZ Cin1,5 0.047 µF, 50 V, X7R 1206 Yageo America CC1206KRX7R9BB473 Cin2,3 10 µF, 50 V, X7R 1210 Taiyo Yuden UMK325BJ106MM-T Cin6 (OPT) CAP, AL, 150 µF, 50 V Radial G Panasonic EEE-FK1H151P CO1,6 0.047 µF, 50 V, X7R 1206 Yageo America CC1206KRX7R9BB473 CO2 (OPT) 100 µF, 6.3 V, X7R 1210 TDK C3225X5R0J107M CO5 220 μF, 6.3 V, SP-Cap (7343) Panasonic EEF-UE0J221LR RFBT 3.32 kΩ 0805 Panasonic ERJ-6ENF3321V RFBB 1.07 kΩ 0805 Panasonic ERJ-6ENF1071V RSN (OPT) 1.50 kΩ 0805 Vishay Dale CRCW08051K50FKEA RENT 42.2 kΩ 0805 Panasonic ERJ-6ENF4222V RENB 12.7 kΩ 0805 Panasonic ERJ-6ENF1272V RFRA(OPT) 23.7Ω 0805 Vishay Dale CRCW080523R7FKEA RENH 100 Ω 0805 Vishay Dale CRCW0805100RFKEA CFF 180 pF, ±10%, C0G, 50 V 0805 TDK 08055A181JAT2A CSS 047 μF, ±10%, X7R, 16 V 0805 AVX 0805YC474KAT2A D1(OPT) 5.1 V, 0.5 W SOD-123 Diodes Inc. MMSZ5231BS-7-F Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 19 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com 8.2.2.4 Soft-start Capacitor Selection Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time. Upon turnon, after all UVLO conditions have been passed, an internal 2-ms circuit slowly ramps the SS/TRK input to implement internal soft-start. If 1.6 ms is an adequate turnon time then the CSS capacitor can be left unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input. Soft-start duration is given by the formula: tSS = VREF × CSS / Iss = 0.796 V × CSS / 50 µA (6) This equation can be rearranged as follows: CSS = tSS × 50 μA / 0.796 V (7) Using a 0.22-μF capacitor results in 3.5-ms typical soft-start duration; and 0.47 μF results in 7.5-ms typical. 0.47 μF is a recommended initial value. Once the soft-start input exceeds 0.796 V the output of the power stage will be in regulation and the 50-μA current is deactivated. The following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal current sink. • • • The Enable input being pulled low Thermal shutdown condition Internal VCC UVLO (Approx 4.3V input to VIN) 8.2.2.5 Tracking Supply Divider Option The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the 3.3-V system rail) where the slave module output voltage is lower than that of the master. Proper configuration allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails during ramp-up is small (that is, <0.15 V typical). The values for the tracking resistive divider must be selected such that the effect of the internal 50-µA current source is minimized. In most cases the ratio of the tracking divider resistors is the same as the ratio of the output voltage setting divider. Proper operation in tracking mode dictates the soft-start time of the slave rail be shorter than the master rail; a condition that is easy satisfy because the CSS cap is replaced by RTKB. The tracking function is only supported for the power up interval of the master supply; once the SS/TRK rises past 0.8V the input is no longer enabled and the 50-µA internal current source is switched off. 3.3V Master 2.5Vout Int VCC 50 PA Rtkt 226 Rfbt 2.26k SS/TRK FB Rtkb 107 Rfbb 1.07k Figure 48. Tracking Option Input Detail 8.2.2.6 CO Selection None of the required CO output capacitance is contained within the module. A minimum value of 200 μF is required based on the values of internal compensation in the error amplifier. Low ESR tantalum, organic semiconductor or specialty polymer capacitor types are recommended for obtaining lowest ripple. The output capacitor CO may consist of several capacitors in parallel placed in close proximity to the module. The output capacitor assembly must also meet the worst case minimum ripple current rating of 0.5 × ILRP-P, as calculated in Equation 14. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. Loop response verification is also valuable to confirm closed loop behavior. 20 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 For applications with dynamic load steps; the following equation provides a good first pass approximation of CO for load transient requirements. Where VO-Tran is 100 mV on a 3.3-V output design. CO ≥ IO-Tran / (VO-Tran – ESR × IO-Tran) × (Fsw / VO) (8) Solving: CO ≥ 4.5 A / (0.1 V – 0.007 × 4.5 A) × ( 800000 Hz / 3.3 V) ≥ 271 μF (9) NOTE The stability requirement for 200-µF minimum output capacitance will take precedence. One recommended output capacitor combination is a 220-µF, 7-mΩ ESR specialty polymer cap in parallel with a 100-µF, 6.3-V X5R ceramic. This combination provides excellent performance that may exceed the requirements of certain applications. Additionally some small ceramic capacitors can be used for high-frequency EMI suppression. 8.2.2.7 CIN Selection The LMZ22005 module contains only a small amount of input capacitance. Additional input capacitance is required external to the module to handle the input ripple current of the application. The input capacitor can be several capacitors in parallel. This input capacitance must be located in very close proximity to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Input ripple current rating is dictated by the equation: I(CIN(RMS)) ≊ 1 / 2 × IO × SQRT (D / 1 – D) where • D ≊ VO / VIN (10) As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when VIN = 2 × VO. Recommended minimum input capacitance is 22-µF X7R (or X5R) ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. TI recommends to pay attention to the voltage and temperature derating of the capacitor selected. The ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this parameter. If the system design requires a certain minimum value of peak-to-peak input ripple voltage (ΔVIN) be maintained then the following equation may be used. CIN ≥ IO × D × (1 – D) / fSW-CCM × ΔVIN (11) If ΔVIN is 1% of VIN for a 12-V input to 3.3-V output application this equals 120 mV and fSW = 812 kHz. CIN ≥ 5 A × 3.3 V / 12 V × (1 – 3.3 V / 12 V) / (812000 × 0.120 V) ≥ 10.2 μF (12) Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. The LMZ22005 typical applications schematic recommends a 150-μF 50-V aluminum capacitor for this function. There are many situations where this capacitor is not necessary. 8.2.2.8 Discontinuous And Continuous Conduction Modes Selection The approximate formula for determining the DCM/CCM boundary is as follows: IDCB ≊ VO × (VIN– VO) / (2 × 3.3 μH × fSW(CCM) × VIN) (13) The inductor internal to the module is 3.3 μH. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (ILR). ILR can be calculated with: ILR P-P = VO× (VIN– VO) / (3.3 µH × fSW × VIN) where • • VIN is the maximum input voltage And fSW is typically 812 kHz. (14) Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 21 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be determined. 8.2.3 Application Curves 100 5 MAXIMUM OUTPUT CURRENT (A) 6 90 4 DISSIPATION (W) EFFICIENCY (%) 80 70 60 3 50 40 2 30 20 1 10 0 0 0 1 2 3 4 OUTPUT CURRENT (A) 5 4 3 2 1 JA=12°C/W 0 5 30 40 50 60 70 80 90 100 110 120 130 AMBIENT TEMPERATURE (°C) VIN = 12 V, VOUT = 5 V VIN = 12 V, VOUT = 5 V Figure 49. Efficiency Figure 50. Thermal Derating Curve AMPLITUDE (dBV/m) 50 40 30 20 Class A Limit Class B Limit Horiz Peak Horiz Quasi-Peak 10 0 0 200 400 600 800 FREQUENCY (MHz) 1000 Figure 51. Radiated EMI (EN 55022) of Demo Board (See AN-2125) 9 Power Supply Recommendations The LMZ22005 device is designed to operate from an input voltage supply range between 6 V and 20 V. This input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the LMZ22005 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is more than a few inches from the LMZ22005, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice. 22 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 10 Layout 10.1 Layout Guidelines PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. A good example layout is shown in Figure 54. 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout as shown in Figure 52. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor (CIN1) is placed at a distance away from the LMZ22005. Therefore place CIN1 as close as possible to the LMZ22005 VIN and PGND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the PGND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Additionally provide the single point ground connection from pin 4 (AGND) to EP/PGND. 3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB, and the feed-forward capacitor CFF, must be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from RFBT, RFBB, and CFF must be routed away from the body of the LMZ22005 to minimize possible noise pickup. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 10 via array with a minimum via diameter of 8 mils thermal vias spaced 39 mils (1.0 mm). Ensure enough copper area is used for heatsinking to keep the junction temperature below 125°C. 10.2 Layout Examples VIN VO VOUT VIN High di/dt Cin1 CO1 GND Loop 1 Loop 2 Figure 52. Critical Current Loops to Minimize Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 23 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com Layout Examples (continued) Top View Thermal Vias GND GND EPAD 1 2 3 4 5 6 7 VIN EN SYNC FB GND VOUT SS CIN VIN RENT SYNC CSS RENB COUT VOUT RFBT CFF RFBB GND Plane Figure 53. PCB Layout Guide Figure 54. Top View Evaluation Board – See AN–2085 SNVA457 24 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 Layout Examples (continued) Figure 55. Bottom View Demonstration Board 10.3 Power Dissipation and Thermal Considerations When calculating module dissipation use the maximum input voltage and the average output current for the application. Many common operating conditions are provided in the characteristic curves such that less common applications can be derived through interpolation. In all designs, the junction temperature must be kept below the rated maximum of 125°C. For the design case of VIN = 12 V, VO = 3.3 V, IO = 5 A, and TAMB(MAX) = 85°C, the module must see a thermal resistance from case to ambient of less than: RθCA< (TJ-MAX – TA-MAX) / PIC-LOSS – RθJC (15) Given the typical thermal resistance from junction to case to be 1.9°C/W. Use the 85°C power dissipation curves in the Typical Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is 4.3W. RθCA = (125 – 85) / 4.3 W – 1.9 = 7.4 (16) To reach RθCA = 7.4, the PCB is required to dissipate heat effectively. With no airflow and no external heat-sink, a good estimate of the required board area covered by 2-oz. copper on both the top and bottom metal layers is: Board_Area_cm2 = 500°C x cm2/W / RθCA (17) As a result, approximately 67 square cm of 2-oz. copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad. Approximately sixty, 8 mils thermal vias spaced 39 mils (1.0 mm) apart connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout for SIMPLE SWITCHER power modules, refer to AN-2085 (SNVA457), AN2125 (SNVA437), AN-2020 (SNVA419) and AN-2026 (SNVA424). Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 25 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com 10.4 Power Module SMT Guidelines The recommendations below are for a standard module surface mount assembly • Land Pattern — Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads • Stencil Aperture – For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern – For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation • Solder Paste — Use a standard SAC Alloy such as SAC 305, type 3 or higher • Stencil Thickness — 0.125 to 0.15 mm • Reflow — Refer to solder paste supplier recommendation and optimized per board size and density • Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information • Maximum number of reflows allowed is one Figure 56. Sample Reflow Profile Table 2. Sample Reflow Profile Table 26 PROBE MAX TEMP (°C) REACHED MAX TEMP TIME ABOVE 235°C REACHED 235°C TIME ABOVE 245°C REACHED 245°C TIME ABOVE 260°C REACHED 260°C 1 242.5 6.58 0.49 6.39 2 242.5 7.10 0.55 6.31 0.00 – 0.00 – 0.00 7.10 0.00 3 241.0 7.09 0.42 6.44 – 0.00 – 0.00 – Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 LMZ22005 www.ti.com SNVS686J – MARCH 2011 – REVISED AUGUST 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support For developmental support, see the following: WEBENCH Tool, http://www.ti.com/webench 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: • AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, (SNVA425) • Absolute Maximum Ratings for Soldering, (SNOA549) • AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422) • AN-2085 LMZ23605/03, LMZ22005/03 Evaluation Board (SNVA457) • AN-2054 Evaluation Board for LM10000 - PowerWise AVS System Controller (SNVA437) • AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419) • AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424) • Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. SIMPLE SWITCHER is a registered trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Insturments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 27 LMZ22005 SNVS686J – MARCH 2011 – REVISED AUGUST 2015 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMZ22005 PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMZ22005TZ/NOPB ACTIVE TO-PMOD NDW 7 45 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 LMZ22005 LMZ22005TZE/NOPB ACTIVE TO-PMOD NDW 7 250 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 LMZ22005 LMZ22005TZX/NOPB ACTIVE TO-PMOD NDW 7 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 LMZ22005 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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