SP432 SIGNAL PROCESSING EXCELLENCE High Speed, Low Power Quad RS-422 Differential Line Receiver ■ Compatible with the EIA standard for RS-422 serial protocol ■ Quad Differential Line Receivers ■ Tri-state Output Control ■ 8ns Typical Receiver Propagation Delays ■ 60mV Typical Input Hysteresis ■ Single +3.3V to +5V Supply Operation ■ Common Receiver Enable Control ■ Compatibility with the industry standard 26LV32 and 26C32 ■ -7.0V to +7.0V Common-Mode Input Voltage Range DESCRIPTION The SP432 is a quad differential line receiver designed to meet the specifications of RS-422. The SP432 features Sipex's BiCMOS process allowing low power operational characteristics of CMOS technology while meeting all of the demands of the RS-422 serial protocol over 50Mbps under load. The RS-422 protocol allows up to 10 receivers to be connected to a multipoint bus transmission line. The SP432 features a receiver enable control common to all four receivers and a tri-state output with 6mA source and sink capability. Since the cabling can be as long as 4,000 feet, the RS-422 receivers of the SP432 are equipped with a wide (-7.0V to +7.0V) common-mode input voltage range to accomodate ground potential differences. RI1B 1 16 VCC RI1A 2 R01 3 15 RI4B 14 RI4A ENABLE 4 R02 5 RI2A 6 RI2B 7 GND 8 SP432 13 R04 12 ENABLE RI A RI B 4 4 RI A RI B 3 3 RI A RI B 2 2 RI A RI B 1 1 R04 R03 R02 R01 ENABLE ENABLE 11 R0 3 10 RI A 3 9 RI B 3 GND SP432DS/10 INPUTS VCC SP432 High Speed, Low Power Quad Differential Line Receiver 1 OUTPUTS © Copyright 1997 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC (SupplyVoltage).......................................................................+7.0V VCM (Common Mode Range)...........................................................±14V VDIFF (Differential Input Voltage)......................................................±14V VIN (Enable Input Voltage)..............................................................+7.0V TSTG (Storage Temperature Range)..............................-65°C to +150°C Lead Temperature (4sec)............................................................+260°C Maximum Current Per Output......................................................±25mA Storage Temperature....................................................-65°C to +150°C Power Dissipation Per Package 16-pin PDIP (derate 14.3mW/oC above +70oC)........................1150mW 16-pin NSOIC (derate 8.95mW/oC above +70oC).......................725mW ESD INPUTS VCC RI A RI B 4 4 RI A RI B 3 3 RI A RI B 2 2 RI A RI B 1 1 R04 R03 R02 R01 ENABLE ENABLE OUTPUTS GND Figure 1. SP432 Block Diagram SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 2 © Copyright 1997 Sipex Corporation SPECIFICATIONS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with Tamb = 25°C and all MIN and MAX limits apply across the recommended operating temperature range. DC PARAMETERS MIN. Supply Voltage, VCC 3.0 TYP. MAX. UNITS 5.5 Enable Input Rise or Fall Times 3 CONDITIONS V ns Input Electrical Characteristics Minimum Differential Input Voltage, VTH Input Resistance, RIN -200 35 +200 mV VOUT = VOH or VOL, -7V < VCM < +7V 5.0 8 10 KΩ VIN = -7V, +7V, other input = GND +1.25 +1.5 mA VIN = +10V, other input = GND -1.5 -2.5 mA VIN = -10V, other input = GND Input Current IIN IIN Minimum Enable HIGH Input Level Voltage, VIH 2.0 V Maximum Enable LOW Input Level Voltage, VIL 0.8 V ±1.0 µA VIN = VCC or GND Input Hysteresis, VHYST 60 mV VCM = 0V Quiescent Supply Current, ICC 8 TBD mA VCC = +5.0V, VDIF = +1V TBD mA VCC = +3.3V Maximum Enable Input Current, II Quiescent Supply Current, ICC Output Electrical Characteristics Minimum High Level Output Voltage, VOH 2.7 TBD V VCC = +3.0V, VDIFF = +1V, IOUT = -6.0mA Maximum Low Level Output Voltage, VOL 0.2 0.3 V VCC = +5.0V, VDIFF = -1V, IOUT = -6.0mA Maximum Tri-state Output Leakage Current, IOZ ±0.5 ±5.0 µA VOUT = VCC or GND, ENABLE = VIL, ENABLE = VIH SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 3 © Copyright 1997 Sipex Corporation SPECIFICATIONS (continued) Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V, Tamb = 25°C, tr < 6ns, tf < 6ns, and all MIN and MAX limits apply across the recommended operating temperature range. MIN. TYP. MAX. UNITS CONDITIONS AC PARAMETERS Propagation Delays Input to Output, tPLH, tPHL 7 TBD ns CL = 50pF, VDIFF = 2.5V, VCM = 0V, VCC = +5V 5 TBD ns CL = 50pF, VDIFF = 2.5V, VCM = 0V, VCC = +5V 10 TBD ns CL = 50pF, RL = 1000Ω, VDIFF = 2.5V, VCC = +5V 6 TBD ns CL = 50pF, RL = 1000Ω, VDIFF = 2.5V, VCC = +5V Output Rise and Fall Times, tRISE, tFALL Propagation Delay ENABLE to Output, tPLZ, tPHZ Propagation Delay ENABLE to Output, tPZL, tPZH SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 4 © Copyright 1997 Sipex Corporation AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS VCC S1 +2.5V INPUTS (V-) – (V+) V+ INPUT 0V -2.5V tPHL tPLH ttPHL PLH V- INPUT VOH 90% OUTPUT DEVICE UNDER TEST 90% CL 50% VOL 10% RL 10% tRISE tFALL CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. Figure 2. Propagation Delay ENABLE 3.0V ENABLE GND Figure 3. Test Circuit for Tri-State Outputs 1.3V 1.3V tPLZ tPZL VCC OUTPUT 50% VOL 0.5V VOH 0.5V OUTPUT 50% 0V tPHZ tPZH Figure 4. Tri-State Output Enable and Disable Waveforms SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 5 © Copyright 1997 Sipex Corporation DESCRIPTION The SP432 is a low-power quad differential line receiver designed for digital data transmission meeting Federal Standards 1020 and 1030 as well as the specifications of the EIA standard RS-422 protocol. The SP432 features Sipex's BiCMOS process allowing low power operational characteristics of CMOS technology while meeting all of the demands of the RS-422 serial protocol to at least 50Mbps under load in harsh environments. The SP432 accepts RS-422 levels and translates these into TTL or CMOS input levels. The SP432 features active HIGH and active LOW receiver enable controls common to all four receiver channels. A logic HIGH on the ENABLE pin (pin 4) or a logic LOW on the ENABLE pin (pin 12) will enable the differential receiver outputs. A logic LOW on the ENABLE pin (pin 4) or a logic HIGH on the ENABLE pin (pin 12) will tri-state the receiver outputs. The RS-422 standard is ideal for multi-drop applications and for long-distance communication. The RS-422 protocol allows up to 10 drivers to be connected to a data bus, making it an ideal choice for multi-drop applications. Since the cabling can be as long as 4,000 feet, the RS-422 receivers have an input sensitivity of 200mV over the wide (-7.0V to +7.0V) common mode range to accommodate ground potential differences. Internal pull-up and pull-down resistors prevent output oscillation on unused channels. Because the RS-422 is a differential interface, data is virtually immune to noise in the transmission line. The RS-422 line receivers feature high source and sink current capability. All receivers are internally protected against short circuits on their inputs. The receivers feature tri-state outputs with 6mA source and sink capability. The typical receiver propagation delay is 8ns (30ns max). ENABLE ENABLE Input Output LOW HIGH don't care high-Z HIGH don't care VID > VTH (max) HIGH HIGH don't care VID < VTH (min) LOW don't care LOW VID > VTH (max) HIGH don't care LOW VID < VTH (min) LOW HIGH don't care open HIGH don't care LOW open HIGH To minimize reflections, the multipoint bus transmission line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possible. ENABLE DATA DATA OUTPUT *RT is optional although highly recommended to reduce reflection. Figure 5. Truth Table, Enable/Disable Function Common to all Four RS-422 Receivers SP432DS/10 *RT Figure 6. Two-Wire Balanced Systems, RS-422 SP432 High Speed, Low Power Quad Differential Line Receiver 6 © Copyright 1997 Sipex Corporation RI1B 1 RI1A 2 R01 3 ENABLE 4 R02 5 RI2A 6 RI2B 7 GND 8 16 VCC SP432 15 RI4B 14 RI4A 13 R04 12 ENABLE 11 R0 3 10 RI A 3 9 RI B 3 PINOUT PIN ASSIGNMENTS Pin 1 — RI1B — Inverted RS-422 receiver input. Pin 10 — RI3A — Non-inverted RS-422 receiver input. Pin 2 — RI1A — Non-inverted RS-422 receiver input. Pin 11 — R03 — TTL receiver output. Pin 3 — R01 — TTL receiver output. Pin 12 — ENABLE — Receiver input enable, active LOW. Pin 4 — ENABLE — Receiver input enable, active HIGH. Pin 13 — R04 — TTL receiver output. Pin 5 — R02 — TTL receiver output. Pin 14 — RI4A — Non-inverted RS-422 receiver input. Pin 6 — RI2A — Non-inverted RS-422 receiver input. Pin 15 — RI4B — Inverted RS-422 receiver input. Pin 7 — RI2B — Inverted RS-422 receiver input. Pin 16 — VCC — +3.0V to +5.5V power supply. Pin 8 — GND — Ground. Pin 9 — RI3B — Inverted RS-422 receiver input. SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 7 © Copyright 1997 Sipex Corporation TYPICAL PERFORMANCE CHARACTERISTICS TBD TBD Figure 7. Differential Propagation Delay Vs. Temperature Figure 8. Differential Propagation Delay Vs. Power Supply Voltage TBD TBD Figure 9. Differential Skew Vs. Temperature SP432DS/10 Figure 10. Differential Skew Vs. Power Supply Voltage SP432 High Speed, Low Power Quad Differential Line Receiver 8 © Copyright 1997 Sipex Corporation TYPICAL PERFORMANCE CHARACTERISTICS (continued) TBD TBD Figure 11. Output High Voltage Vs. Output High Current (Operational Temperature Range) Figure 12. Output High Voltage Vs. Output High Current (Operational Voltage Range) TBD TBD Figure 13. Output Low Voltage Vs. Output Low Current (Operational Temperature Range) Figure 14. Output Low Voltage Vs. Output Low Current (Operational Voltage Range) SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 9 © Copyright 1997 Sipex Corporation TYPICAL PERFORMANCE CHARACTERISTICS (continued) TBD TBD Figure 16. Input Current Vs. Power Supply Voltage Figure 15. Input Resistance Vs. Input Voltage TBD TBD Figure 18. Hysteresis and Differential Transition Voltage Vs. Power Supply Voltage Figure 17. Hysteresis and Differential Transition Voltage Vs. Temperature SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 10 © Copyright 1997 Sipex Corporation TYPICAL PERFORMANCE CHARACTERISTICS (continued) TBD TBD Figure 20. Disabled Supply Current Vs. Power Supply Voltage Figure 19. Supply Current Vs. Temperature TBD Figure 21. Supply Current Vs. Data Rate SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 11 © Copyright 1997 Sipex Corporation PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) E1 E D1 = 0.005" min. (0.127 min.) A1 = 0.015" min. (0.381min.) D A = 0.210" max. (5.334 max). C A2 e = 0.100 BSC (2.540 BSC) B1 B Ø L eA = 0.300 BSC (7.620 BSC) ALTERNATE END PINS (BOTH ENDS) DIMENSIONS (Inches) Minimum/Maximum (mm) SP432DS/10 16–PIN A2 0.115/0.195 (2.921/4.953) B 0.014/0.022 (0.356/0.559) B1 0.045/0.070 (1.143/1.778) C 0.008/0.014 (0.203/0.356) D 0.780/0.800 (19.812/20.320) E 0.300/0.325 (7.620/8.255) E1 0.240/0.280 (6.096/7.112) L 0.115/0.150 (2.921/3.810) Ø 0°/ 15° (0°/15°) SP432 High Speed, Low Power Quad Differential Line Receiver 12 © Copyright 1997 Sipex Corporation PACKAGE: PLASTIC SMALL OUTLINE (SOIC) (NARROW) E H h x 45° D A Ø e B A1 L DIMENSIONS (Inches) Minimum/Maximum (mm) SP432DS/10 16–PIN A 0.053/0.069 (1.346/1.748) A1 0.004/0.010 (0.102/0.249) B 0.013/0.020 (0.330/0.508) D 0.386/0.394 (9.802/10.000) E 0.150/0.157 (3.802/3.988) e 0.050 BSC (1.270 BSC) H 0.228/0.244 (5.801/6.198) h 0.010/0.020 (0.254/0.498) L 0.016/0.050 (0.406/1.270) Ø 0°/8° (0°/8°) SP432 High Speed, Low Power Quad Differential Line Receiver 13 © Copyright 1997 Sipex Corporation ORDERING INFORMATION Model .................................................................................... Temperature Range ..................................................................................... Package SP432CP ..................................................................................... 0°C to +70°C ....................................................................................... 16–pin DIP SP432CN ..................................................................................... 0°C to +70°C .................................................................................... 16–pin SOIC Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation European Sales Offices: Far East: Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] ENGLAND: Sipex Corporation 2 Linden House Turk Street Alton Hampshire GU34 IAN England TEL: 44-1420-549527 FAX: 44-1420-542700 e-mail: [email protected] JAPAN: Nippon Sipex Corporation Yahagi No. 2 Building 3-5-3 Uchikanda, Chiyoda-ku Tokyo 101 TEL: 81.3.3256.0577 FAX: 81.3.3256.0621 Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 GERMANY: Sipex GmbH Gautinger Strasse 10 82319 Starnberg TEL: 49.81.51.89810 FAX: 49.81.51.29598 e-mail: [email protected] Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. SP432DS/10 SP432 High Speed, Low Power Quad Differential Line Receiver 14 © Copyright 1997 Sipex Corporation