SP26LV432 High-Speed, Low-Power Quad RS-422 Differential Line Receiver ■ Quad Differential Line Receivers RI1B 1 ■ Compatible with the EIA standard for 16 VCC RS-422 serial protocol RI1A 2 15 RI4B SP26LV432 ■ High-Z Output Control R01 3 14 RI4A ■ 14ns Typical Receiver Propagation Delays ENABLE 4 13 R04 ■ 60mV Typical Input Hysteresis 12 ENABLE R02 5 ■ Single +3.3V Supply Operation 11 R0 RI2A 6 3 ■ Common Receiver Enable Control 10 RI A RI2B 7 ■ 26LV32 industry standard footprint compatible 3 9 RI B GND 8 ■ -7.0V to +7.0V Common-Mode Input 3 Voltage Range ■ Switching Rates Up to 50Mbps Now Available in Lead-Free Packaging ■ Ideal for use with SP26LV431 Quad Drivers DESCRIPTION The SP26LV432 is a quad differential line receiver with three-state outputs designed to meet the specifications of RS-422. The SP26LV432 features Sipex's BiCMOS process allowing low power operational characteristics of CMOS technology while meeting all of the demands of the RS-422 serial protocol at 50Mbps under load. The RS-422 protocol allows up to ten receivers to be connected to a multipoint bus transmission line. The SP26LV432 features a receiver enable control common to all four receivers and a high-Z output with 6mA source and sink capability. Since the cabling can be as long as 4,000 feet, the RS-422 receivers of the SP26LV432 are equipped with a wide (-7.0V to +7.0V) common-mode input voltage range to accommodate ground potential differences. TYPICAL APPLICATION CIRCUIT ENABLE ENABLE Input Output LOW HIGH don't care High-Z HIGH Don't Care VID > VTH (max) HIGH HIGH Don't Care VID < VTH (min) LOW Don't Care LOW VID > VTH (max) HIGH Don't Care LOW VID < VTH (min) LOW HIGH Don't Care Open HIGH Don't Care LOW Open HIGH RI A RI B 4 4 RI A RI B 3 3 RI A RI B 2 2 RI A RI B 1 1 R04 R03 R02 R01 ENABLE ENABLE GND Date: 04/27/06 INPUTS VCC SP26LV432 High Speed, Low Power Quad Differential Line Receiver 1 OUTPUTS © Copyright 2006 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC (Supply Voltage) ................................................................... +7.0V VCM (Common Mode Range) ........................................................ ±14V VDIFF (Differential Input Voltage) .................................................. ±14V VIN (Enable Input Voltage) ................................................... VCC + 1.5V TSTG (Storage Temperature Range) ........................... -65°C to +150°C Maximum Current Per Output .................................................... ±25mA Storage Temperature .................................................. -65°C to +150°C Power Dissipation Per Package 16-pin PDIP (derate 14.3mW/ºC above +70ºC) ...................... 1150mW 16-pin NSOIC (derate 8.95mW/ºC above +70ºC) ..................... 725mW ELECTRICAL CHARACTERISTICS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +3.6V with TAMB = 25°C and all MIN and MAX limits apply across the recommended operating temperature range. DC PARAMETERS MIN. TYP. MAX. UNITS 3.0 Supply Voltage, VCC Enable Input Rise or Fall Times 3.6 3 CONDITIONS V ns Input Electrical Characteristics Minimum Differential Input Voltage, VTH -200 Input Resistance, RIN 5.0 50 +200 mV VOUT = VOH or VOL, -7V < VCM < +7V KΩ VIN = -7V, +7V, +10V other input = GND Input Current IIN +1.25 +1.5 mA VIN = +10V, other input = GND IIN -1.5 -2.5 mA VIN = -10V, other input = GND Minimum Enable HIGH Input Level Voltage, VIH(EN) 2.0 V Maximum Enable LOW Input Level Voltage, VIL(EN) 0.8 V ±1.0 µA VIN = VCC or GND Input Hysteresis, VHYST 60 mV VCM = 0V Quiescent Supply Current, ICC 5 mA VCC = +3.3V, VDIF = +1V V VCC = +3.0V, VDIFF = +1V, IOUT = -6mA Maximum Enable Input Current, IEN 15 Output Electrical Characteristics Minimum High Level Output Voltage, VOH 2.4 2.8 Maximum Low Level Output Voltage, VOL 0.2 0.5 V VCC = +3.0V, VDIFF = -1V, IOUT = +6mA Maximum Tri-state Output Leakage Current, IOZQ ±0.5 ±5. 0 µA VOUT = VCC or GND, ENABLE = VIL, ENABLE = VIH Date: 04/27/06 SP26LV432 High Speed, Low Power Quad Differential Line Receiver 2 © Copyright 2006 Sipex Corporation SPECIFICATIONS (continued) Unless otherwise noted, the following specifications apply for VCC = +3.0V to +3.6V, Tamb = 25°C, tr < 6ns, tf < 6ns, and all MIN and MAX limits apply across the recommended operating temperature range. MIN. TYP. MAX. UNITS CONDITIONS AC PARAMETERS Propagation Delays Input to Output, tPLH, tPHL Refer to figure 2. 14 35 ns CL = 50pF, VDIFF = 2.5V, VCM = 0V, VCC = +5V 5 10 ns CL = 50pF, VDIFF = 2.5V, VCM = 0V, VCC = +5V 40 ns CL = 50pF, RL = 1000Ω, VDIFF = 2.5V, VCC = +5V Output Rise and Fall Times, tRISE, tFALL Propagation Delay ENABLE to Output, tPLZ, tPHZ Propagation Delay ENABLE to Output, Refer to Figure 4. tPZL, tPZH 40 ns CL = 50pF, RL = 1000Ω, VDIFF = 2.5V, VCC = +5V INPUTS VCC RI A RI B 4 4 RI A RI B 3 3 RI A RI B 2 2 RI A RI B 1 1 R04 R03 R02 R01 ENABLE ENABLE OUTPUTS GND Figure 1. SP26LV432 Block Diagram Date: 04/27/06 SP26LV432 High Speed, Low Power Quad Differential Line Receiver 3 © Copyright 2006 Sipex Corporation RI1B 1 RI1A 2 R01 3 ENABLE 16 VCC 15 RI4B 14 RI4A 4 13 R04 R02 5 12 ENABLE RI2A 6 11 R03 RI2B 7 10 RI3A GND 8 9 RI3B SP26LV432 PINOUT PIN DESCRIPTION PIN NUMBER PIN NAME DESCRIPTION 1 RI1B Inverted RS-422 receiver input. 2 RI1A Non-inverted RS-422 receiver input. 3 R01 TTL receiver output. 4 ENABLE 5 R02 TTL receiver output. 6 RI2A Non-inverted RS-422 receiver input. 7 RI2B Inverted RS-422 receiver input. 8 GND Ground. 9 RI3B Inverted RS-422 receiver input. 10 RI3A Non-inverted RS-422 receiver input. 11 R03 TTL receiver output. 12 ENABLE 13 R04 TTL receiver output. 14 RI4A Non-inverted RS-422 receiver input. 15 RI4B Inverted RS-422 receiver input. 16 VCC +3.0V to +3.6V power supply. Date: 04/27/06 Receiver input enable, active HIGH. Receiver input enable, active LOW. SP26LV432 High Speed, Low Power Quad Differential Line Receiver 4 © Copyright 2006 Sipex Corporation AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS VCC S1 +2.5V INPUTS (V-) – (V+) V+ INPUT 0V tPHL tPLH ttPHL PLH V- INPUT VOH 90% OUTPUT 90% ENABLE ENABLE 50% VOL 10% 10% tRISE RL DEVICE UNDER TEST -2.5V CL tFALL CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. Figure 3. Test Circuit for high-Z Output Timing Figure 2. Propagation Delay 3.0V 16 1.3V 1.3V ENABLE GND 15 tPLZ tPZL Differential Prop. Delay (ns) ENABLE VCC OUTPUT 50% VOL 0.5V VOH 0.5V OUTPUT 50% 0V tPHZ tPZH tPHLD 14 tPLHD 13 12 11 10 -40 -15 10 35 60 85 Temperature (°C) Figure 4. High Impedance Output Enable and Disable Waveforms Figure 5. Differential Propagation Delay vs Temperature 17 2 1.8 tPHLD 15 Differential Skew (ns) Differential Prop. Delay (ns) 16 14 13 tPLHD 1.6 1.4 1.2 1 12 0.8 11 3.0 3.1 3.2 3.3 3.4 3.5 0.6 3.6 -40 Power Supply Voltage (V) 10 35 60 85 Temperature (°C) Figure 6. Differential Propagation Delay vs Supply Voltage Date: 04/27/06 -15 Figure 7. Differential Skew vs Temperature SP26LV432 High Speed, Low Power Quad Differential Line Receiver 5 © Copyright 2006 Sipex Corporation 2.0 3.3 1.8 3.1 VCC = 3.3V Output High Voltage (V) Differential Skew (ns) 1.6 1.4 1.2 1.0 2.9 T = -40°C 2.7 2.5 T = +25°C 2.3 0.8 T = +85°C 2.1 0.6 3.0 3.1 3.2 3.3 3.4 3.5 0 3.6 5 10 15 20 Output High Current (mA) Power Supply Voltage (V) Figure 8. Differntial Skew vs Supply Voltage Figure 9. High Output Voltage vs Current over Temperature 1.6 3.6 1.4 3.2 VCC = 3.3V Output Low Voltage (V) Output High Voltage (V) 2.8 VCC = 3.3V 2.4 T= +85°C 1.2 VCC = 3.6V VCC = 3.0V 2.0 T=+25°C 1.0 0.8 0.6 T= -40°C 0.4 1.6 0.2 0.0 1.2 0 5 10 15 20 0 25 5 10 15 20 Output Low Current (mA) Output High Current (mA) Figure 10. High Output Voltage vs Current over Supply Voltage Figure 11. Low Output Voltage vs Current over Temperature 1.4 VCC = 3.0V 45 1.0 Input Resistance (KΩ) Output Low Voltage (V) 1.2 VCC = 3.3V 0.8 VCC = 3.6V 0.6 35 25 0.4 15 0.2 5 -10.0 -8.0 0.0 0 5 10 15 20 Figure 12. Low Output Voltage vs Current over Supply Voltage Date: 04/27/06 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0 Input Voltage (V) Output Low Current (mA) Figure 13. Input Resistance vs Input Voltage SP26LV432 High Speed, Low Power Quad Differential Line Receiver 6 © Copyright 2006 Sipex Corporation 0.9 80 +10V @ Inverting Input VHYST 0.6 +10V @ Non-Inverting Input 60 VTH 0.0 Transition Voltage (mV) Input Current (mA) 0.3 0V @ Inverting Input -0.3 0V @ Non-Inverting Input 40 20 VCC = 3.3V 0 -0.6 VTL -20 -10V @ Inverting Input -0.9 -40 -40 -10V @ Non-Inverting Input -1.2 3.0 3.1 3.2 3.3 3.4 3.5 -15 3.6 10 35 60 85 Temperature (°C) Power Supply Voltage (V) Figure 14. Input Current vs Supply Voltage Figure 15. Transition Voltage vs Temperature 7.0 80 VCC = 3.3V 60 6.5 40 6.0 Supply Current (mA) Transition Voltage (mV) VHYST 20 0 5.5 5.0 VTL -20 4.5 -40 3.0 3.1 3.2 3.3 3.4 3.5 3.6 4.0 -40 Power Supply Voltage (V) -15 10 35 60 85 Temperature (°C) Figure 16. Transition Voltage vs Supply Voltage Figure 17. Supply Current vs Temperature 7.0 5.4 VCC = 3.0V 6.5 6.0 50pF Load Supply Current (mA) Disabled Supply Current (mA) 5.1 5.5 5.0 4.5 4.8 1 TTL Load 4.5 4.2 No Load 4.0 3.9 3.5 3.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.6 1 Power Supply Voltage (V) 100 1000 10000 100000 Data Rate (kBaud) Figure 18. Disabled Supply Current vs Supply Voltage Date: 04/27/06 10 Figure 19. Supply Current vs Data Rate SP26LV432 High Speed, Low Power Quad Differential Line Receiver 7 © Copyright 2006 Sipex Corporation THEORY OF OPERATION The SP26LV432 accepts RS-422 levels and translates these into TTL or CMOS input levels. The SP26LV432 features active HIGH and active LOW receiver enable controls common to all four receiver channels. A logic HIGH on the ENABLE pin (pin 4) or a logic LOW on the ENABLE pin (pin 12) will enable the differential receiver outputs. A logic LOW on the ENABLE pin (pin 4) and a logic HIGH on the ENABLE pin (pin 12) will force the receiver outputs into high impedance (high-Z). Refer to the truth table in Figure 20. The SP26LV432 is a low-power quad differential line receiver designed for digital data transmission meeting specifications of the EIA standard RS-422 protocol. The SP26LV432 features Sipex's BiCMOS process allowing low power operational characteristics of CMOS technology while meeting all of the demands of the RS-422 serial protocol to at least 50Mbps under load in harsh environments. The RS-422 standard is ideal for multi-drop applications and for long-distance communication. The RS-422 protocol allows up to ten receivers to be connected to a data bus, making it an ideal choice for multi-drop applications. Since the cabling can be as long as 4,000 feet, the RS-422 receivers have an input sensitivity of 200mV over the wide (-7.0V to +7.0V) common mode range to accommodate ground potential differences. Internal pull-up and pull-down resistors prevent output oscillation on unused channels. Because the RS-422 is a differential interface, data is virtually immune to noise in the transmission line. ENABLE ENABLE Input Output LOW HIGH don't care High-Z HIGH Don't Care VID > VTH (max) HIGH HIGH Don't Care VID < VTH (min) LOW Don't Care LOW VID > VTH (max) HIGH Don't Care LOW VID < VTH (min) LOW The RS-422 line receivers feature high source and sink current capability. All receivers are internally protected against short circuits on their inputs. The receivers feature tri-state outputs with 6mA source and sink capability. The typical receiver propagation delay is 14ns (35ns max). To minimize reflections, the multipoint bus transmission line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possible. Driver Side such as SP26LV431 Receiver Side such as SP26LV432 ENABLE DATA *RT DATA OUTPUT *RT is optional although highly recommended to reduce reflection. HIGH Don't Care Open HIGH Don't Care LOW Open HIGH Figure 20. Truth Table, Enable/Disable Function Common to all Four RS-422 Receivers Date: 04/27/06 Figure 21. Two-Wire Balanced Systems, RS-422 SP26LV432 High Speed, Low Power Quad Differential Line Receiver 8 © Copyright 2006 Sipex Corporation PACKAGE: 16 PIN PDIP A1 D A N A2 D1 b3 e b2 b INDEX AREA L E1 E 1 2 3 N/2 E c eA eB 16 PIN PDIP JEDEC MS-001 (BB) Variation SYMBOL MIN NOM MAX A 0.21 A1 0.15 A2 0.115 0.13 0.195 b 0.014 0.018 0.022 b2 0.045 0.06 0.07 b3 0.3 0.039 0.045 c 0.008 0.01 0.014 D 0.735 0.75 0.755 D1 0.005 E 0.3 0.31 0.325 E1 0.24 0.25 0.28 .100 BSC e .300 BSC eA eB 0.43 L 0.115 0.13 0.15 Note: Dimensions in (mm) Date: 04/27/06 b C SP26LV432 High Speed, Low Power Quad Differential Line Receiver 9 © Copyright 2006 Sipex Corporation PACKAGE: 16 PIN NSOIC D e Ø E/2 E1 E E1/2 L2 Seating Plane 1 INDEX AREA (D/2 X E1/2) Ø L Ø1 L1 b Gauge Plane VIEW C TOP VIEW A1 A Seating Plane A2 16 Pin NSOIC JEDEC MO-012 (AC) Variation MIN NOM MAX SYMBOL A 1.35 1.75 A1 0.1 0.25 A2 1.25 1.65 b 0.31 0.51 c 0.17 0.25 9.90 BSC D 6.00 BSC E 3.90 BSC E1 1.27 BSC e L 0.4 1.27 1.04 REF L1 0.25 BSC L2 ø 0º 8º ø1 5º 15º SIDE VIEW B B SEE VIEW C b Note: Dimensions in (mm) c BASE METAL SECTION B-B WITH PLATING Date: 04/27/06 SP26LV432 High Speed, Low Power Quad Differential Line Receiver 10 © Copyright 2006 Sipex Corporation ORDERING INFORMATION Model Temperature Range Package SP26LV432CP ............................................................................. 0°C to +70°C ..................................................................................... 16–pin PDIP SP26LV432CP-L ......................................................................... 0°C to +70°C ..................................................................................... 16–pin PDIP SP26LV432CN ............................................................................ 0°C to +70°C .................................................................................. 16–pin NSOIC SP26LV432CN-L ......................................................................... 0°C to +70°C .................................................................................. 16–pin NSOIC SP26LV432CN/TR ...................................................................... 0°C to +70°C .................................................................................. 16–pin NSOIC SP26LV432CN-L/TR ................................................................... 0°C to +70°C .................................................................................. 16–pin NSOIC Available in lead free packaging. To order add “-L” suffix to part number. Example: SP26LV432CN/TR = standard; SP26LV432CN-L/TR = lead free /TR = Tape and Reel Pack quantity is 2,500 for NSOIC. REVISION HISTORY DATE 3/08/04 3/08/04 4/17/06 REVISION A B C DESCRIPTION Production Release. Included tape and reel p/n. Fixed truth table typo pg1 SOLVED BY SIPEX Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: 04/27/06 SP26LV432 High Speed, Low Power Quad Differential Line Receiver 11 © Copyright 2006 Sipex Corporation