TI CLVC125AQPWRG4Q1

SN74LVC125A-Q1
www.ti.com .................................................................................................................................................. SCAS762B – FEBRUARY 2004 – REVISED APRIL 2008
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
FEATURES
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Operates From 1.65 V to 3.6 V
Specified From –40°C to 125°C
Inputs Accept Voltages to 5.5 V
Max tpd of 4.8 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
abc
DESCRIPTION/ORDERING INFORMATION
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SOIC – D
Reel of 2500
SN74LVC125AQDRQ1
LC125AQ
TSSOP – PW
Reel of 2000
SN74LVC125AQPWRQ1
LC125AQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated
SN74LVC125A-Q1
SCAS762B – FEBRUARY 2004 – REVISED APRIL 2008 .................................................................................................................................................. www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1A
2OE
2A
1
3OE
2
3
1Y
3A
4
4OE
5
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range
–0.5
6.5
V
–0.5
VCC + 0.5
(2) (3)
UNIT
VO
Output voltage range
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
Ptot
Power dissipation (5) (6)
(1)
(2)
(3)
(4)
(5)
(6)
2
D package
86
PW package
113
–65
TA = –40°C to 125°C
V
°C/W
150
°C
500
mW
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
For the PW package: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
Submit Documentation Feedback
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC125A-Q1
SN74LVC125A-Q1
www.ti.com .................................................................................................................................................. SCAS762B – FEBRUARY 2004 – REVISED APRIL 2008
Recommended Operating Conditions (1)
TA = 25°C
Operating
VCC
Supply voltage
VIH
High-level input voltage
Data retention only
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.5
1.5
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
0.35 × VCC
0.35 × VCC
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
Low-level output current
V
5.5
0
5.5
V
0
VCC
0
VCC
V
VCC = 1.65 V
–4
–4
VCC = 2.3 V
–8
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
4
4
mA
VCC = 2.3 V
8
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
mA
8
8
ns/V
Δt/Δv Input transition rise or fall rate
(1)
V
0
VCC = 1.65 V
IOL
UNIT
V
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
VIL
–40°C to 125°C
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETE
R
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 3.6 V
MIN
–40°C to 125°C
TYP MAX
VCC – 0.2
MIN
MAX
UNIT
VCC – 0.2
IOH = –4 mA
1.65 V
1.29
1.1
IOH = –8 mA
2.3 V
1.9
1.75
2.7 V
2.2
2.1
2.35
IOH = –12 mA
VOL
TA = 25°C
VCC
V
3V
2.4
IOH = –24 mA
3V
2.3
IOL = 100 µA
1.65 V to 3.6 V
0.1
0.2
IOL = 4 mA
1.65 V
0.24
0.45
IOL = 8 mA
2.3 V
0.3
0.7
IOL = 12 mA
2.7 V
0.4
0.5
IOL = 24 mA
3V
0.55
0.7
2.1
V
II
VI = 5.5 V or GND
3.6 V
±1
±10
µA
IOZ
VO = VCC or GND
3.6 V
±1
±10
µA
ICC
VI = VCC or GND,
3.6 V
1
20
µA
500
500
µA
ΔICC
Ci
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V to 3.6 V
VI = VCC or GND
3.3 V
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC125A-Q1
5
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pF
3
SN74LVC125A-Q1
SCAS762B – FEBRUARY 2004 – REVISED APRIL 2008 .................................................................................................................................................. www.ti.com
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tsk(o)
VCC
TA = 25°C
–40°C to 125°C
MIN
TYP
MAX
MIN
MAX
2.7 V
1
3
5.3
1
7
3.3 V ± 0.3 V
1
2.5
4.6
1
6
2.7 V
1
3.3
6.4
1
8.5
3.3 V ± 0.3 V
1
2.4
5.2
1
7
2.7 V
1
2.5
4.8
1
6.5
3.3 V ± 0.3 V
1
2.4
4.4
1
6
3.3 V ± 0.3 V
UNIT
ns
ns
ns
1.5
ns
UNIT
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance per gate
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TEST
CONDITIONS
VCC
TYP
f = 10 MHz
3.3 V
15
pF
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC125A-Q1
SN74LVC125A-Q1
www.ti.com .................................................................................................................................................. SCAS762B – FEBRUARY 2004 – REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
2.7 V
3.3 V ± 0.3 V
VM
tr/tf
VI
≤ 2.5 ns
≤ 2.5 ns
2.7 V
2.7 V
1.5 V
1.5 V
VLOAD
6V
6V
CL
RL
V∆
50 pF
50 pF
500 Ω
500 Ω
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC125A-Q1
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5
PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
CLVC125AQPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74LVC125AQDRG4Q1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74LVC125AQDRQ1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74LVC125AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC125A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2011
• Catalog: SN74LVC125A
• Enhanced Product: SN74LVC125A-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
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