TI CDCP1803

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004
Distributes One Differential Clock Input to
S2
Vdd0
/Y0
Y0
Vdd0
S1
24
23
22
21
20
19
18
S0
VddPECL
2
17
Vdd1
IN
3
16
Y1
IN
4
15
Y1
VddPECL
5
14
Vdd1
VBB
6
13
VSS
10
11
/Y2
Vdd2
NC 12
9
Y2
VSS
8
1
Vdd2
EN
7
Vss
Three LVPECL Differential Clock Outputs
Programmable Output Divider for Two
LVPECL Outputs
Low-Output Skew 15 ps (Typical)
VCC Range 3 V−3.6 V
Signaling Rate Up to 800-MHz LVPECL
Differential Input Stage for Wide
Common-Mode Range
Provides VBB Bias Voltage Output for
Single-Ended Input Signals
Receiver Input Threshold +75 mV
24-Pin MLF Package (4 mm x 4 mm)
Accepts Any Differential Signaling: LVDS,
HSTL, CML, VML, SSTL-2, and
Single-Ended: LVTTL/LVCMOS
MLF PACKAGE
(TOP VIEW)
PowerPad must be connected to V .
SS
description
The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential
clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCP1803 is specifically
designed for driving 50-Ω transmission lines.
The CDCP1803 has three control pins, S0, S1, and S2, to select different output mode settings, see Table 1
for details. The CDCP1803 is characterized for operation from −40°C to 85°C. For use in single-ended driver
applications, the CDCP1803 also provides a VBB output pin that can be directly connected to the unused input
as a common-mode voltage reference.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
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functional block diagram
Y0
IN
LVPECL
Y0
IN
Y1
LVPECL
Y1
Div 1
Div 2
Div 4
Div 8
Div 16
Y2
LVPECL
Y2
VBB
Bias
Generator
VDD - 1.3 V
(imax < 1.5 mA)
Control
2
S1
S2
S0
EN
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Terminal Functions
NAME
EN
IN, IN
NO.
I/O
1
I
(with 60-kΩ pullup)
3, 4
I (differential)
DESCRIPTION
ENABLE: Enables or disables all outputs simultaneously.
EN=1: outputs on according to S0, S1, and S2 setting
EN=0: outputs Y[2:0] off (high impedance)
See Table 1 for details.
Differential input clock: Input stage is sensitive and has a wide common-mode range.
Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS, CML,
HSTL). Since the input is high impedance, it is recommended to terminate the PCB
transmission line before the input (e.g. with 100-Ω across input). Input can also be driven by
single ended signal if the complementary input is tight to VBB. A more advanced scheme for
single-ended signal is given in the application section near the end of this document.
The inputs deploy an ESD structure protecting the inputs in case of an input voltage exceeding
the rails by more than ~0.7 V. Reverse biasing of the IC through these inputs is possible and
must be prevented by limiting the input voltage < VDD.
NC
12
No connect. Leave this pin open or tie to ground
S0, S1, S2
18, 19,
24
I
(with 60-kΩ pullup)
Select mode of operation: Defines the output configuration of Y[2:0]. See Table 1 for
configuration.
Y[2:0],
Y[2:0]
9, 10,
15, 16,
21, 22
O (LVPECL)
LVPECL clock outputs: These outputs provide low-skew copies of IN pair or down divided
copies of clock IN based on selected mode of operation S[2:0]; If an output is unused, the
output can simply be left open to save power and minimize noise impact to the remaining
outputs.
6
O
Bias voltage output can be used to bias unused complementary input IN for single ended input
signals.
The output voltage of VBB is VDD − 1.3 V. When driving a load, the output current drive is limited
to about 1.5 mA.
VSS
VDDPECL
7, 13
Supply
Device ground
2, 5
Supply
Supply voltage PECL input + internal logic
VDD [0−2]
8, 11, 14,
17,20,
23
Supply
PECL output supply voltage for output Y[0−2]: Each output can be disabled by pulling the
corresponding VDDx to GND.
VBB
CAUTION: In this mode, no voltage from outside may be forced, because internal diodes could
be forced in forward direction; Thus, it is recommended to disconnect the output if it is not being
used.
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control pin settings
The CDCP1803 has three control pins (S0, S1, and S2) and an enable pin (EN) to select different output mode
settings.
Setting for Mode 20:
EN = 1
S2 = 1
S1 = 0
S0 = 1
CDCP1803
REN = Open
EN
RS2 = Open
S2
RS1 = 0 Ω
S1
RS0 = Open
S0
Figure 1. Control Pin Setting for Example
Table 1. Selection Mode Table
LVPECL
4
MODE
EN
S2
0
0
x
x
x
1
1
0
0
0
÷1
÷1
÷1
2
1
0
0
÷1
Off (high-z)
Off (high-z)
3
1
0
0
VDD/2
1
÷1
÷1
Off (high-z)
4
1
0
0
÷1
÷2
Off (high-z)
5
1
0
VDD/2
VDD/2
÷4
Off (high-z)
1
0
÷1
÷8
Off (high-z)
7
1
0
VDD/2
1
VDD/2
1
÷1
6
0
÷1
Off (high-z)
÷1
8
1
0
1
1
÷1
÷2
÷1
9
1
0
0
÷1
÷4
÷1
10
1
VDD/2
VDD/2
0
÷8
÷1
1
0
÷1
Off (high-z)
÷2
12
1
VDD/2
VDD/2
VDD/2
1
÷1
11
0
÷1
÷1
÷2
13
1
÷2
÷2
1
VDD/2
1
÷1
14
÷1
÷4
÷2
15
1
16
1
17
1
18
19
VDD/2
VDD/2
VDD/2
VDD/2
S1
VDD/2
VDD/2
VDD/2
1
1
S0
Y0
Y1
Y2
Off (high-z)
0
÷1
÷8
÷2
VDD/2
1
÷1
Off (high-z)
÷4
÷1
÷1
÷4
1
1
VDD/2
1
0
0
÷1
÷2
÷4
1
1
0
÷1
÷4
÷4
20
1
1
0
VDD/2
1
÷1
÷8
÷4
21
1
1
÷1
Off (high-z)
÷8
1
1
VDD/2
VDD/2
0
22
VDD/2
÷1
÷1
÷8
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1
÷1
÷2
÷8
1
VDD/2
1
0
÷1
÷4
÷8
1
1
÷1
÷8
÷8
1
1
1
VDD/2
1
÷1
Off (high-z)
÷ 16
VDD/2
VDD/2
0
0
0
÷1
÷1
÷ 16
0
0
VDD/2
1
÷1
÷2
÷ 16
÷1
÷4
÷ 16
0
÷1
÷8
÷ 16
1
VDD/2
VDD/2
1
Reserved
Reserved
Reserved
1
1
0
N/A
Low
Low
23
1
1
24
1
25
1
26
27
VDD/2
VDD/2
0
0
0
VDD/2
VDD/2
28
29
30
Rsv
Rsv
NOTE: The LVPECL outputs are open emitter stages. Thus, if you leave the unused LVPECL outputs Y0, Y1, or Y2
unconnected, then the current consumption is minimized and noise impact to remaining outputs is neglectable.
Also, each output can be individually disabled by connecting the corresponding VDD input to GND.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3.8 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to (VDD +0.2 V)
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to (VDD +0.2 V)
Differential short circuit current, Yn, Yn, IOSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Electrostatic discharge (HBM 1.5 kΩ, 100 pF), ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2000 V
Moisture level 24-pin MLF package (solder reflow temperature of 235°C) MSL . . . . . . . . . . . . . . . . . . . . . . . . 2
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
Supply voltage, VDD
Operating free-air temperature, TA
MIN
TYP
MAX
3
3.3
3.6
V
85
°C
−40
UNIT
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
LVPECL input IN, IN
PARAMETER
fclk
VCM
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
Input frequency
0
800
High-level input common mode
1
VDD−0.3
VIN
Input voltage swing between IN and IN,
see Note 1
500
1300
mV
VIN
Input voltage swing between IN and IN,
see Note 2
150
1300
mV
IIN
RIN
Input current
±10
VI = VDD or 0 V
Input impedance
300
CI
Input capacitance at IN, IN
NOTES: 1. Is required to maintain ac specifications
2. Is required to maintain device functionality
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SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004
LVPECL output driver Y[2:0], Y[2:0]
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
0
800
MHz
VDD–0.81
VDD–1.55
fclk
VOH
Output frequency, see Figure 3
High-level output voltage
Termination with 50 Ω to VDD−2 V
VOL
Low-level output voltage
Termination with 50 Ω to VDD−2 V
VDD−1.18
VDD−1.98
VO
Output voltage swing between Y and Y,
see Figure 3
Termination with 50 Ω to VDD−2 V
500
IOZL
IOZH
Output 3-state
Output 3-state
VDD = 3.6 V, VO = 0 V
VDD = 3.6 V, VO = VDD – 0.8 V
tr/tf
Rise and fall time
20% to 80% of VOUTPP, see Figure 7
tskpecl(o)
Output skew between any LVPECL
output Y[2−0] and Y[2−0]
See Note A in Figure 6
tDuty
Output duty cycle distortion,
see Note 3
Crossing point-to-crossing point
distortion
tsk(pp)
CO
Part-to-part skew
Any Y, See Note B in Figure 6
Output capacitance
VO = VDD or GND
LOAD
Expected output load
TYP
V
V
mV
200
15
−50
5
µA
10
µA
350
ps
30
ps
50
ps
50
ps
1
pF
50
Ω
NOTES: 3. For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal.
LVPECL input-to-LVPECL output parameter
PARAMETER
6
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpd(lh)
tpd(hl)
Propagation delay rising edge
VOX to VOX
320
600
ps
Propagation delay falling edge
VOX to VOX
320
600
ps
tsk(p)
LVPECL pulse skew
VOX to VOX, See Note C in Figure 6
100
ps
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
jitter characteristics
PARAMETER
TEST CONDITIONS
Additive phase jitter from input to LVPECL output [Y2−0],
see Figure 2
MIN
TYP
UNIT
0.15
ps rms
50 kHz to 40 MHz,
fout = 250 MHz to 800 MHz,
divide by 1 mode
0.25
ps rms
ADDITIVE PHASE NOISE
vs
FREQUENCY OFFSET FROM CARRIER − LVPECL
−110
−115
Additive Phase Noise − dBc/Hz
tjitterLVPECL
MAX
12 kHz to 20 MHz,
fout = 250 MHz to 800 MHz,
divide by 1 mode
−120
VDD = 3.3 V
TA = 25°C
f = 622 MHz
÷1 Mode
−125
−130
−135
−140
−145
−150
−155
−160
10
100
1k
10k
100k
1M
10M
100M
f − Frequency Offset From Carrier − Hz
Figure 2.
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LVPECL OUTPUT SWING
vs
FREQUENCY
0.90
0.85
VDD = 3.6 V
LVPECL Output Swing − V
0.80
0.75
0.70
VDD = 3 V
0.65
0.60
0.55
VDD = 3.3 V
0.50
0.45
0.40
0.1
TA = 25°C
Load = 50 Ω to VDD − 2 V
0.3
0.5
0.7
0.9
1.1
1.3
1.5
f − Frequency − GHz
Figure 3.
supply current electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
PARAMETER
IDD
TEST CONDITIONS
Full load
All outputs enabled and terminated with 50 Ω to
VDD − 2 V on LVPECL outputs, f = 800 MHz for LVPECL
outputs
VDD = 3.3 V
No load
Outputs enabled, no output load, f = 800 MHz for LVPECL
outputs
VDD = 3.6 V
Supply current
IDD
Supply current saving per LVPECL
output stage disabled, no load
f = 800 MHz for LVPECL output, VDD = 3.3 V
IDDZ
Supply current, tri-state
All outputs 3-state by control logic, f = 0 Hz,
VDD = 3.6 V
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MIN
TYP
MAX
UNITS
140
mA
90
10
mA
0.5
mA
SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004
SUPPLY CURRENT
vs
FREQUENCY
150
I DD − Supply Current − mA
VDD = 3.3 V,
TA = 255C,
50 W to VDD −2 V for LVPECL
145
3 LVPECL Outputs(P1) Running
140
135
130
100
300
500
700
900
1100
1300
1500
f − Frequency − MHz
Figure 4.
package thermal resistance
PARAMETER
TEST CONDITIONS
θJA−1
MLF−24 package thermal resistance,
See Note 1
4-layer JEDEC test board (JESD51−7),
airflow = 0 ft/min
θJA−2
MLF−24 package thermal resistance
with thermal vias in PCB, See Note 1
4-layer JEDEC test board (JESD51−7) with four
thermal vias of 22-mil diameter each,
airflow = 0 ft/min
MIN
TYP
MAX
UNIT
106.6
°C/W
55.4
°C/W
NOTE 1: It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good
heat sink.
Example:
calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal
vias:
TChassis = 85°C (temperature of the chassis)
Peffective = Imax x Vmax = 90 mA x 3.6 V = 324 mW (max power consumption inside the package)
θTJunction = θJA−2 x Peffective = 55.45°C/W x 324 mW = 17.97°C
TJunction = θTJunction + TChassis = 17.97°C + 85°C = 103°C (the maximum junction temperature of Tdie−max =
125°C is not violated)
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control input characteristics over recommended operating free-air temperature range
PARAMETER
tsu
th
TEST CONDITIONS
MIN
Setup time, S0, S1, S2, and EN pin before clock IN
Hold time, S0, S1, S2, and EN pin after clock IN
TYP
MAX
UNITS
25
ns
0
ns
t(disable)
Time between latching the EN low transition and when all
outputs are disabled (how much time is required until the
outputs turn off)
10
ns
t(enable)
Time between latching the EN low-to-high transition and
when outputs are enabled based on control settings (how
much time passes before the outputs carry valid signals)
1
µs
Rpullup
Internal pullup resistor on S[2:0] and EN input
VIH(H)
VIL(L)
Three level input high, S0, S1, S2, and EN pin, see Note 1
IIH
IIL
Input current, S0, S1, S2, and EN pin
42
60
0.9xVDD
VI = VDD
VI = GND
kΩ
V
Three level low, S0, S1, S2, and EN pin
Input current, S0, S1, S2, and EN pin
78
38
0.1xVDD
−5
µA
V
85
µA
NOTES: 1. Leaving this pin floating automatically pulse the logic level high to VDD through an internal pullup resistor of 60 kΩ.
bias voltage VBB over recommended operating free-air temperature range
PARAMETER
VBB
TEST CONDITIONS
Output reference voltage
MIN
VDD = 3 V − 3.6 V, IBB = −0.2 mA
VDD − 1.4
OUTPUT REFERENCE VOLTAGE (VBB)
vs
LOAD
4.0
VBB − Output Reference Voltage − V
VDD = 3.3 V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−5
0
5
10
15
20
25
30
I − Load − mA
Figure 5.
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35
TYP
MAX
VDD − 1.2
UNITS
V
SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
IN
IN
Y0
Y0
tpd(LH1)
Y1
Y1
tpd(LH2)
Y2
Y2
NOTES: A. Output skew, tsk(o), is calculated as the greater of:
− The difference between the fastest and the slowest tpd(LH)n (n = 0…2)
− The difference between the fastest and the slowest tpd(HL)n (n = 0…2)
B. Part-to-part skew, tsk(pp), is calculated as the greater of:
− The difference between the fastest and the slowest tpd(LH)n (n = 0…2) for LVPECL across multiple devices
− The difference between the fastest and the slowest tpd(HL)n (n = 0…2) for LVPECL across multiple devices
C. Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and the low-to-high
(tpd(LH)) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = | tpd(HL) − tpd(LH) |. Pulse
skew is sometimes referred to as pulse width distortion or duty cycle skew.
Figure 6. Waveforms for Calculation of tsk(o) and tsk(pp)
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PARAMETER MEASUREMENT INFORMATION
Yn
VOH
Yn
VOL
80%
VOUT(pp)
0V
20%
|Yn*Yn|
tr
tf
Figure 7. LVPECL Differential Output Voltage and Rise/Fall Time
PCB design for thermal functionality
It is recommended to take special care of the PCB design for good thermal flow from the MLF-24 pin package
to the PCB.
Due to the three LVPECL outputs, the current consumption of the CDCP1803 is fixed.
JEDEC JESD51-7 specifies thermal conductivity for standard PCB boards.
Modeling the CDCP1803 with a standard 4-layer JEDEC board results into a 59.5°C max temperature with a
θJA of 106.62°C/W for 25°C ambient temperature.
When deploying four thermal vias (one per quadrant), the thermal flow improves significantly, yielding 42.9°C
max temperature with a θJA of 55.4°C/W for 25°C ambient temperature.
To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications enabling
all four outputs at ones.
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PARAMETER MEASUREMENT INFORMATION
Package Thermal Pad
(Underside)
Thermal Via
Dia 0.020 In.
Top Side
Island
Heat
Dissipation
VSS Copper Plane
VSS Copper Plane
Figure 8. Recommended Thermal Via Placement
See the SCBA017 and the SLUA271 application notes for further package related information.
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APPLICATION INFORMATION
LVPECL receiver input termination
The input of the CDCP1803 has a high impedance and comes with a large common-mode voltage range.
For optimized noise performance, it is recommended to properly terminate the PCB trace (transmission line).
If a differential signal drives the CDCP1803, then a 100-Ω termination resistor is recommended to be placed
as close as possible across the input pins. An even better approach is to install 2x 50 Ω, with the center tap
connected to a capacitor (C) to terminate odd-mode noise and make up for transmission line mismatches. The
VBB output can also be connected to the center tap to bias the input signal to (VDD − 1.3 V) (see Figure 9).
CDCP1803
CAC
IN
50 Ω
LVPECL
50 Ω
150 Ω
50 Ω
CAC
IN
50 Ω
VBB
150 Ω
C
Figure 9. Recommended AC-Coupling LVPECL Receiver Input Termination
CDCP1803
130 Ω
50 Ω
LVPECL
83 Ω
130 Ω
50 Ω
83 Ω
Figure 10. Recommended DC-Coupling LVPECL Receiver Input Termination
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APPLICATION INFORMATION
The CDCP1803 can also be driven by single-ended signals. Typically, the input signal becomes connected to
one input, while the complementary input must be properly biased to the center voltage of the incoming input
signal. For LVCMOS signals, this would be VCC/2, realized by a simple voltage divider (e.g. two 10-kΩ resistors).
The best options (especially if the dc offset of the input signal might vary) are to ac-couple the input signal and
then rebias the signal using the VBB reference output. See Figure 11.
CDCP1803
CAC
IN
CLK
Rdc
IN
VBB
CCT
NOTE: CAC − AC-coupling capacitor (e.g., 10 nF)
CCT − Capacitor keeps voltage at IN constant (e.g., 10 nF)
Rdc − Load and correct duty cycle (e.g., 50 Ω)
VBB − Bias voltage output
Figure 11. Typical Application Setting for Single-Ended Input Signals Driving the CDCP1803
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SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
device behavior during RESET and control pin switching
output behavior from enabling the device (EN=0 % 1)
In disable mode (EN=0), all output drivers are switched in high-Z mode. The S[0:2] control inputs are also
switched off. In the same mode, all flip-flops are reset. The typical current consumption is below 500 µA.
When the device is enabled again, it takes typically 1 µs for the settling of the reference voltage and currents.
During this time, the outputs Y[0:2] and Y[0:2] drive a high signal. After the settle time, the outputs go into the
low state. Due to the synchronization of each output driver signal with the input clock, the state of the waveforms
after enabling the device looks like shown in Figure 12. The inverting input and output signal is not included.
The Y:/1 waveform is the undivided output driver state.
1 µs
EN
IN
Y:/1
High-Z
Undefined
Y:/2
High-Z
Undefined
Y:/4
High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = Low)
1 µs
Undivided State is Valid After the First
Positive Transition of the Input Clock
EN
IN
Y:/1
High-Z
Undefined
Y:/2
High-Z
Undefined
Y:/4
High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = High)
Figure 12. Waveforms
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APPLICATION INFORMATION
enabling a single output stage
If a single output stage becomes enabled:
Y[0:2] will either be low or high (undefined).
Y[0:2] will be the inverted signal of Y[0:2].
With the first positive clock transition the undivided output becomes the input clock state. The divided output
states are equal to the actual internal divider. The internal divider doesn’t get reset while enabling single output
drivers.
ENABLE Yx:
Disabled
Enabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
IN
Yx:/1
High-Z
Undefined
Yx:/x
High-Z
Undefined
Divider State
Figure 13. Signal State After an Output Driver Becomes Enabled While IN = 0
ENABLE Yx:
Disabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
Enabled
IN
Yx:/1
High-Z
Undefined
Yx:/x
High-Z
Undefined
Divider State
Figure 14. Signal State After an Output Driver Becomes Enabled While IN = 1
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SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004
MECHANICAL DATA
RTH (S−PQFP−N24)
PLASTIC QUAD FLATPACK
2.25 MAX SQ.
1.95 MIN SQ.
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