W536030T/060T/090T/120T VOICE/MELODY/LCD CONTROLLER (ViewTalk TM Series) Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 2 2. FEATURES ................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................... 5 4. PAD DESCRIPTION ................................................................................................................... 6 5. ELECTRICAL CHARACTERISTICS........................................................................................... 9 6. 7. 5.1 Absolute Maximum Ratings............................................................................................... 9 5.2 DC Characteristics............................................................................................................. 9 5.3 AC Characteristics ........................................................................................................... 11 TYPICAL APPLICATION CIRCUITS ........................................................................................ 14 6.1 Sub Clock with RC Mode................................................................................................. 14 6.2 Sub Clock with Crystal Mode........................................................................................... 15 REVISION HISTORY ................................................................................................................ 16 -1- Publication Release Date: May 21, 2003 Revision A8 W536030T/060T/090T/120T 1. GENERAL DESCRIPTION The W536XXXT, a member of ViewTalkTM family, is a high-performance 4-bit micro-controller (uC) with built-in speech unit, melody unit and 64seg * 32 com LCD driver unit which includes internal regulator,pump circuit and dedicated two pages LCD RAM. The 4-bit uC core contains dual clock source, 4-bit ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and 8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM), is capable of expanding to 512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation. It is ideal for games, educational toys, remote controllers, watches, clocks and other application products which incorporate both LCD display and speech. BODY Voice I/O pad WDT disable/Enable (Mask Option) W536030T W536060T W536090T W536120T 30 sec 60 sec 90 sec 120 sec 4I/O, 4I 4I/O, 8I 8I/O, 8I, 8O 8I/O, 8I, 8O (RA/RD) (RA/RC/RD) (RA/RB/RC/RD/RE/RF) (RA/RB/RC/RD/RE/RF) Y Y Y Y Y Y Y Y Y(1) Y(1) N N (2) Y Y Y Y Y(1) Y(1) N Y Sub-clock RC/XTAL mode (Mask Option) RD port shared as serial bus (Mask Option) Tri-state serial bus (Mask Option) ( 3) Cascaded Voice ROM through serial bus (2) Notes: (1). Share 3 pads of RD port (RD1/CLK, RD2/DATA and RD3/ADDR) (2). Dedicate serial bus 3 pads (CLK, DATA and ADDR) to interface with W55XXX. Cascaded Voice ROM can help user to expand voice up to 512 sec by W55XXX chip. (3). Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this mask option is disabled to get minimum power consumption in general. -2- W536030T/060T/090T/120T 2. FEATURES • Operating voltage: 2.4 volt ~ 5.5 volt • Watch dog disabled/enabled by mask option • Dual clock operating system − Main clock with Ring/Crystal (400 KHz to 4 MHz) − Sub-clock with 32.768 KHz RC/Crystal by mask option • Memory − Program ROM (P-ROM): 64K × 20 (ROM Bank0, 1, 2, 3, 4, 5, 6) − Data RAM (W-RAM): 1.4K × 4 bit (RAM Bank 0 is 896 nibbles from 0: 000~0:37F and 0: 380~0:3FF are mapped to special register. RAM Bank F is 512 nibbles from F: 200~F: 3FF either data RAM or dedicated to script kernel) − LCD RAM (L-RAM): 512 × 4 bit × 2 pages (RAM Bank1, 2 from 200~3FF) • Maximum 24 input/output pads − Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory W55XXX interface @W536030T/060T) − Ports for output only: 8 pads (RE & RF port; W536090T/120T available only) − Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536090T /W536120T only) • Power-down mode − Hold mode (except for 32KHz oscillator) − Stop mode (including 32KHz oscillator and release by RD or RC port) • Eight types of interrupts − Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody) − Three external interrupts (Port RC, RD, RA) • One built-in 14-bit clock frequency divider circuit • Two built-in 8-bit programmable countdown timers − Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected − Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0 • Built-in 18/14-bit watchdog timer for system reset. • Powerful instruction sets • 8-level subroutine (including interrupt) nesting • LCD driver unit capability − VLCD higher than (VDD -0.5V) − Built-in voltage regulator to V2 pad − 64 seg × 32 com -3- Publication Release Date: May 21, 2003 Revision A8 W536030T/060T/090T/120T − 1/32 or 1/16 duty, 1/5 or 1/4 bias, internal pump circuit option by special register − COM24~ 31 and SEG40~63 can be shared as general input/output by special register − Either uC ROM or voice ROM used as LCD picture • Speech function − Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030T/060T/090T/120T based on 5 bits MDPCM algorithm − Voice ROM (V-ROM) available for uC data or LCD picture data. − Maximum 8*256 Label/Interrupt vector (voice section number) available − Provide two types of speech busy flag to either each GO or each trigger − Maximum up to 16M bits speech address capability interface with external memory W55XXX through serial bus. • Melody function − Provide 1K notes (22bits/note) dedicated melody ROM − Provide two types of melody busy flag to uC either each note or each song − Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7 − Tremolo, triple frequency and 3 kinds of percussion available − Maximum 31 songs available • Can mix speech with melody • Multi-engine controller • Direct driving speaker/buzzer or DAC output • Chip On Board available -4- W536030T/060T/090T/120T 3. BLOCK DIAGRAM COM0~31 SEG0~63 DH1,DH2 VDD LCD DRIVER LCD RAM 512*4*2 bit V2 V3,V4,V5,V6 VLCD PUMP & REGULATOR VSS Data RAM 1.4K*4 bit PORT RA ROM RA0~3 TONE ACC 64K*20Bit PORT RB RB0~3 PORT RC RC0~3 PORT RD RD0~3 PORT RE RE0~3 ALU PC Special Register STACK (8 Levels) IEF HEF PEF EVF HCF SPC MLD FLAG0 FLAG1 PM0 MR0 PSR0 LPX0 LPX1 LPX2 LPX3 LPX4 LPX5 LPY0 LPY1 PORT RF RF0~3 Parallel to Serial ADDR CLK DATA VDDA SPC_busy VSSA SPC_play LPXY Shared_ROM Data Speech MDPCM core ROSC VSSP Timer 0 Interrupt ,Hold & Stop Control Timer 1 PW M1/DAC MLD_busy Voice ROM (1M /2M/3M/4M bits) MLD_play W atch Dog Divide Timing Generator Dual Tone melody (1K notes) PW M/DAC Mix Block PW M2 VDDP TEST RES XIN XOUT X32I X32O -5- Publication Release Date: May 21, 2003 Revision A8 W536030T/060T/090T/120T 4. PAD DESCRIPTION SYMBOL I/O FUNCTION XIN/RXIN I Input pad for main clock oscillator. It can be connected to crystal when crystal mode is selected (SCR0.2 = 1), otherwise connect a resistor to VDD to generate main system clock while Ring mode is selected (SCR0.2 = 0 and default). Oscillator can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External capacitor connects to start oscillation and get more accurate clock when crystal mode XOUT O Output pad for oscillator which is connected to another crystal pad when in crystal mode. External capacitor connects to start oscillation when in crystal mode. X32I/RSUB1 I 32.768 KHz crystal input pad or external resistor node 1 by mask option. External 15~20pF capacitor connects to start oscillation and get more accurate clock when in crystal mode. X32O/RSUB2 O 32.768 KHz crystal output pad or external resistor node 2 by mask option. External 15~20pF capacitor connects to start oscillation when in crystal mode. I/O General Input/Output port specified by PM1 register. If output mode is selected, PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option. Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special register is set to logic 1. An interrupt source. I/O General Input/Output port specified by PM2 register. If output mode is selected, PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option. Initial state is input mode (W536090T /W536120T only.) I 4-bit schmitter input with internal pull high option specified by PM3 register bit 2. Each pad has an independent interrupt capability specified by PEFL special register. Interrupt and STOP mode wake up source. RC0 is also the external event counter source of Timer1. (W536060T/090T/120T only.) I 4-bit schmitter input port with internal pull high option specified by PM3 register bit 3. Each pad has an independent interrupt capability specified by PEFH special register. Interrupt and STOP mode wake up source. RD1~3 will be shared as the external memory W55XXX interface pads while RD port shared as serial bus mask option is enabled @W536030T/060T. O Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving capability option. (W536090T/120T only) O Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving capability option. (W536090T/120T only) I System reset pad, active low with internal pull-high resistor. RA0 ~ RA3/TONE (8) RB0 ~ RB3 (8) RC0 ~ RC3 RD0 RD1/CLK RD2/DATA RD3/ADDR (4) RE0~RE3 (8) RF0~RF3 (8) RES -6- W536030T/060T/090T/120T PAD Description, continued SYMBOL I/O FUNCTION TEST I Test pad. Active high with internal pull low resistor. ROSC I Connect resistor to VDD pad to generate speech or melody playing clock source. PWM1/DAC O While speech or melody is active, PWM1/DAC is speaker direct driving output or DAC output controlled by voice output file. PWM2 O While speech or melody is active, PWM2 is another speaker direct driving output. ADDR (5) O External serial memory address write clock for voice extension (W536120T only). The “Tri-sate serial bus” mask option can use trisate WRP pad while external voice ROM is not available. Default that mask option is disabled and fixes WRP pad state while external voice is not enabled to get chip low power consumption. CLK (5) O External serial memory address read clock for voice extension. (W536120T only). The pad state is same as WRP pad depended on “Tri-sate serial bus” mask option. DATA (5) I/O External serial memory data in/out for voice extension (W536120T only). The pad state is same as WRP pad depended on “Tri-sate serial bus” mask option. SEG0−SEG39 O Dedicated LCD segment output pads. SEG40/PORTN.0 SEG43/PORTN.3 O/O LCD segment output pads, and can be shared as general output by register LCDM3 bit 1. Default function is segment pad. SEG44/PORTM.0 SEG47/PORTM.3 O/I LCD segment output pads, and can be shared as general input by register LCDM3 bit 0. Default function is segment pad and PM5.1=0 to inhibit LCD waveform abnormal. SEG48/PORTL.0 SEG51/PORTL.3 O/O LCD segment output pads, and can be shared as general output by register LCDM2 bit 3. Default function is segment pad. SEG52/PORTK.0 SEG55/PORTK.3 O/I LCD segment output pads, and can be shared as general input by register LCDM2 bit 2. Default function is segment pad and PM5.0 = 0 to inhibit LCD waveform abnormal. O/IO LCD segment output pads, and can be shared as general input/output by register LCDM2 bit 1. PM4 register is used to select input or output while shared I/O function is active. Default function is segment pad and PM4.3 = 0 to inhibit LCD waveform abnormal. O/IO LCD segment output pads, and can be shared as general input/output by register LCDM2 bit 0. PM4 register is used to select input or output while shared I/O function is active. Default function is segment pad and PM4.2 = 0 to inhibit LCD waveform abnormal. SEG56/PORTJ.0 SEG59/PORTJ.3 SEG60/PORTI.0 SEG63/PORTI.3 -7- Publication Release Date: May 21, 2003 Revision A8 W536030T/060T/090T/120T PAD Description, continued SYMBOL I/O FUNCTION COM0−COM15 O LCD common signal output pads either 1/32 duty or 1/16 duty. The LCD frame rate is controlled by LCDM1 register, and default value LCDM1 = 0111b with 64Hz frame rate. COM16−COM23 O LCD common signal output pads while 1/32 duty is active. The LCD frame rate is controlled by LCDM1 register, and default value LCDM1 = 0111b with 64Hz frame rate. O/O LCD common signal output pads, or shared as general output by register LCDM3.2 when in 1/16 duty mode. Default function is common function. O/I LCD common signal output pads, or shared as general input by register LCDM3.2 when in 1/16 duty mode. Default function is common function and PM5.2 = 0 to inhibit LCD waveform abnormal. DH1, DH2 (6) O Connection terminal for voltage double capacitor with 0.1uF. The DH2 connects to capacitor positive node and DH1 negative node if polar capacitor is used. V3 ~ V6 (6) O LCD COM/SEG output driving voltage. Need an external 0.1uF capacitor to every pad terminal. I/O Voltage regulator output pad. An external capacitor is a must. Output level can be controlled from 0~Fh by LCDM4 register. If internal pump is enabled (LCDM3.3 = 0 and default value), LCD operating voltage (VLCD) will be 4*V2 or 5*V2 depending on 1/4 bias or 1/5 bias. A limitation should be noted that VLCD must be higher than (VDD -0.5v) to avoid chip leakage current. While external reference voltage is selected (LCDM3.3 = 1), V2 pad input voltage can not be over 1.5 Volt to inhibit chip damage. COM24/PORTP.0 COM27/PORTP.3 COM28/PORTO.0 COM31/PORTO.3 V2 (6) VSSP I Power ground for PWM or DAC playing output. VSSA (7) I Power ground. (For w536090/120T only) VSS I Power ground VDDP I Power source for PWM or DAC playing output. VDDA (7) I Power source. (For w536090/120T only) VDD I Power source. Notes: (4). RD1~3 are shared as CLK/DATA/ADDR to interface with W55XXX @W536030T/060T (5). @W536120T only (6). 0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over 0.5mm*0.5mm. (7). External application circuit should connect together, please refer to APPLICATION CIRCUIT. To sure chip operation properly, please bond all VDDP, VDDA, VDD, VSSP, VSS and VSSA pads and connect VSSP, VSS from chip outside PCB circuit. VSSA and VDDA are for W536090/120T only (8). When working at NMOS open drain mode, external pull high voltage can't higher than VDD to avoid leakage current. -8- W536030T/060T/090T/120T 5. ELECTRICAL CHARACTERISTICS 5.1 Absolute Maximum Ratings PARAMETER RATING UNIT Supply Voltage to Ground Potential -0.3 to +7.0 V Applied Input/Output Voltage -0.3 to +7.0 V 120 mW 0 to +70 °C -55 to +150 °C Power Dissipation Ambient Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 5.2 DC Characteristics (VDD−VSS = 3.0V, No load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD panel on with dot size 0.5mm*0.5mm; unless otherwise specified) PARAMETER SYM. Op. Voltage VDD Op. Current IOP1 CONDITIONS MIN. TYP. MAX. UNIT 5.5 V 600 700 µA 2.4 Dual clock with crystal - (No Load, no Voice, Dual clock with Ring type 600 700 No Melody) Sub-clock only, LCD off 40 50 Sub-clock only, LCD on 70 90 IOP2 Sub-clock active only 6 10 µA IOP3 Sub-clock active only 70 µA Stop Mode Current IOP4 LCD auto off 1 µA CLK/ADDR Output High Current IoH1 Vout = 2.7V -0.8 mA CLK/ADDR Output low Current IoL1 Vout = 0.4V 0.8 mA Input Low Voltage VIL - VSS - 0.3 VDD Input High Voltage VIH - 0.7 - 1 VDD Hold Mode Current (No Load, LCD OFF) Hold Mode Current (No load, LCD ON) Port RA, RB, RE, RF Output Low Voltage VABL IOL = 2.0 mA - - 0.4 V Port RA, RB, RE, RF Output High Voltage VABH IOH = -2.0 mA 2.4 - - V -9- Publication Release Date: May 21, 2003 Revision A8 W536030T/060T/090T/120T DC Characteristics, continued PARAMETER SYM. CONDITIONS MIN TYP MAX UNIT Pull-up Resistor RCD Port RC, RD 200 300 400 KΩ Share Output RI, RJ, RL, RN, RP Sink Current IOL3 VOL = 0.4V -300 RES Pull-up Resistor RRES PWM1/2 Source Current (9) ISPH - 50 uA 100 Volume Option = 00 -20 (RLOAD = 8Ω between PWM1 Volume Option = 01 -70 And PWM2) Volume Option = 10 -110 Volume Option = 11 -135 Volume Option = 00 20 (RLOAD = 8Ω between PWM1 Volume Option = 01 70 And PWM2) Volume Option = 10 110 Volume Option = 11 135 PWM1/2 Sink Current (9) ISPL 200 KΩ mA mA DAC output Current IDAC VDD = 3v, RL=100ohm -4 -5 -6 mA LCD Supply Current ILCD No Load, All Seg. ON - 50 - µA COM/SEG On Resistor RON IOH = ±50 µA 5K 10K Ω V2 Pad Output Voltage VRR Depended on LCDM4 1.45 V V2 Pad Output Deviation (10) VD1 No Load ±5 % V2 Pad Voltage Step VR2 LCDM4 increased 1 VLCD 1/4 Bias & no load V6 Pad Output Voltage (LCD's VLCD depended on LCDM4 register) (10) V2 Input Voltage 1/5 Bias & no load VEXT 0.7 50 3.8 3.85 3.9 * V2 * V2 * V2 4.75 4.8 4.85 * V2 * V2 * V2 LCDM3.3 = 1 Notes: (9) PWM current deviation will be ±20%. (10) VLCD deviation is governed by LCD dot size. More larger LCD dot will get larger deviation. - 10 - mV 1.5 V V W536030T/060T/090T/120T 5.3 AC Characteristics (VDD−VSS = 3.0V, No load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD on with dot size 0.5mm*0.5mm; unless otherwise specified) PARAMETER SYM. CONDITIONS Sub-clock Frequency FSUB Crystal type and X32IN and X32O with 17pF external cap. Main-clock Frequency FM Ring type/Crystal type Chip Operation Frequency FOSC MIN. TYP. MAX. 32768 400K SCR0.0 = 1, FSYS = FSUB SCR0.0 = 0; FSYS = FMAIN - UNIT Hz 4M 32768 Hz Hz 400K - 4M Instruction Cycle Time TCYC One machine cycle - 4/FOSC - S Reset Active Width TRAW FOSC = 32.768 KHz 1 - - µS Interrupt Active Width TIAW FOSC = 32.768 KHz 1 - - µS Main clock Ring frequency FRXIN RXIN = 680KΩ 1M RXIN = 330K Ω 2M RXIN = 200KΩ 3M RXIN = 130KΩ 4M 32 (11) Sub-Clock RC Oscillator FRSUB RSUB = 680KΩ Sub-Clock Oscillation Stable Time @ Cold Start FSTOP RSUB = 680KΩ Frequency Deviation of main-clock FRXIN ≤ 2MHz ∆f Frequency Deviation of main-clock FRXIN = 3MHz ∆f Frequency Deviation of main-clock FRXIN = 4 MHz ∆f ROSC Frequency Frequency Deviation of FROSC = 3MHz Frame frequency f f f FROSC ∆f f FLCD 0.8 Hz KHz 1 S f(3V) − f(2.4V) f(3V) 10 % f(3V) − f(2.4V) f(3V) 15 % f(3V) − f(2.4V) f(3V) 20 % 3 ROSC = 680KΩ f(3V) − f(2.4V) f(3V) MHz 7.5 LCDM1 = 0111 b (default) 64 % Hz Notes: (11). The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor - 11 - Publication Release Date: May 21, 2003 Revision A8 W536030T/060T/090T/120T Iop Vs. Main clock RC mode 1000 800 600 Iop (uA) 3V 4.5V 400 200 0 1 2 3 4 Freq (MhZ) Oscillation Freq Vs. Sub-Clock 44 40 36 3V 4.5V Fsub (KhZ) 32 28 24 20 560 620 680 750 Rsub (Kohm) - 12 - 820 1K W536030T/060T/090T/120T Main Freq Vs. Rxin 6 5 2.4V 3v 4.5V 5.5V 4 Fmain 3 (MhZ) 2 1 0 130 150 160 200 330 680 2K 3K RXIN (Kohm) Voice Operating Freq. Vs. ROSC Freq (MhZ) 4.5 4 3.5 3 2.5 2 3V 4.5V 470 560 680 910 ROSC (Kohm) - 13 - Publication Release Date: May 21, 2003 Revision A8 W536030T/060T/090T/120T 6. TYPICAL APPLICATION CIRCUITS 6.1 Sub Clock with RC Mode 1/5 Bias 1/32 Duty VDDP VDDP (*2 ) Q1 SPEAKER SEG0~63 COM0~31 6 4 S E G *3 2 C O M LCD Panel V L C D > V D D -0 .5 V 8 05 0 470 R5 S W IT C H P W M 1 /D A C R4 C2 B atte ry VDD C L K /R D 1 W 55M XX D A T A /R D 2 W 536XXXT A D D R /R D 3 DH2 R osc C3 VDDP C6 PW M2 VD DP VDDA SPEAKER (*4 ) _ __ RES C4 C1 (*3 ) R3 DH1 C14 V6 C13 C5 V5 R1 X IN C12 (*4 ) (*1 ) V4 X 3 2 IN C 11 V3 R2 C10 X 3 2IO V2 C9 4.7uF C2~C4 0.1uF C5~C6 100pF C7~C8 - VSS Value C1 VSSP VSSA COMPONENT (*5 ) C9~C14 0.1~1uF R1 680KΩ R2 R3 R4 680KΩ 650KΩ/1MHz 350KΩ/2MHz 225KΩ/3MHz 160KΩ/4MHz 100Ω Notes: 1. C9~C14 depends on LCD panel dot size. 2. Option R5 equals to 100Ω if high noise immunity is needed. 3. For DAC option application. 4. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to pad PWM/PWM2 at its best. Under the mask ROM version, C5 and C6 can be skipped. 5. Sure chip operation properly, please bond all VDDP, VDD, VDDA, VSSA, VSSP and VSS; and connect VSSP pad to VSS from external PCB circuit. VSSA and VDDA are for W536090T/120T only. - 14 - W536030T/060T/090T/120T 6.2 Sub Clock with Crystal Mode 1/5 Bias 1/16 Duty 6 4 S E G *1 6 C O M LCD Panel VDDP VDD SEG0~39 CO M0~15 V L C D > V D D -0 .5 V SPEAKER Q1 8050 470 (*2 ) (*3 ) R5 S W IT C H ___ C4 P W M 1 /D A C RES R4 VDD C L K /R D 1 W 536XXXT C2 A D D R /R D 3 R1 C3 W 55M XX D A T A /R D 2 R osc B a tte ry VDDP C6 PW M2 VDDP VDDA C1 SPEAKER (*4 ) DH2 X IN DH1 C14 R3 C5 V6 C13 (*4 ) V5 X 3 2 IN C12 C7 32K V4 C 11 X 3 2 IO (*1 ) V3 C 10 V2 C9 C8 VSS VSSP VSSA (*5 ) COMPONENT C1 C2~C4 C5~C6 C7~C8 C9~C14 R1 R2 R3 R4 Value 4.7uF 0.1uF 100pF 15-30PF 0.1~1uF 680KΩ - 650KΩ/1MHz 350KΩ/2MHz 225KΩ/3MHz 160KΩ/4MHz 100Ω Notes: 1. C9~C14 depends on LCD panel dot size. 2. Option R5 equals to 100Ω if high noise immunity is needed. 3. For DAC option application. 4. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to pad PWM/PWM2 at its best. Under the mask ROM version, C5 and C6 can be skipped. 5. Sure chip operation properly, please bond all VDDP, VDD, VDDA, VSSA, VSSP and VSS; and connect VSSP pad to VSS from external PCB circuit. VSSA and VDDA are for W536090T/120T only. - 15 - Publication Release Date: May 21, 2003 Revision A8 W536030T/060T/090T/120T 7. REVISION HISTORY VERSION DATE WRITER A2 Aug. 10, 1999 YCHuang A3 Aug. 23,1999 Judy Kuo A4 April 13, 2000 Judy Kuo A5 Sep. 10, 2000 A6 DESCRIPTION • MASK option • W536060A to 12io only, and external speech shared RD port except W536120X Part No • Modify some errors and add "Tri-state serial bus" mask option and cascaded voice ROM function Jimmy Chen • Add Application Circuit Dec. 15, 2000 Jimmy Chen • Add AC Picture A7 May 22, 2001 Jimmy Chen • Application circuit modify A8 May 21, 2003 Jimmy Chen • Application circuit modify • Melody Function Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded updates. No representation or warranty is given and no liability is assumed by Winbond Electronics Corp. with respect to the accuracy or use of such information, or infringement of patents or other intellectual property. - 16 -