ETC W536020K

GENERAL DESCRIPTION
TM
The W536XXXK, a member of ViewTalk family, is a high-performance 4-bit micro-controller (uC) with
built-in speech unit, melody unit and 40seg * 8 com LCD driver unit which includes internal regulator,
pump circuit and dedicated one page LCD RAM. The 4-bit uC core contains dual clock source, 4-bit
ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and
8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with
maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to
512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation.
It is ideal for games, educational toys, remote controllers, watches, clocks and other application
products which incorporate both LCD display and speech.
Body
W536020K
W536030K
W536090K
Voice
I/O pad
20 sec
4I/O,8I
(RA/RC/RD)
30 sec
4I/O, 8I
(RA/RC/RD)
90 sec
120 sec
8I/O, 8I, 8O
8I/O, 8I, 8O
(RA/RB/RC/RD/RE/RF) (RA/RB/RC/RD/RE/RF)
W536120K
WDT
disable/Enable
Y
Y
Y
Y
(Mask Option)
Sub-clock
RC/XTAL mode
Y
Y
Y
Y
(Mask Option)
RD port shared as
serial bus
N
Y(1)
N
N (2)
(Mask Option)
Tri-state serial bus
Y
Y
Y
Y
(Mask Option) ( 3)
Cascaded Voice
ROM through
N
Y(1)
N
Y
serial bus (2)
(1) Share 3 pads of RD port (RD1/RDP, RD2/SPDATA and RD3/WRP)
(2) Dedicate serial bus 3 pads (RDP, SPDATA and WRP) to interface with W55XXX. Cascaded
Voice ROM can help to expand voice up to 512 sec by W55XXX chip.
(3) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this
mask option is disabled to get minimum power consumption in general.
FEATURES
• Operating voltage: 2.4 volt ~ 5.5 volt
• Watch dog disabled/enabled by mask option
• Dual clock operating system
− Main clock with RC/Crystal (400 KHz to 4 MHz)
− Sub-clock with 32.768 KHz RC/Crystal by mask option
• Memory
-1-
Publication Release Date: Nov 2000
Revision A1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
− Program ROM (P-ROM): 16K × 20 (ROM Bank0)
− Data RAM (W-RAM): 1K × 4 bit
(RAM Bank 0 is 512 nibbles from 0:000 ~0:1FF and 0:380~0:3FF are mapped to special register.
RAM Bank F is 512 nibbles from F:200 ~F:3FF either data RAM or dedicated to script kernel )
− LCD RAM (L-RAM): 80× 4 bit (RAM Bank1 from 200~24F)
Maximum 24 input/output pads
− Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory
W55XXX interface @W536030K)
− Ports for output only: 8 pads (RE & RF port; W536090K/120K available only)
− Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536090K/120K only)
Power-down mode
− Hold mode (except for 32kHz oscillator)
− Stop mode (including 32kHz oscillator and release by RD or RC port)
Eight types of interrupts
− Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody)
− Three external interrupts (Port RC, RD, RA)
One built-in 14-bit clock frequency divider circuit
Two built-in 8-bit programmable countdown timers
− Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
− Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0
Built-in 18/14-bit watchdog timer for system reset.
Powerful instruction sets
8-level subroutine (including interrupt) nesting
LCD driver unit capability
− VLCD higher than (VDD-0.5V)
− Built-in voltage regulator to V2 pad
− 40 seg × 8 com
− 1/8 or 1/4 duty, 1/4 or 1/3 bias, internal pump circuit option by special register
− COM 4~ 7 and SEG16~39 can be shared as general input/output by special register
− Either uC ROM or voice ROM used as LCD picture
Speech function
− Provided 640K / 1M/ 3M/ 4M bits Voice ROM for W536020K/030K/090K/120K based on 5 bits
MDPCM algorithm
− Voice ROM (V-ROM) available for uC data or LCD picture data.
− Maximum 8*256 Label/Interrupt vector (voice section number) available
− Provide two types of speech busy flag to either each GO or each trigger
− Maximum up to 16M bits speech address capability interface with external memory W55XXX
through serial bus.
Melody function
− Provide 1K notes (22bits/note) dedicated melody ROM
− Provide two types of melody busy flag to uC either each note or each song
− Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7
− Tremolo, triple frequency and 3 kinds of percussion available
− Maximum 31 songs available
Can mix speech with melody
Multi-engine controller
Direct driving speaker/buzzer or DAC output
Chip On Board available
-2-
Publication Release Date:Nov 2000
Revision A1
BLOCK DIAGRAM
V3,V5,V6
COM0~7
SEG0~39
LCD DRIVER
RAM
1K*4Bit
VHI
V2
DH1,DH2
VLCD PUMP &
REGULATOR
VDD
TEST
PORT RA
ACC
ROM
RA0~3
TONE
PORT RB
16K*20Bit
RB0~3
ALU
PORT RC
RC0~3
RD0~3
PORT RD
PC
Special Register
IEF
STACK
(8 Levels)
HEF
HCF
SPC
PEF
EVF
MLD FLAG0
FLAG1 PM0
MR0
PSR0
LPX0 LPX1
LPX2
LPX3
LPX4 LPX5
LPY0
LPY1
Timer 1
Interrupt ,Hold &
Stop Control
MLD_busy
Timing
Generator
Divide
PORT RF
RF0~3
WRP
RDP
SPDATA
to Serial
MLD_play
Watch Dog
RE0~3
Parallel
SPC_bus
y
SPC_pla
y
Timer 0
PORT RE
ROSC
MDPCM
Speech
Voice ROM
(640K/1M/3M/4
M)
Dual
Tone
Melody
PWM/
DAC
MIX
Block
PWM1/DAC
PWM2
VSS
VDDP
VSSP
RES
XIN
XOUT X32I X32O
-3-
Publication Release Date:Nov 2000
Revision A1
PAD DESCRIPTION
SYMBOL
XIN/RXIN
I/O
I
FUNCTION
Input pad for main clock oscillator. It can be connected to crystal when crystal
mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate
main system clock while RC mode is selected (SCR0.2=0 and default). Oscillator
can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External
capacitor connects to start oscillation while crystal mode
XOUT
O
Output pad for oscillator which is connected to another crystal pad when in crystal
mode. External capacitor connects to start oscillation when in crystal mode.
X32I/RSUB1
I
32.768 KHz crystal input pad or external resistor node 1 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
X32O/RSUB2
O
32.768 KHz crystal output pad or external resistor node 2 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
RA0 ~ RA3/TONE
I/O
General Input/Output port specified by PM1 register. If output mode is selected,
PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special
register is set to logic 1. An interrupt source.
RB0 ~ RB3
I/O
General Input/Output port specified by PM2 register. If output mode is selected,
PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode (W536090K/120K only.)
RC0 ~ RC3
I
4-bit schmitter input with internal pull high option specified by PM3 register bit 2.
Each pad has an independent interrupt capability specified by PEFL special
register. Interrupt and STOP mode wake up source. RC0 is also the external
event counter source of Timer1.
RD0
RD1/RDP
RD2/SPDATA
RD3/WRP
(4)
I
4-bit schmitter input port with internal pull high option specified by PM3 register
bit 3. Each pad has an independent interrupt capability specified by PEFH
special register. Interrupt and STOP mode wake up source. RD1~3 will be
shared as the external memory W55XXX interface pads while RD port shared as
serial bus mask option is enabled @W536030K.
For W536030A/060A only, "Tri-state serial bus" mask option can use to float
WRP/RDP/SPDATD while "RD port shared as serial bus" mask option is
enabled.
RE0~RE3
O
Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving
capability option. (W536090K/120K only)
RF0~RF3
O
Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving
capability option. (W536090K/120K only)
I
System reset pad, active low with internal pull-high resistor.
I
Test pad. Active high with internal pull low resistor.
RES
TEST
-4-
Publication Release Date:Nov 2000
Revision A1
ROSC
I
Connect resistor to VDD pad to generate speech or melody playing clock source.
PWM1/DAC
O
While speech or melody is active, PWM1/DAC is speaker direct driving output or
DAC output controlled by voice output file.
PWM2
O
While speech or melody is active, PWM2 is another speaker direct driving output.
WRP (5)
O
External serial memory address write clock for voice extension (W536120K only).
RDP (5)
O
External serial memory address read clock for voice extension. (W536120K only).
SPDATA (5)
I/O
External serial memory data in/out for voice extension (W536120K only).
SEG0−SEG15
O
Dedicated LCD segment output pads.
SEG16/PORTN.0

SEG19/PORTN.3
SEG20/PORTM.0

SEG23/PORTM.3
O/O
LCD segment output pads, and can be shared as general output by register
LCDM3 bit 1. Default function is segment pad.
O/I
LCD segment output pads, and can be shared as general input by register
LCDM3 bit 0. Default function is segment pad and PM5.1=0 to inhibit LCD
waveform abnormal.
SEG24/PORTL.0

SEG27/PORTL.3
SEG28/PORTK.0

SEG31/PORTK.3
O/O
LCD segment output pads, and can be shared as general output by register
LCDM2 bit 0. Default function is segment pad.
O/I
LCD segment output pads, and can be shared as general input by register
LCDM2 bit 1. Default function is segment pad and PM5.0=0 to inhibit LCD
waveform abnormal.
SEG32/PORTJ.0

SEG35/PORTJ.3
O/IO
LCD segment output pads, and can be shared as general input/output by register
LCDM2 bit 2. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.3=0 to inhibit LCD
waveform abnormal.
SEG36/PORTI.0

SEG39/PORTI.3
O/IO
LCD segment output pads, and can be shared as general input/output by register
LCDM2 bit 3. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.2=0 to inhibit LCD
waveform abnormal.
COM0−COM3
O
LCD common signal output pads either 1/8 duty or 1/4duty. The LCD frame rate
is controlled by LCDM1 register, and default value LCDM1=0111b with 64Hz
frame rate.
COM4/PORTO.0

COM7/PORTO.3
O/I
LCD common signal output pads, or shared as general input by register LCDM3.2
when in 1/4 duty mode. Default function is common function and PM5.2=0 to
inhibit LCD waveform abnormal.
DH1, DH2 (6)
O
Connection terminal for voltage double capacitor with 0.1uF. The DH2 connects
to capacitor positive node and DH1 negative node if polar capacitor is used.
VHI
I
Connect to V6 (LCD's VLCD) or VDD which has higher voltage, to make sure there is no
any abnormal leakage current appearance.
-5-
Publication Release Date:Nov 2000
Revision A1
V3
O
LCD COM/SEG output driving voltage. Need an external 0.1uF capacitor when 1/4 bias.
(LCDM0.1=1)
V5 V6 (6)
O
LCD COM/SEG output driving voltage. Need an external 0.1uF capacitor to every
pad terminal.
V2 (6)
I/O
Voltage regulator output pad. An external capacitor is a must. Output level can
be controlled from 0~Fh by LCDM4 register. If internal pump is enabled
(LCDM3.3=0 and default value), LCD operating voltage (VLCD) will be 3*V2 or
4*V2 depending on 1/3 bias or 1/4 bias. A limitation should be noted that VLCD
must be higher than (VDD-0.5v) to avoid chip leakage current. While external
reference voltage is selected (LCDM3.3=1), V2 pad input voltage can not be over
1.5 Volt to inhibit chip damage.
VSSP (7)
I
Power ground for PWM or DAC playing output.
VSS (7)
I
Power ground
VDDP (7)
I
Power source for PWM or DAC playing output.
VDD (7)
I
Power Source
(4) RD1~3 are shared as RDP/SPDATA/WRP to interface with W55XXX @W536030K.
(5) @W536120K only
(6) 0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over
0.5mm * 0.5mm.
(7) External application circuit should connect together, please refer to APPLICATION CIRCUIT. To
sure chip operation properly, please bond all VDD, VDDP, VSS and VSSP pads and connect VSS
and VSSP from chip outside PCB circuit.
(8) VHI pad is bonded to V6 or VDD.
-6-
Publication Release Date:Nov 2000
Revision A1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage to Ground Potential
Applied Input/Output Voltage
Power Dissipation
Ambient Operating Temperature
Storage Temperature
RATING
-0.3 to +7.0
-0.3 to +7.0
120
0 to +70
-55 to +150
UNIT
V
V
mW
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect
the life and reliability of the device.
DC CHARACTERISTICS
(VDD−VSS = 3.0V, no load, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C,
STN LCD panel on with dot size 0.5mm*0.5mm; unless otherwise specified)
PARAMETER
Op. Voltage
Op. Current
(No Load, no Voice, no )
Melody)
SYM.
VDD
IOP1
MAX
5.5
700
700
50
90
5
UNIT
V
uA
Hold Mode Current
(No Load, LCD OFF)
Hold Mode Current
(No load, LCD ON)
Stop Mode Current
RDP/WRP Output High
Current
RDP/WRP Output low
Current
Input Low Voltage
Input High Voltage
Port RA, RB Output Low
Voltage
Port RA, RB Output High
Voltage
Pull-up Resistor
RES Pull-up Resistor
PWM1/2 Source Current (8)
IOP2
Dual clock with crystal
Dual clock with RC type
Sub-clock only, LCD off
Sub-clock only, LCD on
Sub-clock active only
IOP3
Sub-clock active only
35
uA
IOP4
IoH1
LCD auto off
Vout=2.7V
1
-0.8
uA
mA
IoL1
Vout=0.4V
0.8
mA
VIL
VIH
VABL
IOL = 2.0 mA
VSS
0.7
-
-
0.3
1
0.4
VDD
VDD
V
VABH
IOH = -2.0 mA
2.4
-
-
V
RCD
RRES
ISPH
Port RC, RD
Volume Option =00
Volume Option =01
200
50
300
100
-20
-70
400
200
KΩ
KΩ
mA
(RLOAD =8Ω between PWM1
And PWM2 )
PWM1/2 Sink Current (8)
(RLOAD =8Ω between PWM1
And PWM2 )
ISPL
CONDITIONS
MIN
2.4
-
TYP
600
600
40
70
3
Volume Option =10
Volume Option =11
Volume Option =00
Volume Option =01
-110
-135
20
70
Volume Option =10
Volume Option =11
110
135
-7-
uA
mA
Publication Release Date:Nov 2000
Revision A1
VRR
VDD=3v, RL=100ohm
No Load, All Seg. ON
IOH = ± 50 µA
Depended on LCDM4
V2 Pad Output Deviation (9)
VD1
No Load
V2 Pad Voltage Step
VR2
VLCD
LCDM4 increased 1
DAC output Current
LCD Supply Current
COM/SEG On Resistor
V2 Pad Output Voltage
V6 Pad Output Voltage
(LCD's VLCD depended on
LCDM4 register) (9)
IDAC
ILCD
RON
1/3 Bias & no load
1/4 Bias & no load
-4
-
-5
50
5K
0.7
-6
10K
1.45
mA
µA
Ω
V
±5
%
50
2.85
* V2
3.8
* V2
2.9
* V2
3.85
* V2
mV
2.95
* V2
3.9
* V2
1.5
V
V2 input voltage
VEXT
LCDM3.3=1
V
(8)
PWM current deviation will be ±20%.
(9)
Deviation is governed by LCD dot size. More larger LCD dot will get larger deviation..
AC CHARATERISTICS
(VDD−VSS = 3.0V, no load, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C,
STN LCD on with dot size 0.5mm*0.5mm; unless otherwise specified)
PARAMETER
SYM.
CONDITIONS
MIN. TYP.
MAX. UNIT
Sub-clock Frequency
FSUB
Crystal type and X32IN
32768
Hz
and X32O with 17pF
external cap.
Main-clock Frequency
FM
RC type/Crystal type
400K 4M
Hz
Chip Operation Frequency
FOSC
32768
Hz
SCR0.0=1,FSYS=FSUB
4M
SCR0.0=0;FSYS= FMAIN 400K Instruction Cycle Time
TCYC
One machine cycle
4/FOSC
S
Reset Active Width
TRAW
FOSC = 32.768 KHz
1
µS
Interrupt Active Width
TIAW
FOSC = 32.768 KHz
1
µS
Main clock RC frequency
FRXIN
1M
Hz
RXIN =680KΩ
2M
(10)
RXIN =330K Ω
3M
RXIN =200KΩ
4M
RXIN =130KΩ
Sub-Clock Ring Oscillator
FRSUB
32
KHz
RSUB=680KΩ
Sub-Clock Oscillation
0.8
1
S
FSTOP
RSUB=680KΩ
Stable Time @ Cold Start
10
%
Frequency Deviation of
f(3V) − f(2.4V)
∆f
f
main-clock FRXIN ≤ 2MHz
f(3V)
15
%
Frequency Deviation of
f(3V) − f(2.4V)
∆f
main-clock FRXIN = 3 MHz f
f(3V)
20
%
Frequency Deviation of
f(3V) − f(2.4V)
∆f
main-clock FRXIN =4 MHz
f
f(3V)
ROSC Frequency
FROSC
3
MHz
ROSC=680KΩ
7.5
%
Frequency Deviation of
f(3V) − f(2.4V)
∆f
FROSC = 3MHz
f
f(3V)
Frame frequency
FLCD
LCDM1=0111 b(default)
64
Hz
(10) The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor
Publication Release Date:Nov 2000
-8Revision A1
Iop Vs. Main clock RC mode
1000
800
600
3V
4.5V
400
Iop (uA)
200
0
1
2
3
4
Freq (MhZ)
Oscillation Freq Vs. Sub-Clock
44
40
36
3V
4.5V
Fsub (KhZ) 32
28
24
20
560
620
680
750
820
1K
Rsub (Kohm)
-9-
Publication Release Date:Nov 2000
Revision A1
Main Freq Vs. Rxin
6
5
2.4V
3v
4.5V
5.5V
4
Fmain
3
(MhZ)
2
1
0
130 150 160 200 330 680 2K
3K
RXIN (Kohm)
Voice Operating Freq. Vs. ROSC
Freq (MhZ)
4.5
4
3.5
3
2.5
2
3V
4.5V
470
560
680
910
ROSC (Kohm)
- 10 -
Publication Release Date:Nov 2000
Revision A1
APPLICATION CIRCUIT--1: Sub clock with RC mode
1/4 bias, VLCD=4.5V
40SEG x 8COM LCD
panel
SEG0~39
COM0~7
VDDP
RA0~3
RC0~3
RD0~3
470
VDD
(* 2)
(*3)
R5
RES
C6
PWM1
Battery
VDDP
C8
R4
PWM2
W536xxxK
DH1
C1
DH2
VDD
C7
C5
V6
R1
ROSC
C4
V5
R3
XIN
VHI
X32IN
(*1)
V6
VDD
V3
R2
C3
C2
V2
X32O
Value
VSS2
VSS1
Component
C1~C6
C7,C8
C9,C10
C11
R1
R2
R3
R4
0.1uF
20pF
0.1uF
1uF
680K
-
680Kohm/1Mhz
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
100
Note:
(1) C1~C5 depends on LCD panel dot size.
(2) Option R5 equals to 100Ω if high noise immunity is needed.
(3) For DAC option application.
(4) To sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS .
- 11 -
Publication Release Date:Nov 2000
Revision A1
APPLICATION CIRCUIT---2 : Sub clock with Crystal mode
1/3 bias, VLCD=3V
40SEG x 8COM LCD
panel
SEG0~39
COM0~7
VDDP
RA0~3
RC0~3
RD0~3
470
VDD
( *2)
(*3)
R5
RES
C6
PWM1
Battery
VDDP
C8
W536xxxK
PWM2
DH1
R4
C1
DH2
VDD
C7
C5
V6
R1
ROSC
C4
V5
R3
XIN
(*1)
V6
VHI
C9
X32IN
VDD
32.768kHz
C2
V2
C10
X32O
Value
VSS2
VSS1
Component
C1~C6
C7,C8
C9,C10
C11
R1
R2
R3
R4
0.1uF
20pF
0.1uF
1uF
680K
-
680Kohm/1Mhz
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
100
Note:
(1) C1~C5 depends on LCD panel dot size.
(2) Option R5 equals to 100Ω if high noise immunity is needed.
(3) For DAC option application.
(4) To sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS.
- 12 -
Publication Release Date:Nov 2000
Revision A1