W536030P/060P/090P/120P VOICE & MELODY CONTROLLER (ViewTalk TM Series) Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 2 2. FEATURES ................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................... 5 4. PAD DESCRIPTION ................................................................................................................... 6 5. ELECTRICAL CHARACTERISTICS........................................................................................... 7 6. 7. 5.1 Absolute Maximum Ratings............................................................................................... 7 5.2 DC Characteristics............................................................................................................. 8 5.3 AC Characteristics ............................................................................................................. 9 TYPICAL APPLICATION CIRCUITS ........................................................................................ 12 6.1 Sub Clock with RC Mode................................................................................................. 12 6.2 Sub Clock with Xtal Mode................................................................................................ 13 REVISION HISTORY ................................................................................................................ 14 -1- Publication Release Date: May 21, 2003 Revision A4 W536030P/060P/090P/120P 1. GENERAL DESCRIPTION The W536XXXP, a member of ViewTalkTM family, is a high-performance 4-bit micro-controller (uC) with built-in 8KW uC program. The 4-bit uC core contains dual clock source, 4-bit ALU, two 8-bit timers, one 14 bits divider, maximum 32 pads for input or output, 8 interrupt sources and 8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM), is capable of expanding to 512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation. It is ideal for educational toys, remote controllers and other application products which incorporate both melody and speech. BODY Voice I/O pad WDT disable/Enable (Mask Option) W536030P W536060P W536090P W536120P 30 sec 60 sec 90 sec 120 sec 8I/O, 8I 8I/O, 8I 8I/O, 12I, 12O 8I/O, 12I, 12O (RA/RB/RC/RD) (RA/RB/RC/RD) (RA/RB/RC/RD/RE /RF/RG/RH) (RA/RB/RC/RD/RE/ RF/RG/RH) Y Y Y Y Y Y Y Y Y Y Y Y Y Y N Y Sub-clock RC/XTAL mode (Mask Option) Tri-state serial bus (Mask Option)( 1) Cascaded Voice through serial bus (2) Notes: 1. Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this mask option is disabled to get minimum power consumption in general. 2. Cascaded Voice ROM user option help to expand voice up to 512 sec through serial bus by W55XXX chip. -2- W536030P/060P/090P/120P 2. FEATURES • Operating voltage: 2.4 volt ~ 5.5 volt • Watch dog disabled/enabled by mask option • Dual clock operating system − Main clock with Ring/Crystal (400 KHz to 4 MHz) − Sub-clock with 32.768 KHz RC/Crystal by mask option • Memory − Program ROM (P-ROM): 8 K × 20 (ROM Bank0) − Data RAM (W-RAM): 1K × 4 bit (RAM Bank 0 is 512 nibbles from 0: 000~0: 1FF and 0:380~0:3FF are mapped to special register. RAM Bank F is 512 nibbles from F: 200~F: 3FF either data RAM or dedicated to script kernel) • Maximum 32 input/output pads − Ports for input only: 12 pads (RC, RD and RG port; RG for W536090P/120P only) − Ports for output only: 12 pads (RE, RF and RH port; RH for W536090P/120P only) − Ports for Input/output: 8 pads • Power-down mode − Hold mode (except for 32KHz oscillator) − Stop mode (including 32KHz oscillator and release by RD or RC port) • Eight types of interrupts − Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody) − Three external interrupts (Port RC, RD, RA) • One built-in 14-bit clock frequency divider circuit • Two built-in 8-bit programmable countdown timers − Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected − Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0 • Built-in 18/14-bit watchdog timer for system reset. • Powerful instruction sets. • 8-level subroutine (including interrupt) nesting -3- Publication Release Date: May 21, 2003 Revision A4 W536030P/060P/090P/120P • Speech function − Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030P/060P/090P/120P based on 5 bits MDPCM algorithm − Voice ROM (V-ROM) available for uC data. − Maximum 8*256 Label/Interrupt vector (voice section number) available − Provide two types of speech busy flag to either each GO or each trigger − Maximum up to 16M bits speech address capability interface with external memory W55XXX through serial bus. • Melody function − Provide 1K notes (22bits/note) dedicated melody ROM − Provide two types of melody busy flag to uC either each note or each song − Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7 − Tremolo, triple frequency and 3 kinds of percussion available − Maximum 31 songs available • Can mix speech with melody • Multi-engine controller • Direct driving speaker/buzzer or DAC output • Chip On Board available -4- W536030P/060P/090P/120P 3. BLOCK DIAGRAM Data R AM 1K* 4Bit PORT RA RA0~3 PORT RB RB0~3 PORT RC R C 0~3 PORT RD R D 0~3 P OR T R E PO RE0~3 PORT RF R F0~3 PO R T R G R G 0~3 TO NE ACC ROM 8K*20Bit ALU PC S TAC K (8 Levels) Special Register IE F HEF P EF EV F HCF SP C M LD FLAG 0 LPX 0 MR PM 0 0 LPX 1 LP X 2 LPX 4 LPX 5 LP Y 0 FLAG 1 PO R T R H Parallel to Serial PS R0 LP X 3 SP C_busy S PC _play LP Y 1 LP XY S hared_RO M Data Speech M DPC M core R H 0~3 AD D R CLK D ATA VD D A R O SC VSSA VSSP Tim er 0 (8 Bit) Tim er 1 (8 Bit) Interrupt ,H old & Stop C ontrol M LD _busy V oice RO M (1M /2M /3M /4M bits) M LD_play W atch Dog Tim er (18/14 Bit) D ivide r (14/10 Bit) Tim ing G enerator XIN XO U T Dual Tone M elody (1K notes) PW M 1/D AC PW M /D AC M ix Block PW M 2 VD DP VD D VSS TES T R ES X32I X32O -5- Publication Release Date: May 21, 2003 Revision A4 W536030P/060P/090P/120P 4. PAD DESCRIPTION SYMBOL I/O FUNCTION XIN/RXIN I Input pad for main clock oscillator. It can be connected to crystal when crystal mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate main system clock while Ring mode is selected (SCR0.2=0 and default). Oscillator can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External capacitor connects to start oscillation and get more accurate clock when crystal mode XOUT O Output pad for oscillator which is connected to another crystal pad when in crystal mode. External capacitor connects to start oscillation when in crystal mode. X32I/RSUB1 I 32.768 KHz crystal input pad or external resistor node 1 by mask option. External 15~20pF capacitor connects to start oscillation and get more accurate clock when in crystal mode. X32O/RSUB2 O 32.768 KHz crystal output pad or external resistor node 2 by mask option. External 15~20pF capacitor connects to start oscillation when in crystal mode. I/O General Input/Output port specified by PM1 register. If output mode is selected, PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option. Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special register is set to logic 1. An interrupt source. I/O General Input/Output port specified by PM2 register. If output mode is selected, PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option. Initial state is input mode. I 4-bit schmitter input with internal pull high option specified by PM3 register bit 2. Each pad has an independent interrupt capability specified by PEFL special register. Interrupt and STOP mode wake up source. RC0 is also the external event counter source of Timer1. I 4-bit schmitter input port with internal pull high option specified by PM3 register bit 3. Each pad has an independent interrupt capability specified by PEFH special register. Interrupt and STOP mode wake up source. O Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving capability option. O Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving capability option. I Input port with internal pull high option specified by PM6 register bit 0. (W536090P/W536120P only) O Output port only. PM6 register bit 1 can be used to specify CMOS/NMOS driving capability option. (W536090P/W536120P only) I System reset pad, active low with internal pull-high resistor. RA0 ~ RA3/TONE (4) RB0 ~ RB3 (4) RC0 ~ RC3 RD0 ~ RD3 RE0~RE3 (4) RF0~RF3 (4) RG0 ~ RG3 RH0 ~ RH3 (4) RES -6- W536030P/060P/090P/120P PAD Description, continued SYMBOL I/O FUNCTION TEST I Test pad. Active high with internal pull low resistor. ROSC I Connect resistor to VDD pad to generate speech or melody playing clock source. PWM1/DAC O While speech or melody is active, PWM1/DAC is speaker direct driving output or DAC output controlled by voice output file. PWM2 O While speech or melody is active, PWM2 is another speaker direct driving output. ADDR O External serial memory address write clock for voice extension. CLK O External serial memory address read clock for voice extension. DATA I/O External serial memory data in/out for voice extension. VSS I Chip ground. VSSP I Chip ground for PWM or DAC playing output. VSSA (3) I Chip ground. (W536090P/120P only) VDD I Power source. VDDP I Power source for PWM or DAC playing output. VDDA (3) I Power source. (W536090P/120P only) Notes: (3). VDDA, VSSA for W536090P/120P only. To sure chip operation properly, please bond all VDD, VDDA, VDDP, VSS, VSSA and VSSP pads, and connect VSS, VSSP form chip external PCB circuit. (4). When working at NMOS open drain mode, external pull high voltage can't higher than VDD to avoid leakage current. 5. ELECTRICAL CHARACTERISTICS 5.1 Absolute Maximum Ratings PARAMETER RATING UNIT Supply Voltage to Ground Potential -0.3 to +7.0 V Applied Input/Output Voltage -0.3 to +7.0 V 120 mW 0 to +70 °C -55 to +150 °C Power Dissipation Ambient Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. -7- Publication Release Date: May 21, 2003 Revision A4 W536030P/060P/090P/120P 5.2 DC Characteristics (VDD−VSS = 3.0V, No load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C unless otherwise specified) PARAMETER SYM. Op. Voltage VDD Op. Current IOP1 CONDITIONS MIN TYP MAX UNIT 5.5 V 400 500 µA 2.4 Dual clock with crystal - (No Load, no Voice, no Dual clock with Ring type 400 500 Melody) Sub-clock only 15 30 Sub-clock active only 4 6 µA 1 µA Hold Mode Current IOP2 Stop Mode Current IOP3 CLK/ADDR Output High Current IoH1 Vout = 2.7V -0.8 mA CLK/ADDR Output low Current IoL1 Vout = 0.4V 0.8 mA Input Low Voltage VIL - VSS - 0.3 VDD Input High Voltage VIH - 0.7 - 1 VDD Port RA, RB, RE, RF and RH Output Low Voltage VABL IOL = 2.0 mA - - 0.4 V Port RA, RB, RE, RF and RH Output High Voltage VABH IOH = -2.0 mA 2.4 - - V Pull-up Resistor RCD Port RC, RD, RG 200 300 400 KΩ RES Pull-up Resistor RRES - 50 100 200 KΩ PWM1/2 Source Current (4) ISPH Volume Option = 00 -20 (RLOAD = 8Ω between PWM1 Volume Option = 01 -70 And PWM2) Volume Option = 10 -110 Volume Option = 11 -135 Volume Option = 00 20 (RLOAD = 8Ω between PWM1 Volume Option = 01 70 And PWM2) Volume Option = 10 110 Volume Option = 11 135 PWM1/2 Sink Current (4) DAC output Current ISPL IDAC VDD = 3V, RL = 100ohm Notes: (4). PWM current deviation will be ±20%. -8- -4 -5 mA mA -6 mA W536030P/060P/090P/120P 5.3 AC Characteristics (VDD−VSS = 3.0V, No load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C unless otherwise specified) PARAMETER SYM. CONDITIONS Sub-clock Frequency FSUB Crystal type and X32IN and X32O with 17pF external cap. Main-clock Frequency FM Ring type/Crystal type Chip Operation Frequency FOSC MIN. TYP. MAX. 32768 400K SCR0.0 = 1, FSYS = FSUB - Hz 4M 32768 SCR0.0 = 0; FSYS = FMAIN UNIT Hz Hz 400K - 4M Instruction Cycle Time TCYC One machine cycle - 4/FOSC - S Reset Active Width TRAW FOSC = 32.768 KHz 1 - - µS Interrupt Active Width TIAW FOSC = 32.768 KHz 1 - - µS Main clock Ring frequency FRXIN RXIN = 680KΩ 1M RXIN = 330K Ω 2M RXIN = 200KΩ 3M RXIN = 130KΩ 4M 32 Sub-Clock RC Oscillator FRSUB RSUB = 680KΩ Sub-Clock Oscillation Stable Time @ Cold Start FSTOP RSUB = 680KΩ Frequency Deviation of main-clock FRXIN ≤ 2 MHz ∆f Frequency Deviation of main-clock FRXIN = 3 MHz ∆f Frequency Deviation of main-clock FRXIN = 4 MHz ∆f ROSC Frequency Frequency Deviation of FROSC = 3MHz f f f FROS C ∆f f 0.8 Hz KHz 1 S f(3V) − f(2.4V) f(3V) 10 % f(3V) − f(2.4V) f(3V) 15 % f(3V) − f(2.4V) f(3V) 20 % 3 ROSC = 680KΩ f(3V) − f(2.4V) f(3V) MHz 7.5 % Notes: (5). The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor -9- Publication Release Date: May 21, 2003 Revision A4 W536030P/060P/090P/120P Iop Vs. Main clock RC mode 800 600 3V 4.5V 400 Iop (uA) 200 0 1 2 3 4 Freq (MhZ) Oscillation Freq Vs. Sub-Clock 44 40 36 3V 4.5V Fsub (KhZ) 32 28 24 20 560 620 680 750 Rsub (Kohm) - 10 - 820 1K W536030P/060P/090P/120P Main Freq Vs. Rxin 6 5 2.4V 3v 4.5V 5.5V 4 Fmain 3 (MhZ) 2 1 0 130 150 160 200 330 680 2K 3K RXIN (Kohm) Voice Operating Freq. Vs. ROSC Freq (MhZ) 4.5 4 3.5 3 2.5 2 3V 4.5V 470 560 680 910 ROSC (Kohm) - 11 - Publication Release Date: May 21, 2003 Revision A4 W536030P/060P/090P/120P 6. TYPICAL APPLICATION CIRCUITS 6.1 Sub Clock with RC Mode VDDP (*1) VDDP R5 SWITCH SPEAKER Q1 ___ RES C4 8050 VDDP VDDA C1 R4 VDD 470 (*3) W536XXXP Rosc C2 C3 Battery PWM1/DAC R1 SPEAKER C6 XIN (*2) R3 VDDP PWM2 (*2) C5 ADDR W55MXX CLK X32IN DATA R2 X32IO C2~C4 Value 4.7uF 0.1uF C5~C6 100pF VSS C1 VSSA VSSP COMPONENT (*4) C7~C8 R1 R2 R3 R4 - 680KΩ 680KΩ 650KΩ/1MHz 350KΩ/2MHz 225KΩ/3MHz 160KΩ/4MHz 100Ω Notes: 1. Option R5 equals to 100Ω if high noise immunity is needed. 2. For DAC option application. 3. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to pad PWM/PWM2 at its best. Under the mask ROM version, C5 and C6 can be skipped. 4. Sure chip operation properly, please bond all VDDP, VDDA, VDD, VSSP, VSSA and VSS; and connect VSSP pad to VSS from external PCB circuit. VDDA, VSSA are only for W536090P/120P. - 12 - W536030P/060P/090P/120P 6.2 Sub Clock with Xtal Mode VDDP (*1) R5 VDDP SWITCH ___ RES C4 SPEAKER Q1 8050 VDDP VDDA R4 C1 C2 Battery VDD 470 W536XXXP (*3) Rosc R1 C3 PWM1/DAC XIN SPEAKER (*2) R3 C6 PWM2 C5 (*2) ADDR X32IN CLK VDDP W55MXX DATA C7 32K X32IO C8 VSS VSSA VSSP (*4) COMPONENT Value C1 4.7uF C2~C4 0.1uF C5~C6 100pF C7~C8 R1 15~30PF 680KΩ R2 R3 R4 - 650KΩ/1MHz 350KΩ/2MHz 225KΩ/3MHz 160KΩ/4M/Hz 100Ω Notes: 1. Option R5 equals to 100Ω if high noise immunity is needed. 2. For DAC option application. 3. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to pad PWM/PWM2 at its best. Under the mask ROM version, C5 and C6 can be skipped. 4. Sure chip operation properly, please bond all VDDP, VDDA, VDD, VSSP, VSSA and VSS; and connect VSSP pad to VSS from external PCB circuit. VDDA, VSSA are only for W536090P/120P. - 13 - Publication Release Date: May 21, 2003 Revision A4 W536030P/060P/090P/120P 7. REVISION HISTORY VERSION DATE WRITER DESCRIPTION A1 April 19, 2000 Judy Kuo (10) W536060A to 12io only, and external speech shared RD port except W536120X Part No A2 Aug. 7, 2000 Jimmy Chen • Speech Function Modify A3 Jun. 1, 2001 Jimmy Chen • Speech Function Modify A4 May 21, 2003 Jimmy Chen • Modify some errors and add "Tri-state serial bus" mask option and cascaded voice ROM function Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded updates. No representation or warranty is given and no liability is assumed by Winbond Electronics Corp. with respect to the accuracy or use of such information, or infringement of patents or other intellectual property. - 14 -