ETC W536020P

GENERAL DESCRIPTION
TM
The W536XXXP, a member of ViewTalk family, is a high-performance 4-bit micro-controller (uC)
with built-in 8KW uC program. The 4-bit uC core contains dual clock source, 4-bit ALU, two 8-bit
timers, one 14 bits divider, maximum 32 pads for input or output, 8 interrupt sources and 8-level
nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with maximum
128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to 512
seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power
dissipation. It is ideal for educational toys, remote controllers and other application products which
incorporate both melody and speech.
Body
W536030P
Voice
I/O pad
30 sec
60 sec
90 sec
8I/O, 12I, 12O
8I/O, 8I
8I/O, 8I
(RA/RB/RC/RD) (RA/RB/RC/RD) (RA/RB/RC/RD/RE/RF
W536060P
W536090P
/RG/RH)
W536120P
120 sec
8I/O, 12I, 12O
(RA/RB/RC/RD/RE/RF
/RG/RH)
WDT disable/Enable
Y
Y
Y
Y
(Mask Option)
Sub-clock
RC/XTAL mode
Y
Y
Y
Y
(Mask Option)
Tri-state serial bus
Y
Y
Y
Y
(Mask Option)( 1)
Cascaded Voice
Y
Y
N
Y
through serial bus (2)
(1) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let
this mask option is disabled to get minimum power consumption in general.
(2) Cascaded Voice ROM user option help to expand voice up to 512 sec through serial bus
by W55XXX chip.
FEATURES
• Operating voltage: 2.4 volt ~ 5.5 volt
• Watch dog disabled/enabled by mask option
• Dual clock operating system
− Main clock with RC/Crystal (400 KHz to 4 MHz)
− Sub-clock with 32.768 KHz RC/Crystal by mask option
• Memory
− Program ROM (P-ROM): 8 K × 20 (ROM Bank0)
− Data RAM (W-RAM): 1K × 4 bit
(RAM Bank 0 is 512 nibbles from 0:000~0:1FF and 0:380~0:3FF are mapped to special register.
RAM Bank F is 512 nibbles from F:200~F:3FF either data RAM or dedicated to script kernel )
• Maximum 32 input/output pads
− Ports for input only: 12 pads (RC, RD and RG port ; RG for W536090P/120P only)
− Ports for output only: 12 pads (RE, RF and RH port; RH for W536090P/120P only)
− Ports for Input/output: 8 pads
-1-
Publication Release Date: Sep 2000
Revision A3
• Power-down mode
− Hold mode (except for 32kHz oscillator)
− Stop mode (including 32kHz oscillator and release by RD or RC port)
• Eight types of interrupts
− Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody )
− Three external interrupts (Port RC, RD, RA)
• One built-in 14-bit clock frequency divider circuit
• Two built-in 8-bit programmable countdown timers
− Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
− Timer 1: built-in auto-reload function includes internal timer, external event counter from
RC.0
• Built-in 18/14-bit watchdog timer for system reset.
• Powerful instruction sets.
• 8-level subroutine (including interrupt) nesting
• Speech function
− Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030P/060P/090P/120P based on 5 bits
MDPCM algorithm
− Voice ROM (V-ROM) available for uC data.
− Maximum 8*256 Label/Interrupt vector (voice section number) available
− Provide two types of speech busy flag to either each GO or each trigger
− Maximum up to 16M bits speech address capability interface with external memory W55XXX
through serial bus.
• Melody function
− Provide 1K notes (22bits/note) dedicated melody ROM
− Provide two types of melody busy flag to uC either each note or each song
− Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7
− Tremolo, triple frequency and 3 kinds of percussion available
− Maximum 31 songs available
• Can mix speech with melody
• Multi-engine controller
• Direct driving speaker/buzzer or DAC output
• Chip On Board available
-2-
Publication Release Date:Sep 2000
Revision A3
BLOCK DIAGRAM
RAM
1K* 4Bit
PORT RA
RA0~3
PORT RB
RB0~3
PORT RC
RC0~3
PORT RD
RD0~3
PORT RE
RE0~3
PORT RF
RF0~3
PORT RG
RG0~3
TONE
ACC
ROM
8K*20Bit
ALU
PC
STACK
(8 Levels)
Special Register
IEF
HEF
PEF
EVF
HCF
SPC
MLD
FLAG0
FLAG1
PM0
MR0
PORT RH
Parallel
to
Serial
PSR0
LPX0
LPX1 LPX2
LPX3
LPX4
LPX5 LPY0
LPY1
SPC_busy
SPC_play
LPXY
Speech
MDPCM
Shared_ROM Data
core
RH0~3
WRP
RDP
SPDATA
VDDA
ROSC
VSSA
VSSP
Timer 0
(8 Bit)
Timer 1
(8 Bit)
Interrupt ,Hold
& Stop Control
MLD_busy
Voice ROM
(1M /2M/3M/4M
bits)
MLD_play
Watch Dog Timer
(18/14 Bit)
Divider
(14/10 Bit)
Timing Generator
XIN
Dual Tone
Melody
(1K notes)
PWM/
DAC
Mix
Block
PWM1/DAC
PWM2
VDDP
VDD
VSS
TEST
RES
XOUT X32I X32O
-3-
Publication Release Date:Sep 2000
Revision A3
PAD DESCRIPTION
SYMBOL
XIN/RXIN
I/O
I
XOUT
O
X32I/RSUB1
I
X32O/RSUB2
O
RA0 ~ RA3/TONE
I/O
RB0 ~ RB3
I/O
RC0 ~ RC3
I
RD0 ~ RD3
I
RE0~RE3
O
RF0~RF3
O
RG0 ~ RG3
I
RH0 ~ RH3
O
RES
I
TEST
ROSC
PWM1/DAC
I
I
O
PWM2
WRP
O
O
FUNCTION
Input pad for main clock oscillator. It can be connected to crystal when crystal
mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate
main system clock while RC mode is selected (SCR0.2=0 and default). Oscillator
can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External
capacitor connects to start oscillation while crystal mode
Output pad for oscillator which is connected to another crystal pad when in crystal
mode. External capacitor connects to start oscillation when in crystal mode.
32.768 KHz crystal input pad or external resistor node 1 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
32.768 KHz crystal output pad or external resistor node 2 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
General Input/Output port specified by PM1 register. If output mode is selected,
PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special
register is set to logic 1. An interrupt source.
General Input/Output port specified by PM2 register. If output mode is selected,
PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode.
4-bit schmitter input with internal pull high option specified by PM3 register bit 2.
Each pad has an independent interrupt capability specified by PEFL special
register. Interrupt and STOP mode wake up source. RC0 is also the external
event counter source of Timer1.
4-bit schmitter input port with internal pull high option specified by PM3 register
bit 3. Each pad has an independent interrupt capability specified by PEFH
special register. Interrupt and STOP mode wake up source.
Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving
capability option.
Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving
capability option.
Input port with internal pull high option specified by PM6 register bit 0.
(W536090P/W536120P only)
Output port only. PM6 register bit 1 can be used to specify CMOS/NMOS driving
capability option. (W536090P/W536120P only)
System reset pad, active low with internal pull-high resistor.
Test pad. Active high with internal pull low resistor.
Connect resistor to VDD pad to generate speech or melody playing clock source.
While speech or melody is active, PWM1/DAC is speaker direct driving output or
DAC output controlled by voice output file.
While speech or melody is active, PWM2 is another speaker direct driving output.
External serial memory address write clock for voice extension.
-4-
Publication Release Date:Sep 2000
Revision A3
RDP
O
External serial memory address read clock for voice extension.
SPDATA
I/O
External serial memory data in/out for voice extension.
VSS
I
Chip ground.
VSSP
I
Chip ground for PWM or DAC playing output.
VSSA (3)
I
Chip ground. (W536090P/120P only)
VDD
I
Power source.
VDDP
I
Power source for PWM or DAC playing output.
VDDA (3)
I
Power source. (W536090P/120P only)
(3) VDDA, VSSA for W536090P/120P only. To sure chip operation properly, please bond all
VDD, VDDA, VDDP, VSS, VSSA and VSSP pads, and connect VSS, VSSP form chip external
PCB circuit.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage to Ground Potential
Applied Input/Output Voltage
Power Dissipation
Ambient Operating Temperature
Storage Temperature
RATING
-0.3 to +7.0
-0.3 to +7.0
120
0 to +70
-55 to +150
UNIT
V
V
mW
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device.
DC CHARACTERISTICS
(VDD−VSS = 3.0V, No load, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C
unless otherwise specified)
PARAMETER
Op. Voltage
Op. Current
(No Load, no Voice, no
Melody)
Hold Mode Current
Stop Mode Current
RDP/WRP Output High
Current
RDP/WRP Output low
Current
Input Low Voltage
Input High Voltage
Port RA, RB, RE,RF and RH
Output Low Voltage
Port RA, RB, RE,RF and RH
Output High Voltage
SYM.
VDD
IOP1
CONDITIONS
IOP2
IOP3
IoH1
Vout =2.7V
MAX
5.5
500
500
30
6
1
-0.8
IoL1
Vout =0.4V
0.8
mA
VIL
VIH
VABL
IOL = 2.0 mA
VSS
0.7
-
-
0.3
1
0.4
VDD
VDD
V
VABH
IOH = -2.0 mA
2.4
-
-
V
Dual clock with crystal
Dual clock with RC type
Sub-clock only
Sub-clock active only
-5-
MIN
2.4
-
TYP
400
400
15
4
UNIT
V
uA
uA
uA
mA
Publication Release Date:Sep 2000
Revision A3
Pull-up Resistor
RES Pull-up Resistor
PWM1/2 Source Current (4)
RCD
RRES
ISPH
(RLOAD =8Ω between PWM1
And PWM2 )
PWM1/2 Sink Current (4)
ISPL
(RLOAD =8Ω between PWM1
And PWM2 )
Port RC, RD, RG
Volume Option =00
Volume Option =01
200
50
Volume Option =10
Volume Option =11
Volume Option =00
Volume Option =01
Volume Option =10
Volume Option =11
DAC output Current
IDAC
VDD=3v, RL=100ohm
(4) PWM current deviation will be ±20%.
300
100
-20
-70
400
200
-110
-135
20
70
-4
110
135
-5
KΩ
KΩ
mA
mA
-6
mA
AC CHARATERISTICS
(VDD−VSS = 3.0V, No load, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C
unless otherwise specified)
PARAMETER
SYM.
CONDITIONS
MIN. TYP.
MAX. UNIT
Sub-clock Frequency
FSUB
Crystal type and X32IN
32768
Hz
and X32O with 17pF
external cap.
Main-clock Frequency
FM
RC type/Crystal type
400K 4M
Hz
Chip Operation Frequency
FOSC
32768
Hz
SCR0.0=1,FSYS= FSUB
4M
SCR0.0=0;FSYS= FMAIN 400K Instruction Cycle Time
TCYC
One machine cycle
4/FOSC
S
Reset Active Width
TRAW
FOSC = 32.768 KHz
1
µS
Interrupt Active Width
TIAW
FOSC = 32.768 KHz
1
µS
Main clock RC frequency
FRXIN
1M
Hz
RXIN =680KΩ
2M
RXIN =330K Ω
3M
RXIN =200KΩ
4M
RXIN =130KΩ
Sub-Clock Ring Oscillator
FRSUB
32
KHz
RSUB=680KΩ
Sub-Clock Oscillation
0.8
1
S
FSTOP
RSUB=680KΩ
Stable Time @ Cold Start
10
%
Frequency Deviation of
f(3V) − f(2.4V)
∆f
f
main-clock FRXIN ≤ 2 MHz
f(3V)
15
%
Frequency Deviation of
f(3V) − f(2.4V)
∆f
main-clock FRXIN = 3 MHz
f
f(3V)
20
%
Frequency Deviation of
f(3V) − f(2.4V)
∆f
main-clock FRXIN = 4 MHz
f
f(3V)
ROSC Frequency
FROSC
3
MHz
ROSC=680KΩ
7.5
%
Frequency Deviation of
f(3V) − f(2.4V)
∆f
FROSC = 3MHz
f
f(3V)
(5) The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor
-6-
Publication Release Date:Sep 2000
Revision A3
Iop Vs. Main clock RC mode
800
600
3V
4.5V
400
Iop (uA) 200
0
1
2
3
4
Freq (MhZ)
Oscillation Freq Vs. Sub-Clock
44
40
36
3V
4.5V
Fsub (KhZ) 32
28
24
20
560
620
680
750
820
1K
Rsub (Kohm)
-7-
Publication Release Date:Sep 2000
Revision A3
Main Freq Vs. Rxin
6
5
2.4V
3v
4.5V
5.5V
4
Fmain
3
(MhZ)
2
1
0
130 150 160 200 330 680 2K
3K
RXIN (Kohm)
Voice Operating Freq. Vs. ROSC
Freq (MhZ)
4.5
4
3.5
3
2.5
2
3V
4.5V
470
560
680
910
ROSC (Kohm)
-8-
Publication Release Date:Sep 2000
Revision A3
APPLICATION CIRCUIT--1: Sub clock with RC mode
VDDP
RA0~3
RB0~3
RC0~3
RD0~3
RE0~3
RF0~3
470
VDD
R5
( *1)
(*2)
RES
PWM1/DAC
C3
Battery
VDDP
R4
C2
VDDA
W536XXXP
PWM2
VDD
C1
WRP
R1
ROSC
RDP
R3
XIN
W55M08
SPDATA
X32IN
RG0~3
R2
RH0~3
X32O
C2
4.7uF
C3
0.1uF
VSSA
C1
0.1uF
VSS
VSSP
Component
Value
R1
680K
R2
680K
R3
680Kohm/1Mhz
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
R4
100
Note:
(1) Option R5 equals to 100Ω if high noise immunity is needed.
(2) For DAC option application
(3) To sure chip operation properly, please bond all VDDP, VDD, VDDA, VSSP, VSSA and VSS
(4) VDDA, VSSA are only for W536090P/120P.
-9-
Publication Release Date:Sep 2000
Revision A3
APPLICATION CIRCUIT--2: Sub clock with Xtal mode
VDDP
RA0~3
RB0~3
RC0~3
RD0~3
RE0~3
RF0~3
470
VDD
R5
( * 1)
(*2)
RES
PWM1/DAC
C3
Battery
PWM2
VDDP
VDDA
C2
R4
C1
VDD
W536XXXP
WRP
R1 ROSC
RDP
R3 XIN
C4
SPDATA
X32IN
RG0~3
32.768kHz
C5
RH0~3
X32O
C2
4.7uF
C3
0.1uF
VSSA
C1
0.1uF
VSS
VSSP
Component
Value
W55M08
C4~C5
17pF~20pF
R1
680K
R3
680Kohm/1Mhz
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
R4
100
Note:
(1) Option R5 equals to 100Ω if high noise immunity is needed.
(2) For DAC option application.
(3) To sure chip operation properly, please bond all VDDP, VDD, VDDA, VSSP , VSSA and VSS .
(4) VDDA and VSSA are only for W536090P/120P.
- 10 -
Publication Release Date:Sep 2000
Revision A3