Ver1.0 Ai4100 1 A1 PROs A1 PROs CCD CDS/PGA/10b-20M-ADC FEATURES ㆍOperating voltage : 2.7V ~ 3.6V ㆍLow power consumption : 70mW (Typ.) ㆍPower down mode : less than 30μW ㆍAccepts a direct signal input to ADC or PGA at 1.0 VPP (Typ.) ㆍCCD signal input level : 1.1 VP-P (Max.) ㆍ10-bit ADC (up to 20MHz) - DNL : ±0.6 LSB (Typ.) ㆍBlack level neutralizer, target setting : 16~127 LSB ㆍBuilt-in serial interface ㆍIndependent ADC input conversion clock and data output clock ㆍIndependent CDS and PGA gain control - CDS : -1.94/ 0/ 6/ 12dB - PGA : 0~24dB ㆍWide gain range : -1.94 ~ 36dB ㆍHigh speed sample and hold circuit : pulse width 11ns (Min.) ㆍ48-pin LQFP package GENERAL DESCRIPTION voltage generator, black level detection circuit, 20MHz 10-bit A/D converter (ADC), timing generator for internally required pulses and serial interface for internal function control and PGA gain control. The Ai4100 is a CMOS single-chip signal processing devices for CCD area sensors. It consists of a clamp circuit, Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA), reference voltage generator, black level detection circuit, BLOCK DIAGRAM OBP ADCLK BLK ADCLP/CCDCLP CSN SCK SDATA MONOUT Serial Register Timing Generator BandGap Circuit CLPCAP CCDCLP PGA Rough CDS REFIN PGA Fine 10-Bit ADC CCDIN CCD VRP VCOM VRN DC Clamp ADCLP -1.94/0/6/12dB 0~6dB 0/6/12/18dB (0.047dB/Step) ADIN OBCAP DAC OBP VDD VSS Compare Black Level Register RESET STBY SHP SHD 1 OUTCK DO0~DO9 Ai4100 PIN ASSIGNMENT DO0 DO1 DO2 DO4 DO3 DVSS2 DVDD2 DO5 DO6 DO7 DO8 DO9 NC OUTCK AVDD4 RESETN NC DVDD1 REFB DVSS1 REFT STBY AVDD3 CSN Ai4100 AVDD2 SDATA AVSS3 SCK AVSS2 OBP CML CCDCLP CCDIN BLK REFIN ADCLP SHD SHP ADCLK NC AVSS1 AVDD1 AISET NC MONOUT OBCAP ADIN CLPCAP 2 Ai4100 PIN DESCRIPTION Pin No. Pin Name I/O Description 1, 3, 17, 21 NC - No Connection 2, 6~7, 19 AVDD - Analog Power (+3.3V) 4 REFB O ADC Internal Bottom Reference Voltage 5 REFT O ADC Internal Top Reference Voltage 8~9, 20 AVSS - Analog Ground 10 CML O ADC Internal Common Reference Voltage 11 CCDIN I CDS Input Data Input 12 REFIN I CDS Circuit Reference Input 13 CLPCAP O Clamp Level Output 14 ADIN I ADIN Signal Input 15 OBCAP O Black Level Integration Voltage 16 MONOUT O Monitor Output of CDS or PGA 18 AISET I External Bias Current Setting 22 ADCLK I ADC Sampling Clock Input 23 SHP I Reference Sampling Pulse Input 24 SHD I Data Sampling Pulse Input 25 ADCLP I Pulse Input for ADIN Clamp and Black Calibration Control 26 BLK I Blanking Pulse Input 27 CCDCLP I Clamp Control Input 28 OBP I Black Level Period Pulse Input 29 SCK I Serial Port Clock Input 30 SDATA I Serial Port Data Input 31 CSN I Serial Port Chip Selection (Active Low) 32 STBY I Power Down Control (Power Down at Low) 33, 42 DVSS - Digital GND 34, 43 DVDD - Digital Power (+3.3V) 35 RESETN I Reset Signal Input (Active Low) 36 OUTCK I Clock Input for ADC Output Timing 37~41, 44~48 D0~D9 O ADC Digital Output ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Supply Voltage VCC GND-0.3 to GND+6.0 Input Voltage VIN VSS-0.3 to VDD+0.3 Storage Temperature TSTG -55 to +150 Operating Temperature TOP -20 to +70 Unit V ℃ Note : These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Rating” may cause substantial damage to the devices. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability 3 Ai4100 DC CHARACTERISTICS (Ta = 25℃) Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions VDD VIH High Level Input Voltage 3V - 0.7VDD - VDD V VIL Low Level Input Voltage 3V - 0 - 0.3VDD V IIH High Level Input Current 3V VIL=0V - - 200 μA IIL Low Level Input Current 3V VIH=3.0V - - 1 μA IMD Operation Current at Monitor Disable 3V fS=20MHz - 23 - mA IMA Supply Current at Monitor Active 3V fS=20MHz - 26 - mA ISS Power Down Current 3V - - - 10 μA 3V CCDIN input, fIN=1MHz - 1.1 - VP-P 3V ADIN input, fIN=1MHz - 1.0 - VP-P VCCDIN Analog Input Range VADIN VCLPCAP Clamp Voltage 3V - 1.5 1.7 1.9 V tBLKCAL Black Calibration Time 3V - - - 200 Pixel VBLKCAL Maximum Calibration Offset Voltage 3V - - ±200 - mV G (0) CDS Gain (Set 0 dB) 3V Absolute gain -2 -1 0 dB G (1) CDS Gain (Set 6.02 dB) 3V 5.52 6.02 6.52 dB G (2) CDS Gain (Set 12.04 dB) 3V 11.54 12.04 12.04 dB G (3) CDS Gain (Set -1.94 dB) 3V -2.44 -1.94 -1.44 dB GMIN PGA Gain (Minimum Gain) 3V -1.2 -0.2 0.8 dB GMAX PGA Gain (Maximum Gain) 3V 22.906 23.906 24.906 dB 0 0.047 0.094 dB Relative gain Absolute gain Relative gain GSTEP PGA Gain (Gain Step) 3V ERPA Total (CDS+PGA) Gain Monotony 3V - - - ±4 LSB RES Resolution 3V - - - 10 Bits DNL Differential Nonlinearity 3V fS=20MHz - ±0.6 ±1.0 LSB SN S/N 3V - - 58 - dB SND S/(N+D) 3V - - 56 - dB VCOM ADC Common Voltage 3V - 1.25 1.4 1.55 V VRP VRP Voltage (Positive) 3V - 1.55 1.65 1.75 V VRN VRN Voltage (Negative) 3V - 1.05 1.15 1.25 V ADC Output Black Level Calibration Code 16 - 127 LSB CCAL 3V 1 - 127 LSB Calibration Code Resolution 3V - 1 - LSB STCAL - Note : Black calibration period is specified when CCAL is from 16 to 127LSB. Although black level codes of 1 to 15 could be set, tBLKCAL is not guaranteed for these codes. 4 Ai4100 AC CHARACTERISTICS (VSS = 0V, Ta = 25℃) Test Conditions Symbol Parameter VDD Min. Typ. Max. Unit Conditions fS Conversion Frequency 3.0V - 0.5 - 20 MHz tCYC Clock Cycle Time 3.0V - 50 - - ns tR Clock Rising Time 3.0V - - - 2 ns tF Clock Falling Time 3.0V - - - 2 ns tL Clock Low Period 3.0V - 23 - - ns tH Clock High Period 3.0V - 23 - - ns tWR SHP Pulse Width 3.0V - 11 - - ns tWD SHD Pulse Width 3.0V - 11 - - ns tDR SHP Pulse Width 3.0V - - - 4 ns tDD SHD Sampling Aperture 3.0V - - - 4 ns tPSUP Data Pulse Setup 3.0V - 2 - - ns tHOLD Data Pulse Hold 3.0V - 5 - - ns tSP Sampling Pulse Non-overlay 3.0V - 1 - - ns tSUPE Enable Pulse Setup 3.0V - 10 - - ns tHOLDE Enable Pulse Hold 3.0V - 10 - - ns tSUPOC OUTCK Setup 3.0V - 0 - - ns tHOLDOC OUTCK Hold 3.0V - 10 - - ns tDLD 3-state Disable Delay 3.0V Active Æ High-Z - 20 - ns tDLE 3-state Disable Delay 3.0V High–Z Æ Active - 20 - ns tDL ADC Output Data Delay 3.0V - - 6 - ns 5 Ai4100 FUNCTIONAL DESCRIPTION CDS ( Co rrelated Double Sampling) Circuit ㆍClamp target (Mode 2 register D5 and D4), input signal(REFIN and CCDIN) to be clamped are selected. Connect the CCDIN pin to the CCD sensor through a capacitor. Connect also the REFIN pin to VSS through a capacitor. The CDS circuit holds the pre-charge voltage of the CCD at SHP pulse and do sampling of the CCD pixel data at SHD pulse, Correlated noise is removed by subtracting the pre-charge voltage from the pixel data level. CDS could choose a gain setting from 0, 6.02, 12 or -1.94dB (Mode 3, register D4 and D5 bits). A CDS gain is controlled by PGA gain. It is recommended to increase the CDS gain then increase the PGA gain to reduce the noise level. CDS ( Co rrelated Double Sampling) Circuit The purpose of a black level cancel circuit is to control the DC level of the PGA input. The ADC output code at an optical black period may correspond to the black level code set up by the register. A black level code of (1 to)16 to 127 LSB is available (the default is 64 LSB) While the OBP pin is active a black level cancel loop is established. In the loop, a comparison is made between the ADC output code and the black level code, the result controls the voltage of the OBCAP capacitor. Hence, the OBCAP voltage settles gradually and the signal level of the optical black period corresponds to the established value. Clamp Circuits ㆍ DC clamp The DC level of the CCDIN/REFIN input is fixed by an internal DC clamp circuit. The DC level of the C-coupled CCD signal at the CDS input is set to CLPCAP by the internal DC clamp circuit. The clamp switches are usually turned on at the black level calibration period. The CLPCAP pin connects to VSS through a 0.1μF capacitor. The following conditions will reset the OBCAP capacitor: ㆍ ADIN signal clamp ㆍ Set the black level reset register to “1” (Mode 1 register D1=1). ㆍSet the RESETN pin to low ㆍPower down by STBY pin or register control Clamp operation can also be used for the ADIN path. The clamp voltage is different from the CCDIN/REFIN signal and it could be turned off by register setting. At “ADIN signal to ADC” mode, the ADCLP signal controls the “clamp circuit”. Black level calibration circuit is also controlled by ADCLP at “ADIN signal to PGA” mode The DC clamping (CCDCLP) is allowed while the DBP pin is low. The black level cancellation is available at “ADIN signal to PGA” mode. The black level cancellation is available at the ADCLP period in this mode. The clamping function and black level canceling function are done simultaneously. ㆍ Clamp control ㆍClamp current (Mode 2 register D7). Charge current can select normal or fast clamp. CCD OB Effective Pixel Blanking ADCLK BLK OBP CCDCLP OUTCK DO0~DO9 Data Output 6 Black Code Ai4100 Effective Pixel Signal Blanking Optical Black Period Effective Pixel Signal Blanking CCD ADCLK Resulting Black Calibration Level (Hold) OBP Previous Black Level OBCAP Black Level Calibration Timing High-speed Black Level Cancellation (D3~D0-5’b0). By setting the register D2~D0, the gain becomes high by 1 to 7 times that of the OBP pulse period after any access to the serial interface. After that period, the gain returns to low. When setting D3 to 1’b1, the gain is always high. The CSN signal becomes the starting point of the OBP pulse count. The Ai4100 has a high speed black level cancellation function, which by means of a register setting enhances the setting speed within a fixed period from access to the serial interface, It increases the gain of the setting DAC within a fixed a fixed period and in turn increases the charge/discharge current to the OBCAP capacitor. The following figure shows the black loop setting gain boost timing chart when the boost controls is on (D3=“0”) and the boost period is set to 3. The Mode 3 register D3 to D0 data controls the black level boost function. The default setting is always low gain CSN tSUCS tHCS OBP Counter 0 2 1 High gain Black loop gain 3 3 0 Low gain 2 1 0 1 2 High gain Black Loop Setting Gain Boost Timing Symbol Parameter Condition Min. Typ. Max. Unit tSUCS CSN Setup Time - 10 - - ns tHCS CSN Hold Time - 10 - - ns Gain Control Circuit ㆍThe signal from the CCDIN input through a CDS and PGA ㆍThe signal from the ADIN input through an PGA at the ADIN mode. ㆍThe signal from the ADIN input at the ADIN mode. The total gain for a CCD input signal covers from -1.94dB to 36dB. The CDS range is 0/6/12/-1.94 dB. The PGA rough is 0/6/12/18 dB and ADC fine is 0 to 6dB, 0.047dB/step. The CDS gain is controlled by a 2-bit register and the PGA gain is controlled by a 9-bit register A/D Conversion Range The analog input range of the ADC is determined by the internal reference voltage. The full scale of the ADC is 1.0 VPP A/D Converter Circuit The Ai4100 includes one 20MHz 10-bits AD converter. The ADC converters the following signals. 7 Ai4100 A/D Converter Output Code (Mode 1 Register D5=1) the ADCLK input after a 5.5 clock of pipeline delay. The format of an ADC digital output is a straight binary. When in the input zero reference voltage, the output code will be all zero and when the input is a full scale voltage, the output code will be all one High-Z Control of ADC Digital Output ADC digital outputs become High-Z under the following conditions Clock, Pipeline Delay, Digital Data Output Timing ㆍ Set the ADC output bit to one. (Mode 1 register D2=1) ㆍ Set the STBY pin to low ㆍ Set the power control bit to one (Mode 1 register D0=1) The ADCLK input is used for an A/D conversion. The ADC input signal is sampled at the falling edge of the ADCLK input and 10 bits parallel data is output at the rising edge of Digital Output Code A/D Input LSB MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Full Scale 1 1 1 1 1 1 1 1 1 1 : : : : : : : : : : : : 1 0 0 0 0 0 0 0 0 0 : 0 1 1 1 1 1 1 1 1 1 : : : : : : : : : : : Zero Scale 0 0 0 0 0 0 0 0 0 0 ADC Data Output (Coding : Straight Binary) Miscellaneous Functions (ADC Direct Input, ADIN Mode) Polarity Inversion The following input polarities can be inverted by register setting: The direct input path to the ADC or the PGA is achieved by means of a register setting. The selectable paths are as follows: ㆍADCLK (A/D converter sampling clock, Mode 1 register D6) ㆍSHP and SHD (CDS sampling clock, Mode 2 register D3 and D2) ㆍBLK, OBP, CCDCLP and ADCLP (Mode 2 register D3 and D2) ㆍFunction disable (default, Mode 1 register D5=0, D4=0) ㆍADIN input to the PGA (Mode 1 register D5=0, D4=1) ㆍADIN input to the PGA (Mode 1 register D5=1, D4=Don’t Care) The BLK, SHD and SHP inputs are ignored at the ADIN mode. Data Output Clock Power Down Mode The ADCK input or the OUTCK input is selectable as an ADC data output clock. The power mode can be set either by register setting or by the STBY pin. Serial Interface Circuit The internal registers of the Ai4110 are controlled by a 3wire serial interface. The data is a 16-bit length serial data that consists of a 2-bit operation code, 4 bits address and 10bits data. Each bit is fetched at the rising edge of the CSN input. Keep CSN to high when not access Ai4110. it is prohibited to write to a non-defined address. When a data length is below 16 bits, the data is not executed. Monitor Output When setting Mode 2 (D1 and D0), the signal from MONOUT is selectable. The alternatives are OFF, CDS output, PGA output or REFIN/CCDIN output. The MONOUT pin gain is fixed to 0dB regardless of the gain control register setting when the CDS output is selected. The MONOUT level becomes V COM at zero reference level. The signals are output in reverse for the CCD input Registers The Ai4100 has 10 bitsX7 registers that control the operations. All registers are write only, the serial registers are written by the serial interface. 8 Ai4100 Address Register Name R/W Function Description A3 A2 A1 A0 W 0 0 0 0 Mode 1 DOUT timing control/OUTCK polarity/ADCLK polarity/ADIN connection/ADC output/Black level reset/Power down W 0 0 0 1 Mode 2 Clamp current/ADIN clamp/Clamp target/S/H, enable logic/Monitor selection W 0 0 1 0 Mode 3 / CDS gain CDS gain control/Black loop gain boost/Boost period W 0 0 1 1 PGA gain PGA gain W 0 1 0 0 Black level ADC code at black level (1 LSB step) Register Map Register Bit Assignment D9 D8 D7 D6 D5 D4 D1 D2 D3 D0 Mode 1 Default X O O O O O O O O O Functions √ DOUT timing control √ OUTCK polarity √ ADCLK polarity ADIN connection ----√ Reserved √ ADC output √ Black level reset √ Power down Mode 2 Default X X O O O O O O O O Functions √ Clamp current √ ADIN clamp Clamp target ----- S/H, enable logic ----- Monitor selection ----- Mode 3 Default X X X X O O O O O O Functions CDS gain control ----√ Black loop gain boost --------------- Boost period PGA Gain Default X O O O O O O O O O O O Functions ---------------------------------------------------------------- PGA gain Black Level Default X X X 1 O O O O Functions Black level -------------------------------------------------- 9 Ai4100 Register Operations Control D9 D8 D7 D6 D5 D4 D3 D2 D1 Operations D0 Mode 1 DOUT timing control OUTCK polarity 0 DOUT synchronizes to ADCLK 1 DOUT synchronizes to OUTCK DOUT changes at OUTCK rising edge 0 1 ADCLK polarity DOUT changes at OUTCK falling edge 0 Normal operation as timing chart 1 ADCLK clock inversion ADIN connection 0 0 ADIN function OFF 0 1 ADIN signal to PGA 1 X Reserved ADIN signal to ADC 0 Reserved 1 Reserved ADC output 0 Normal operation, ADC data output 1 ADC output high-Z, or logic of STBY Black level reset 0 Normal operation 1 Black level reset, or logic of RESET Power down 0 Normal operation 1 Power down, or logic of STBY Mode 2 Clamp current ADIN clamp Clamp target 0 Normal clamp ±50μA 1 Fast clamp ±100μA 0 Clamp operation active for ADIN 1 No clamp for ADIN 0 0 Normal mode, clamp both REFIN and CCDIN 0 1 Clamp REFIN only 1 0 Clamp CCDIN only 1 1 Clamp off S/H, enable logic 0 0 Normal operation as timing chart 0 1 S/H control polarity inversion 1 0 Enable control polarity inversion 1 1 Monitor selection Both of S/H and enable inversion 0 0 Monitor off 0 1 CDS signal to monitor 1 0 PGA output monitor 1 1 Output REFIN and CCDIN Mode 3 CDS gain control Black loop gain boost 0 0 CDS gain=0 dB 0 1 CDS gain=6.02 dB 1 0 CDS gain=12.04 dB 1 1 CDS gain=-1.94 dB 0 Boost control on 1 Always high gain 10 Ai4100 Control Operations D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 Always low gain 0 0 0 1 High gain for 1 OBP pulse 0 0 1 0 High gain for 2 OBP pulse 0 0 1 1 High gain for 3 OBP pulse 0 1 0 0 High gain for 4 OBP pulse 0 1 0 1 High gain for 5 OBP pulse 0 1 1 0 High gain for 6 OBP pulse 0 1 1 1 High gain for 7 OBP pulse Boost period Control HEX PGA Gain (dB) D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0.046 0 0 0 0 0 0 0 0 1 0 2 2 0.093 0 0 0 0 0 0 0 0 1 1 3 3 0.142 0 0 0 0 0 0 0 1 0 0 4 4 0.187 ↓ 3E ↓ 2.915 ↓ 0 0 0 0 1 1 1 1 1 0 ↓ 62 0 0 0 0 1 1 1 1 1 1 63 3F 2.962 0 0 0 1 0 0 0 0 0 0 64 40 3.011 0 0 0 1 0 0 0 0 0 1 65 41 3.056 ↓ 7F ↓ 5.972 ↓ 0 0 0 1 1 1 1 1 1 1 ↓ 127 0 0 1 0 0 0 0 0 0 0 128 80 6.021 0 0 1 0 0 0 0 0 0 1 129 81 6.058 ↓ C0 ↓ 9.031 ↓ PGA gain Decimal D9 0 0 0 0 0 ↓ 192 1 1 1 1 1 1 ↓ 255 ↓ FF ↓ 11.994 0 0 0 0 0 0 0 256 100 12.041 0 0 0 0 0 0 1 257 101 12.087 0 1 0 0 0 0 0 0 ↓ 320 ↓ 140 ↓ 15.05 0 1 1 1 1 1 1 1 ↓ 383 ↓ 17F ↓ 18.14 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 ↓ ↓ ↓ 0 1 1 0 0 0 0 0 0 0 384 180 18.061 0 1 1 0 0 0 0 0 0 1 385 181 18.108 ↓ ↓ ↓ ↓ 0 1 1 1 0 0 0 0 0 0 448 1C0 21.071 0 1 1 1 ↓ ↓ ↓ 1 1 1 1 1 0 510 1FE 0 1 1 1 23.987 1 1 1 1 1 1 511 1FF 24.032 ↓ 11 Ai4100 Operation, ADC Code D9 D8 D7 Black Code D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 Forbidden Forbidden 0 0 0 0 0 0 1 1 1 ↓ ↓ ↓ Decimal 0 0 0 1 1 1 1 15 F 0 0 1 0 0 0 0 16 10 0 0 1 0 0 0 1 17 11 0 0 1 0 0 1 0 18 12 0 0 1 0 0 1 1 19 13 ↓ ↓ 32 20 ↓ ↓ 64 40 ↓ ↓ ↓ Black level 0 1 0 0 0 0 0 ↓ 1 0 0 0 0 0 0 ↓ 1 1 1 1 1 0 0 124 7C 1 1 1 1 1 0 1 125 7D 1 1 1 1 1 1 0 126 7E 1 1 1 1 1 1 1 127 7F TIMING DIAGRAMS tDD tDR CCD Reference Sampling Data Sampling tWR SHP tWD tPSUP tSP SHD tHOLD tCYC ADCLK BLK OBP CCDCLP ADCLP HEX tHOLDE tH tHOLDC tSUPOC OUTCK tOL DO0~DO9 12 tL tSUPE Ai4100 AD Conversion Timing (at ADIN (ADC) Input Mode 1 Register D5=1) Falling Edge 0.7AVDD ADCLK 0.3AVDD N+6 N+5 N+1 N+4 N ADCLK Input 0.7AVDD OUTCK 0.3AVDD tDL N-6 Digital Output N-5 N-2 N-1 N ADC Direct Input Chart ADCK ADCK Rising Edge tHOLDC ADCK Input N tSUPOC N+1 OUTCK Sampling Point ADCLK Inversion Chart OUTCK Timing Chart These figures are shown when the Mode 1 D8 bit is set to “1”, and an external clock is input to the OUTCK pin. When setting D8 bit to “0”, the ADCLK is used as OUTCK. Note : At default condition in ADIN mode, data are sampled at the falling edge of the ADCK clock, and are output at the rising edge of the OUTCK clock. Set the ADCLK polarity register to “1” when the data are sampled and are output at the falling edge of the ADCK clock. The diagram on the upper portion of this page shows the default timing and the lower left figure shows the inverted timing Delay from data sampling to data output ADCLK normal : At Mode 1 register D6=0; 5.5 clk delay ADCLK inversion : At Mode 1 register D6=1; 6.0 clk delay In ADIN input mode, the above mentioned register setting is available. At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks. ADCLK Clock Waveform tH 0.7VDD 0.3VDD tR tF tCYC 13 tL Ai4100 Control Interface Timing (VSS = 0V, Ta = 25℃) Test Conditions Symbol Parameter VDD Conditions Min. Typ. Max. Unit SCYC SCK Clock Frequency 3.0V - - - 10 MHz SLO SCK Clock Low Level Width 3.0V - 40 - - ns SHI SCK Clock High Level Width 3.0V - 40 - - ns SSU Data Setup Time Period 3.0V - 20 - - ns SH Data Hold Time Period 3.0V - 20 - - ns SR SCK, CSN Rising Time Period 3.0V 30% Æ 70% - - 6 ns SF SCK, CSN Falling Time Period 3.0V 70% Æ 30% - - 6 ns SNUM Number of Serial Data 3.0V - - 16 - pcs 50% VDD CSN SSU SH SCYC SLO SHI 50% VDD SCK SSU SDATA O0 SH A0… O1 50% VDD D9 D8 SNUM Serial I/F Timing Chart Data Output Sequence CCD 0 1 2 3 4 5 6 7 8 SHP SHD ADCLK OUTCK BLK DO0~DO9 Black Level Code 0 1 Pixel Data Readout Sequence (1) : Start of Conversion 14 2 3 Ai4100 CCD (N-1) N SHP SHD ADCLK OUTCK BLK DO0~DO9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N Pixel Data Readout Sequence (2) : End of Conversion Clock Timing Variations by Register Setting Clock timing variations when it is inverted by register settings. • No inversion Mode 1 register D6=0, Mode 2 register D2=0; Default CCD SHP SHD ADCLK OUTCK DO0~DO9 Pulse Control (Default : No Inversion) 15 Black Level Code Ai4100 • ADCK inversion Mode 1 register D6=1, Mode 2 register D2=0 CCD SHP SHD ADCLK OUTCK DO0~DO9 Pulse Control (ADCLK Inversion) • SHP & SHD inversion Mode 1 register D6=0, Mode 2 register D2=1 CCD SHP SHD ADCLK OUTCK DO0~DO9 Pulse Control (SHR & SHD Inversion) • ADCLK, SHP & SHD inversion Mode 1 register D6=1, Mode 2 register D2=1 CCD SHP SHD ADCLK OUTCK DO0~DO9 Pulse Control (ADCLK, SHR & SHD Inversion) 16 Ai4100 APPLICATION CIRCUITS 0.1uF Power In RESETN NC REFB DVDD1 DVSS1 REFT STBY 0.1uF 0.1uF CSN Ai4100 AVDD3 10uF AVDD2 SDATA SCK AVSS3 OBP AVSS2 CCDCLP CML ADCLP SHD SHP ADCLK NC AVSS1 AVDD1 * CCD 0.1uF AISET NC OBCAP ADIN REFIN 0.1uF MONOUT CCDIN BLK CLPCAP 0.1uF DO0 OUTCK AVDD4 0.1uF 0.1uF DO1 DO2 DO3 DO4 DVSS2 DVDD2 DO5 DO6 DO7 DO8 NC DO9 Power In 0.1uF ** 0.1uF 0.1uF 0.1uF Power In Note : “*” Pin 18 can also connect to ground through a 4.7K resistor. “**” The capacitor connecting to OBCAP pin may need adjustment depending on user application from 0.1uF to 1uF typically. 17 Power In 0.1uF Ai4100 PKG DIMENSION 48-pin LQFP (7X7) C H D G 25 36 I 37 24 F A B E 48 13 α K J 12 1 Dimensions in mm Symbol Min. Nom. Max. A 8.90 -- 9.10 B 6.90 -- 7.10 C 8.90 -- 9.10 D 6.90 -- 7.10 E -- 0.50 -- F -- 0.20 -- G 1.35 -- 1.45 H -- -- 1.60 I -- 0.10 -- J 0.45 -- 0.75 K 0.10 -- 0.20 α 0˚ -- 7˚ 18