SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995
D Advanced LinCMOS Silicon-Gate
D
D
D
OUT1
OUT2
GND
DB7
DB6
DB5
DB4
DB3
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
RFB
REF
VDD
WR
CS
DB0
DB1
DB2
FK PACKAGE
(TOP VIEW)
OUT2
OUT1
NC
RFB
REF
D
D
D
J PACKAGE
(TOP VIEW)
Technology
Easily interfaced to Microprocessors
On-Chip Data Latches
Monotonicity Over Entire A/D Conversion
Range
Segmented High-Order Bits Ensure
Low-Glitch Output
Designed to Be interchangeable With
Analog Devices AD7524, PMI PM-7524, and
Micro Power Systems MP7524
Fast Control Signaling for Digital Signal
Processor Applications Including Interface
With SMJ320
KEY PERFORMANCE SPECIFICATIONS
Resolution
8 Bits
Linearity error
1/2 LSB Max
Power dissipation at VDD = 5 V
5 mW Max
Settling time
100 ns Max
Propagation delay
80 ns Max
GND
DB7
NC
DB6
DB5
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
VDD
WR
NC
CS
DB0
DB4
DB3
NC
DB2
DB1
description
4
The AD7524M is an Advanced LinCMOS 8-bit
digital-to-analog converter (DAC) designed for
easy interface to most popular microprocessors.
NC−No internal connection
The AD7524M is an 8-bit multiplying DAC with input latches and with a load cycle similar to the write cycle of
a random access memory. Segmenting the high-order bits minimizes glitches during changes in the
most-significant bits, which produce the highest glitch impulse. The AD7524M provides accuracy to 1/2 LSB
without the need for thin-film resistors or laser trimming, while dissipating less than 5 mW typically.
Featuring operation from a 5-V to 15-V single supply, the AD7524M interfaces easily to most microprocessor
buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the AD7524M an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The AD7524M is characterized for operation from − 55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA
CERAMIC CHIP
CARRIER
(FK)
−55°C to 125°C
AD7524MFK
CERAMIC DIP
(J)
AD7524MJ
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
!"#$
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$%#&+
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•
1
SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995
functional block diagram
R
15
R
R
REF
2R
2R
2R
2R
2R
16
S-1
S-2
S-3
S-8
R
1
2
CS
WR
RFB
OUT1
OUT2
12
3
Data Latches
13
4
DB7
(MSB)
5
DB6
6
11
DB5
DB0
(LSB)
GND
Data Inputs
operating sequence
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
tsu(CS)
CS
th(CS)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
10%
tw(WR)
WR
10%
tsu(D)
DB0 −DB7
2
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•
10%
ÎÎÎ
ÎÎÎ
th(D)
SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 17 V
Voltage between RFB and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD+0.3 V
Reference voltage range, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 µA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
VDD = 5 V
NOM
MAX
MIN
Supply voltage, VDD
4.75
5
5.25
VDD = 15 V
NOM
MAX
MIN
14.5
± 10
Reference voltage, Vref
High-level input voltage, VIH
V
V
13.5
0.8
CS setup time, tsu(CS)
15.5
± 10
2.4
Low-level input volage, VIL
15
UNIT
V
1.5
V
40
40
ns
0
0
ns
Data bus input setup time, tsu(D)
25
25
ns
Data bus input hold time, th(D)
10
10
ns
Pulse duration, WR low, tw(WR)
40
40
ns
CS hold time, th(CS)
Operating free-air temperature, TA
−55
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•
125
−55
125
°C
3
SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range, Vref = 10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
IIH
High-level input current
VI = VDD
IIL
Low-level input current
VI = 0
Ipkg
IDD
MIN
10
10
25°C
1
1
Full-range
−10
−10
25°C
−1
−1
Full-range
± 400
± 200
25°C
± 50
± 50
Full-range
± 400
± 200
± 50
± 50
DB0−DB7 at 0,
WR and CS at 0 V
OUT2
Vref = ±10 V
DB0−DB7 at VDD,
WR and CS at 0
Quiescent
Vref = ±10 V
25°C
DB0−DB7 at VIHmin or VILmax
Standby
2
2
Full-range
500
500
25°C
100
100
DB0−DB7 at 0 V or VDD
kSVS
Supply voltage sensitivity,
∆gain/∆VDD
∆VDD = 10%
Ci
Input capacitance, DB0−DB7,
WR, CS
VI = 0
Co
Output
capacitance
Full-range
0.16
25°C
0.002
DB0−DB7 at 0, WR and CS at 0 V
OUT1
OUT2
0.02
0.001
5
OUT1
OUT2
VDD = 15 V
TYP
MAX
MIN
Full-range
OUT1
Output leakage
current
Supply current
VDD = 5 V
TYP
MAX
TEST CONDITIONS
DB0−DB7 at VDD, WR and CS at 0 V
Reference input impedance
(REF to GND)
5
A
µA
nA
mA
µA
A
%/%
0.02
pF
5
pF
30
30
120
120
120
30
30
5
µA
A
0.04
120
20
UNIT
20
pF
kΩ
operating characteristics over recommended operating free-air temperature range, Vref = 10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Linearity error
Full range
VCC = 5 V
MIN
MAX
VDD = 15 V
MIN
MAX
UNIT
± 0.2
± 0.2
%FSR
± 1.4
± 0.6
±1
± 0.5
%FSR
Gain error
See Note 1
Settling time (to 1/2 LSB)
See Note 2
100
100
ns
Propagation delay from digital input to
90% of final analog output current
See Note 2
80
80
ns
Feedthrough at OUT1 or OUT2
Vref = ± 10 V (100 kHz sinewave),
WR and CS at 0, DB0−DB7 at 0
Temperature coefficient of gain
TA = 25°C to tmin or tmax
25°C
Full range
0.5
0.5
25°C
0.25
0.25
± 0.004
± 0.001
NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range (FSR) = Vref − 1 LSB.
2. OUT1 load = 100 Ω, Cext = 13 pF, WR at 0 V, CS at 0 V, DB0−DB7 at 0 V to VDD or VDD to 0 V.
4
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•
%FSR
%FSR/
°C
SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995
PRINCIPLES OF OPERATION
The AD7524M is an 8-bit multiplying D/A converter consisting of an inverted R-2R ladder, analog switches, and
data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines, thus
maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are
decoded and these decoded bits, through a modification in the R-2R ladder, control three equally weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire reference
current, Iref, is switched to OUT2. The current source 1/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch
capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 1. Analysis of the circuit for all digital inputs high is similar to Figure 1; however, in this case, Iref would
be switched to OUT1.
Interfacing the AD7524M D/A converter to a microprocessor is accomplished via the data bus and the CS and
WR control signals. When CS and WR are both low, the AD7524M analog output responds to the data activity
on the DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects
the analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are
latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless
of the state of the WR signal.
The AD7524M is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 1 and 2, respectively.
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5
SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995
PRINCIPLES OF OPERATION
RFB
R
OUT1
I1kg
30 pF
REF
OUT2
1/256
120 pF
I1kg
Figure 1. AD7524M Equivalent Circuit With All Digital Inputs Low
Vref
VDD
RA = 2 kΩ
(see Note A)
RB
C (see Note B)
RFB
DB0 −DB7
OUT1
−
Output
CS
+
OUT2
WR
GND
Figure 2. Unipolar Operation (2-Quadrant Multiplication)
Vref
VDD
20 kΩ
RA = 2 kΩ
(see Note A)
RB
20 kΩ
DB0 −DB7
10 kΩ
OUT1
−
CS
WR
−
C (see Note B)
RFB
+
OUT2
Output
+
5 kΩ
GND
Figure 3. Bipolar Operation (4-Quadrant Operation)
NOTES: A. RA and RB used only if gain adjustment is required.
B. C phase compensation (10 − 15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.
6
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SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995
PRINCIPLES OF OPERATION
Table 1. Unipolar Binary Code
DIGITAL INPUT
(see NOTE 3)
MSB
ANALOG OUTPUT
LSB
11111111
10000001
10000000
01111111
00000001
00000000
−Vref (255/256)
−Vref (129/256)
−Vref (128/256) = −Vref /2
−Vref (127/256)
−Vref (1/256)
0
NOTES: 3. LSB = 1/256 (Vref).
Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT
(see NOTE 4)
MSB
ANALOG OUTPUT
LSB
11111111
10000001
10000000
01111111
00000001
00000000
Vref (127/128)
Vref (128)
0
−Vref (128)
−Vref (127/128)
−Vref
NOTES: 4. LSB = 1/128 (Vref).
microprocessor interfaces
Data Bus
D0 −D7
Z-80A
DB0 −DB7
WR
WR
AD7524M
CS
IORQ
A0 −A15
OUT1
OUT2
Decode
Logic
Address Bus
Figure 4. AD7524M −Z-80A Interface
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7
SGLS028A − SEPTEMBER 1989 − REVISED MARCH 1995
PRINCIPLES OF OPERATION
Data Bus
D0 −D7
6800
DB0 −DB7
Φ2
WR
AD7524M
OUT1
OUT2
CS
Decode
Logic
VMA
A0 −A15
Address Bus
Figure 5. AD7524M −6800 Interface
A8 −A15
Address Bus
Decode
Logic
8-Bit
Latch
8051
CS
WR
DB0 −DB7
WR
Address / Data Bus
Figure 6. AD7524M−8051 Interface
8
OUT1
OUT2
ALE
AD0 −AD7
AD7524M
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•
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-87700012A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
5962-8770001EA
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
AD7524MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
AD7524MJ
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
AD7524MJB
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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