AAT AAT1164C-Q5-T

Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
Product information presented is current as of publication date. Details are subject to change without notice.
TRIPLE-CHANNEL TFT LCD POWER SOLUTION
WITH OPERATIONAL AMPLIFIERS
FEATURES
GENERAL DESCRIPTION
Built in 3A, 0.2Ω Switching NMOS
The AAT1164/AAT1164B/AAT1164C is a triple-channel
Positive LDO Driver Up to 28V/5mA
TFT LCD power solution that provides a step-up PWM
Negative LDO Driver Down to –14V/5mA
controller, two high voltage LDO drivers (one for positive
1 VCOM and 4 VGAMMA Operational Amplifiers
voltage and one for negative voltage), five operational
28V High Voltage Switch for VGH
amplifiers, and one high voltage switch up to 28V for
Internal Soft-Start Function
1.2MHz Fixed Switching Frequency
3 Channels Fault and Thermal Protection
Low Dissipation Current
QFN-32 Package Available
TFT LCD display.
The PWM controller consists of an on-chip voltage
reference, oscillator, error amplifier, current sense circuit,
comparator,
under-voltage
lockout
protection
and
internal soft-start circuit. The thermal and power fault
protection prevents internal circuit being damaged by
excessive power.
PIN CONFIGURATION
The high voltage LDO drivers generate two regulated
output voltage (VOUT2 and VOUT3) set by external resistor
dividers. VGH voltage does not activate until DLY voltage
exceeds 1.25V.
The
AAT1164/AAT1164B/AAT1164C
contains
4+1
operational amplifiers. VO1, VO2, VO4, and VO5 are for
gamma corrections and VO3 is for VCOM. In the short
circuit condition, operational amplifiers are capable of
sourcing ±100mA current for VGAMMA, and ±200mA
current for VCOM.
With the minimal external components, the
AAT1164/AAT1164B/AAT1164C offers a simple and
economical solution for TFT LCD power.
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April 2007
AAT1164/AAT1164B/AAT1164C
ORDERING INFORMATION
DEVICE
TYPE
PART NUMBER
PACKAGE
PACKING
TEMP.
RANGE
MARKING
AAT1164
AAT1164-Q5-T
Q5:VQFN
32-5*5
T: Tape
and Reel
–40 C to +85 C
AAT1164
XXXXX
XXXX
–40 C to +85 C
AAT1164B
XXXXX
XXXX
1. Part Name
2. Lot No.
(6~9 Digits)
3. Date Code
(4 Digits)
–40 C to +85 C
AAT1164C
XXXXX
XXXX
1. Part Name
2. Lot No.
(6~9 Digits)
3. Date Code
(4 Digits)
AAT1164B
AAT1164C
AAT1164B-Q5-T
AAT1164C-Q5-T
Q5:VQFN
32-5*5
Q5:VQFN
32-5*5
T: Tape
and Reel
T: Tape
and Reel
NOTE: All AAT products are lead free and halogen free.
TYPICAL APPLICATION
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MARKING
DESCRIPTION
1. Part Name
2. Lot No.
(6~9 Digits)
3. Date Code
(4 Digits)
Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNIT
VDD to GND
VDD
7
V
VDD1, SW to GND (for AAT1164/AAT1164B)
VH1
13.5
V
VDD1, SW to GND (for AAT1164C)
VH1
14.5
V
VOUT3, OUT3, VGH to GND
VH2
30
V
OUT2 to GND
VH3
–14
V
Input Voltage 1 (IN1, IN2, IN3, DLY, CTL,)
Input Voltage 2 (VI1+, VI1–, VI2+, VI2–, VI3+, VI3–,
VI4+, VI4–, VI5+, VI5–)
Output Voltage 1 (EO, VREF )
VI1
VDD+0.3
V
VI2
VH1+0.3
V
VO1
VDD+0.3
V
Output Voltage 2 (ADJ, VO1, VO2, VO3, VO4, VO5)
VO2
VH1+0.3
V
Operating Free-Air Temperature Range
TC
–40 C to +85 C
Storage Temperature Range
TSTORAGE
–45 C to +125 C
Pd
1,600
Power Dissipation
C
C
mW
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended period of time may affect device reliability.
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Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
ELECTRICAL CHARACTERISTICS
(VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 3.3V, VDD1 = 10V.)
PARAMETER
SYMBOL
VDD Input Voltage Range
VDD
VDD1 Input Voltage Range
VDD1
VDD Under Voltage Lockout
VDD Operating Current
VUVLO
IVDD
VDD1 Operating Current
IVDD1
Thermal Shutdown
TSHDN
TEST CONDITION
MIN
TYP
MAX
UNIT
2.6
5.5
V
AAT1164/AAT1164B
8
13
V
AAT1164C
8
14
V
Falling
2.1
2.2
2.3
V
Rising
2.3
2.4
2.5
V
VIN1 = 1.5V, Not Switching
0.56
0.80
mA
VIN1 = 1.0V, Switching
5.6
10.0
mA
7
10
mA
VVI1+~VVI5+ = 4V
160
C
Reference Voltage
PARAMETER
Reference Voltage
SYMBOL
TEST CONDITION
IVREF = 100µA
VREF
MIN
TYP
MAX
UNIT
1.231
1.250
1.269
V
Line Regulation
IVREF = 100µA,
VDD = 2.6V~5.5V
-
2
5
%/mV
Load Regulation
IVREF = 0~100µA
-
1
5
%/mA
MIN
TYP
MAX
UNIT
Oscillator
PARAMETER
SYMBOL
TEST CONDITION
Oscillation Frequency
fOSC
1.05
1.20
1.35
MHz
Maximum Duty Cycle
DMAX
84
87
90
%
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April 2007
AAT1164/AAT1164B/AAT1164C
ELECTRICAL CHARACTERISTICS
(VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 3.3V, VDD1 = 10V.)
Soft Start & Fault Detect
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
Channel 1 Soft Start Time
tSS1
14
ms
Channel 2 Soft Start Time
tSS2
14
ms
Channel 3 Soft Start Time
tSS3
14
ms
During Fault Protect Trigger Time
tFP
55
ms
IN1 Fault Protection Voltage
VF1
1.00
1.05
1.10
V
IN2 Fault Protection Voltage
VF2
0.40
0.45
0.50
V
IN3 Fault Protection Voltage
VF3
1.00
1.05
1.10
V
MIN
TYP
MAX
UNIT
1.221
1.233
1.245
V
–40
0
40
nA
Level to Produce
VEO = 1.233V
2.6V < VDD < 5.5V
0.05
0.15
%/mV
∆I = 5 µA
105
µS
1,500
V/V
Error Amplifier (Channel 1)
PARAMETER
SYMBOL
Feedback Voltage
VIN1
Input Bias Current
IB1
TEST CONDITION
VIN1 = 1V to1.5V
Feedback-Voltage Line Regulation
Transconductance
Gm
Voltage Gain
AV
N-MOS Switch (Channel 1)
PARAMETER
SYMBOL
Current Limit
ILIM
On-Resistance
RON
ISWOFF
Leakage Current
–
–
TEST CONDITION
MIN
TYP
MAX
UNIT
3.0
A
ISW = 1.0A
0.2
Ω
VSW = 12V
0.01
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20.00
µA
Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
ELECTRICAL CHARACTERISTICS
(VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 3.3V, VDD1 = 10V.)
Negative Charge Pump (Channel 2)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOUT2 = –100 µA
235
250
265
mV
VIN2 = –0.25V to 0.25V
–40
0
40
nA
–20
–50
µA
IN2 Threshold Voltage
VIN2
IN2 Input Bias Current
IB2
OUT2 Leakage Current
IOFF2
VIN2 = 0V, OUT2 = –12V
OUT2 Source Current
IOUT2
VIN2 = 0.35V, OUT2 = –10V
1
4
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOUT3 = 100 µA
1.22
1.25
1.28
V
VIN3 = 1V to 1.5V
–40
0
40
nA
40
80
µA
mA
Positive Charge Pump (Channel 3)
PARAMETER
SYMBOL
IN3 Threshold Voltage
VIN3
IN3 Input Bias Current
IB3
OUT3 Leakage Current
IOFF3
VIN3 = 1.4V, OUT3 = 28V
OUT3 Sink Current
IOUT3
VIN3 = 1.1V, OUT3 = 25V
1
4
mA
MIN
TYP
MAX
UNIT
High Voltage Switch Controller
PARAMETER
SYMBOL
TEST CONDITIONS
DLY Source Current
IDLY
−4
−5
−6
µA
DLY Threshold Voltage
VDLY
1.22
1.25
1.28
V
DLY Discharge RON
RDLY
8
CTL Input Low Voltage
VIL
CTL Input High Voltage
VIH
CTL Input Bias Current
IB4
VCTL = 0 to VDD
Propagation Delay CTL to VGH
tPP
OUT3 = 25V
100
Ω
0.5
2
–40
V
V
0
40
nA
ns
VOUT3 to VGH Switch R-on
RONSC
VDLY = 1.5V, VCTL = VDD
15
30
Ω
ADJ to VGH Switch R-on
RONDC
VDLY = 1.5V, VCTL = GND
30
60
Ω
VGH to GND1 Switch R-on
RONCG
VDLY = 1V
2.5
3.5
kΩ
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1.5
Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
ELECTRICAL CHARACTERISTICS
(VDD = 2.6V to 5.5V, TC = –40 ° C to 85 ° C , unless otherwise specified. Typical values are tested at 25 ° C ambient
temperature, VDD = 3.3V, VDD1 = 10V.)
VCOM and VGAMMA Buffer
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Offset Voltage
VOS
VVI1+ ~ VVI5+ = 4V
-
2
12
mV
Input Bias Current
IB5
VVI1+ ~ VVI5+ = 4V
−40
0
40
nA
-
-
VOL
IVO1, IVO2, IVO4, IVO5 =
5mA,
VVI1, VVI2, VVI4, VVI5 = 0V,
4V,10V
VVI–
+0.15
IVO3 = 50mA, VVI3 = 4V
-
4.03
4.06
VVI–
−0.15
-
-
3.94
3.97
-
IVO1, IVO2, IVO4, IVO5
-
±100
-
mA
IVO3
-
±200
-
mA
VVI1+, VVI3+ = 2V to 8V,
VVI3+ ~ VVI5+ = 8V to 2V,
20% to 80%
-
12
-
V/ µs
VVI1+ ~ VVI5+ = 3.5V to 4.5V,
90%
-
5
-
µs
Output Swing
VOH
IVO1, IVO2, IVO4, IVO5 =
–50mA,
VVI1, VVI2, VVI4, VVI5 = 0V,
4V, 10V
IVO3 = –50mA, VVI3 = 4V
Short Circuit Current
ISHORT
Slew Rate
SR
Settling Time
tS
–
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V
Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
TYPICAL OPERATING CHARACTERISTICS
(VIN = 5V, VOUT1 = 12V, VOUT2 = –7V, VOUT3 = 27V, TC = +25 C , unless otherwise noted.)
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AAT1164/AAT1164B/AAT1164C
TYPICAL OPERATING CHARACTERISTICS (CONT.)
(VIN = 5V, VOUT1 = 12V, VOUT2 = –7V, VOUT3 = 27V, TC = +25 C , unless otherwise noted.)
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April 2007
AAT1164/AAT1164B/AAT1164C
PIN DESCRIPTION
PIN NO.
QFN-32
1
NAME
I/O
VOUT3
-
Channel 3 Output Voltage (gate high voltage input)
2
VERF
O
Internal Reference Voltage Output
3
GND
-
Ground
4
GND1
-
SW MOS Ground
5
VO1
O
Operational Amplifier 1 Output
6
VI1–
I
Operational Amplifier 1 Negative Input
7
VI1+
I
Operational Amplifier 1 Positive Input
8
VO2
O
Operational Amplifier 2 Output
9
VI2–
I
Operational Amplifier 2 Negative Input
10
VI2+
I
Operational Amplifier 2 Positive Input
11
GND2
-
Ground for Operational Amplifiers
12
VI3+
I
VCOM Operational Amplifier Positive Input
13
VO3
I
VCOM Operational Amplifier Output
14
VDD1
-
High Voltage Power Supply Input
15
VI4+
I
Operational Amplifier 4 Positive Input
16
VI4–
I
Operational Amplifier 4 Negative Input
17
VO4
O
Operational Amplifier 4 Output
18
VI5+
I
Operational Amplifier 5 Positive Input
19
VI5–
I
Operational Amplifier 5 Negative Input
20
VO5
O
Operational Amplifier 5 Output
21
SW
-
Main PWM Switching Pin
22
VDD
-
Power Supply Input
23
IN1
I
Main PWM Feedback Pin
24
EO
O
Main PWM Error Amplifier Output
25
IN3
I
Positive Charge Pump Feedback Pin
DESCRIPTION
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AAT1164/AAT1164B/AAT1164C
PIN NO.
QFN-32
NAME
I/O
26
OUT3
O
Positive Charge Pump Output
27
IN2
I
Negative Charge Pump Feedback Pin
28
OUT2
O
Negative Charge Pump Output
29
DLY
I
High Voltage Switch Delay Control
30
CTL
I
High Voltage Switch Control Pin
31
ADJ
O
Gate High Voltage Fall Time Setting Pin
32
VGH
O
Switching Gate High Voltage for TFT
DESCRIPTION
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April 2007
AAT1164/AAT1164B/AAT1164C
FUNCTION BLOCK DIAGRAM
AAT1164/AAT1164B
2
22
VREF
VDD
Reference Voltage
23 IN1
Fail / Thermal
Control
Fail
1.233V
1.25V
0.25V
Error Amplifier
SW 21
1. 233V
Digital Control Block
GND1
24
4
EO
Comparator
Current Sense
and Limit
Oscillator
27 IN2
0. 25V
OUT2 28
1. 25V
OUT3 26
25 IN3
6 VI1--
VO1 5
7 VI1+
9 VI2-10
GND 3
GND2 11
VO2 8
VI2+
12 VI3+
VO3
16 VI4-
VO4
15 VI4+
19 VI518
31
17
VO5 20
VI5+
29 DLY
30
13
VDD1
CTL
14
High Voltage Control
VOUT3
ADJ
32
–
–
VGH
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1
Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
FUNCTION BLOCK DIAGRAM
AAT1164/AAT1164C
2
22
VREF
VDD
Reference Voltage
23 IN1
Fail / Thermal
Control
Fail
1.233V
1.25V
0.25V
Error Amplifier
SW 21
1. 233V
Digital Control Block
GND1
24
4
EO
Comparator
Current Sense
and Limit
Oscillator
27 IN2
0. 25V
OUT2 28
1. 25V
OUT3 26
25 IN3
6 VI1--
VO1 5
7 VI1+
9 VI2-10
GND 3
GND2 11
VO2 8
VI2+
12 VI3+
VO3
16 VI4-
VO4
15 VI4+
19 VI518
17
VO5 20
VI5+
29 DLY
30
13
VDD1
CTL
14
High Voltage Control
2.5kΩ
Ω
31
VOUT3
ADJ
32
–
–
VGH
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Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
TYPICAL APPLICATION CIRCUIT
Figure 1. Application Circuit
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AAT1164/AAT1164B/AAT1164C
DESIGN PROCEDURE
k=
Boost Converter Design
Setting the Output Voltage and Selecting
the Lead Compensation Capacitor
The output voltage of boost converter is set by the
resistor divider from the output (VOUT1) to GND with the
center tap connected to IN1, where VIN1, the boost
converter feedback regulation voltage is 1.233V,
Choose R2 (Figure 2) between 5.1kΩ to 51kΩ and
calculate R1 to satisfy the following equation.
∆ILpeak-peak
IIN
η : Boost converter efficiency
k: The ratio of the inductor peak to peak ripple current to
the input DC current
VIN: Input voltage
VO: Output voltage
IO: Output load current
fS: Switching frequency
D: Duty cycle
∆ILpeak–peak: Inductor peak to peak ripple current
IIN: Input DC current
V

R1 = R2  OUT1 − 1
 VIN1

The AAT1164 SW current limit ( ILIM ) and inductor’s
VOUT1
saturation current rating ( ILSAT ) should exceed IL(peak),
and the inductor's DC current rating should exceed IIN.
VREF
EO
24
gm
IN1
For the best efficiency, choose an inductor with less DC
R1
23
series resistance ( rL ).
VIN1
RC
R2
CP
ILIM and ILSAT > IL(peak )
ILDC > IIN
CC
GND
GND
IL(peak) = IIN +
IIN =
Figure 2. Feedback Circuit
VIND
,
2LfS
IO
,
η(1 − D)
2
Inductor Selection
The minimum inductance value is selected to make
sure that the system operates in continuous conduction
mode (CCM) for high efficiency and to prevent EMI. The
 IO 
PDCR ≈ 
 rL
 η(1 − D) 
ILDC: DC current rating of inductor
PDCR: Power loss of inductor series resistance
equation of inductor uses a parameter k, which is the
ratio of the inductor peak to peak ripple current to the
Table 1. Inductor Data List
rL
DC CURRENT RATING
input DC current. The best trade-off between voltage
C6-K1.8L
ripple of transient output current and permanent output
3.9 µ H
41mΩ
2.5A
current has a k between 0.4 and 0.5.
6.8 µ H
ηVO
L≥
D(1 − D)2 ,
kIO fS
68mΩ
2.2A
10 µ H
81mΩ
1.8A
MITSUMI Product-Max Height:1.9mm
V
D = 1 − IN
VO ,
–
–
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AAT1164/AAT1164B/AAT1164C
Example 1: In the typical application circuit (Figure 1)
For example,
the output load current is 300mA with 13.3V output
PDIODE = PDSW + PDCOM = 0.0273W or 0.68% power loss.
voltage and input voltage of 5V. Choose a k of 0.431
and efficiency of 90%.
L≥
Input Capacitor Selection
The input capacitors have two important functions in
0.9 * 13.3
0.624(0.376)2 ≈ 6.8 µ H
PWM controller. First, an input capacitor provides the
0.431* 0.3 * 1.26
IO
IIN =
= 0.886A
η(1 − D)
power for soft start procedure and supply the current for
the gate-driving circuit. A 10 µ F ceramic capacitor is
used in typical circuit. Second, an input bypass
V D
IL(peak ) = IIN + IN = 1.0778A
2LfS
capacitor reduces the current peaks, the input voltage
drop, and noise injection into the IC. A low ESR
PDCR = 0.0534W or 1.34% power loss
ceramics capacitor 0.1 µ F is used in typical circuit. To
ensure the low noise supply at VDD, VDD is decoupled
Schottky Diode Selection
from input capacitor using an RC low pass filter.
Schottky has to be able to dissipate power. The
dissipated power is the forward voltage and input DC
current. To achieve the best efficiency, choose a
Schottky diode with less recovery capacitor (CT) for fast
recovery time and low forward voltage (VF).
For boost converter, the reverse voltage rating (VR)
should be higher than the maximum output voltage, and
VDD
current rating should exceed the input DC current.
VDD
PDIODE = PDSW + PDCOM
PDSW = (1–D) VFQRfS
Figure 3. Input Bypass Capacitor Affects the VDD
Drop.
QR = VRCTQR
PDCOM = VFIO (1–D)
PDIODE: Total power loss of diode for boost converter
PDSW : Switching loss of diode for boost converter
PDCOM: Conduction loss of diode for boost converter
Table 2. Schottky Data List
Output Capacitor
The output capacitor maintains the DC output voltage. A
Low ESR ( rC ) ceramic capacitor can reduce the output
ripple and power loss. There are two parameters which
can affect the output voltage ripple: 1. the voltage drops
SMA
VF
VR
CT
when the inductor current flows through the ESR of
B220A
0.24V
14V
150pF
output capacitor; 2. charging and discharging of the
B240A
0.24V
28V
150pF
output capacitor also affect the output voltage ripple.
VRIPPLE = VRIPPLE (COUT ) + VRIPPLE (ESR)
DIODES Product-Max Height: 2.3mm
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AAT1164/AAT1164B/AAT1164C
VRIPPLE (COUT ) ≈
IO D
β
fS COUT
VRIPPLE (ESR) ≈ I L(peak) rC
V
IC(rms) = O
RL
(
D
D (1 − D)RL 2
+
[
]
1 − D 12
LfS
PESR = IC(rms)
)
2
rC
ESR: Equivalent Series Resistance
Figure 4. Closed-Current Loop for Boost with PCM
Example 2: COUT = 38µF, rC = 20 mΩ
VRIPPLE (COUT ) = 4.1mV
VRIPPLE (ESR) = 21.5mV
VRIPPLE = 25.6mV
IC(rms) = 0.411A
PESR = 0.00338W or 0.08% power loss
+
+
−
−
Boost Converter Power loss
−
The largest portions of power loss in the boost
β
+
converter are the internal power MOSFET, the inductor,
the Schottky diode, and the output capacitor. If the
boost
converter
has
90%
efficiency,
approximately 7.89% power loss
there
is
in the internal
MOSFET, 1.34% power loss in the inductor, 0.68%
Figure 5. Block Diagram of Boost Converter with
Peak Current Mode (PCM)
power loss in the Schottky diode, and 0.08% power loss
in the output capacitor.
Power Stage Transfer Functions
The duty to output voltage transfer function Tp is:
Loop Compensation Design
The voltage-loop gain with current loop closed sets the
stability
of
performance
steady
of
state
transient
response
and
response.
Tp (s) =
dynamic
The
loop
VO
(s + ωesr )(s − ωz2 )
= Tp0
d
s2 + 2ξωn s + ωn2
Where Tp0 = VO
compensation design is as follows:
−rC
1
, ωesr =
C
1
−
D
R
+
r
(
)( L C )
OUTrC
And
2
ωz2 =
–
–
RL (1 − D ) − r
L
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, ωn =
(1 − D )2 RL + r
LCOUT (RL + rC )
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April 2007
AAT1164/AAT1164B/AAT1164C
2
ξ=
COUT [r (RL + rC ) + RL rC (1 − D ) ] + L
2
,
Ticl (s) =
2 LCOUT (RL + rC ) [r + (1 − D ) RL ]
r = rL + DrDS + (1 − D)RF
rL is the inductor equivalent series resistance, rC is
capacitor ESR, RL is the converter load resistance, COUT
is the output filter capacitor, rDS is the transistor turn on
resistance, and RF is the diode forward resistance.
The duty to inductor current transfer functionTpi is:
i
s + ωzi
Tpi (s) = l = Tpi0 2
d
s + 2ξωn s + ωn2
Where Tpi0 =
)
(
)
The Voltage-Loop Gain with Current Loop
Closed
The control to output voltage transfer function Td is:
Td (s) =
VO (s)
= Ticl (s)Tp (s)
VC (s)
The voltage-loop gain with current loop closed is:
L VI (s) = βTC (s)Td (s)
VO (RL + 2rC )
1
, ωzi =
COUT (RL / 2 + rC )
L (RL + rC )
= βgm R C
2
s + ω c 12fS Tp0
×
s
R CS Tpi0
( s + ωz1 )( s − ωz2 )
( s + ωzi ) (s2 + sωsh + 12fS2 )
Current Sampling Transfer Function
Error voltage to duty transfer function Fm (s) is:
(
(
s2 + 2ξωn s + ωn2
12fS2
x
RCS Tpi0 ( s + ω ) s2 + ω s +12f 2
zi
sh
S
)
2fS2 s2 + 2ξωn s + ωn2
d
Fm (s) =
=
Vei Tpi0RCS s ( s + ωzi ) ( s + ωsh )
V
Where β = FB
VO
The compensator transfer function
Where ωsh
3ωs  1 − α 
M − Ma
=
,α = 2
,


π  1+ α 
M1 + Ma
TC (s) =
ωs = 2πfS
VC
s + ωc
= gmRC
,
Vfb
s
Where
Therefore, Fm(s) depends on duty to inductor current
ωc =
1
RCCC
transfer function Tpi(s), and fS is the clock switching
frequency;
RCS
is
the
current-sense
amplifier
transresistance.
For the boost converter M1 = VIN / L and
M2 = (VO–VIN) / L.
For AAT1164, RCS = 0.24 V/A, Ma is slope
compensation, Ma = 0.8×10
6.
The closed-current loop transfer function Tpi(s) is:
Figure 6. Voltage Loop Compensator
–
–
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AAT1164/AAT1164B/AAT1164C
Compensator design guide:
Bode Diagram
60
1
1. Crossover frequency fci < fS
2
Magnitude (dB)
40
2. Gain margin>10dB
3. Phase margin>45
∘
20
0
-20
-40
-90
-135
Phase (deg)
4. The L VI (s) = 1 at crossover frequency, Therefore,
the compensator resistance, RC is determined by:
-180
-225
-270
2
(RL + 2rC )
V 2πfciCOUTRCS
RC = O
VFB
gmk

r 
(1 − D ) RL −

(1 − D ) 

COUT
Table 3. k Factor Table
Best Corner
Frequency
10
3
4
10
10
5
10
6
10
Frequency (Hz)
Figure 7. Bode Plot of Loop Gain Using Matlab
Simulation
®
Positive and Negative LDO Driver
Output Voltage Selection
k Factor
The output voltage of positive LDO driver is set by a
21.533µF
23.740kHz
4.692
resistive divider from the output (VOUT3) to GND with the
25.079µF
21.842kHz
5.083
center tap connected to the IN3, where VIN3, the positive
32.587µF
20.095kHz
6.042
LDO driver feedback regulation voltage, is 1.25V.
36.312µF
15.649kHz
5.230
Choose R6 (Figure 8) between 10kΩ and 51kΩ . And
38.469µF
13.247kHz
4.703
calculate R5 with the following equation.
5. The output filter capacitor is chosen so COUTRL
pole cancels RCCC zero
V

R5 = R6  OUT3 − 1
 VIN3

R

εRCCC = COUT  L + rC  , and
 2

C
R

CC = OUT  L + rC 
εRC  2

negative LDO driver feedback regulation voltage, is
ε = (1 ~ 3)
0.25V. Choose R9 (Figure 9) between 10kΩ and
The output voltage of negative LDO driver is set by a
resistive divider from the output (VOUT2) to VREF with
the center tap connected to IN2, where VIN2, the
51kΩ and calculate R8 with the following equation.
Example 3:
VIN = 5V, VO = 13.3V, IO = 300mA, fS = 1,190kHz,
 V − VOUT2 
R8 = R9  IN2

 VREF − VIN2 
VFB = 1.233V, L = 6.65µH, gm = 85µS,
rL = 76.689 mΩ
rC = 9.13 mΩ , RF = 0.7667 Ω , CC = 1.95nF,
RC = 7.6 kΩ , COUT = 38.5 µ F , ε = 3, RCS = 0.23V/A.
–
–
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AAT1164/AAT1164B/AAT1164C
SW
used. BAT54S (Figure 8 and 9) has fast recovery time
C5
1µF
C6
1µF
VOUT1
13.3V/300mA
U1
BAT54S
R4
6.8k Ω
LDO Driver Base-Emitter Resistors
Q1
MMBT4403
OUT3 26
For AAT1164, the minimum drive current for positive
and negative LDO drivers are 1mA, thus the minimum
C7
1µF
U2
BAT54S
SW
R5
200 k Ω
base-emitter resistance can be calculated by the
VOUT3
25V/30mA
IN3 25
R6
10kΩ
and low forward voltage for best efficiency.
C8
1µF
following equation:
R 4 (min) ≥ VBE(max) / ((IOUT3(min) − IC ) / hfe(min) )
VOUT3 1
R 7(min) ≥ VBE(max) / ((IOUT2(min) − IC ) / hfe(min) )
Figure 8. The Positive LDO Driver
Table 4. Pass Transistor Specifications
MMBT4401
MMBT4403
VBE(max)
0.65V
0.5V
hfe(min)
130
90
DIODES Product, Package: SOT23
Example 5:
Output current of VOUT3 and VOUT2 are 30mA, the
minimum base-emitter resistor can be calculated as
Figure 9. The Negative LDO Driver
R 4 (min) ≥ 0.5 / (( 1mA − 30mA ) / 90) ≥ 750 Ω
Example 4:
For system design
R 7(min) ≥ 0.65 / (( 1mA − 30mA ) / 130) ≥ 845 Ω
VOUT3 = 25V, R5 = 200kΩ, R6 = 10kΩ,
The minimum value can be used, however, the larger
value has the advantage of reducing quiescent current.
VOUT2 = −6V, R8 = 62kΩ, R9 = 10kΩ
So we choose 6.8kΩ to be R4.
Flying Capacitors
Increasing the flying capacitor (C5, C7, C9) values can
lower
output
voltage
ripples.
The
1µF
ceramic
capacitors works well in positive LDO driver. A 0.1µF
ceramic capacitor works well in negative LDO driver.
Charge Pump Output Capacitor
Using low ESR ceramic capacitor to reduce the output
voltage ripple is recommended and output voltage ripple
is dominated by the capacitance value. The minimum
capacitance value can be calculated by the following
equation:
LDO Driver Diode
To achieve high efficiency, a Schottky diode should be
–
–
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AAT1164/AAT1164B/AAT1164C
COUT ≥
ILOAD
2Vripple fS
Example 6:
The output voltage ripple of VOUT3 and VOUT2 is under
1%, the minimum capacitance value can be calculated
as
COUT (VOUT3 ) ≥
30mA
≈ 0.1µF
η2 × 250mV × 1.19MHz
COUT (VOUT2 ) ≥
30mA
≈ 0.33µF
η2 × 60mV × 1.19MHz
η : Efficiency, about 60% at charge pump circuit
Table 5. Recommended Components
DESIGNATION
DESCRIPTION
6.8 µH, 1.8A,
L
MITSUMI C6-K1.8L 6R8
200mA 30V Schottky barrier
diode (SOT-23),
U1, U2, U3
DIODES BAT54S
2A 20V rectifier diode
D
DIODES DFLS220L
C3
C5, C6, C7
C2, C4, C9, C10, C12
10 µF, 25V X5R ceramic
capacitor
1 µF, 25V X5R ceramic
capacitor
0.1 µF, 50V X5R ceramic
capacitor
Operational Amplifier
The AAT1164 has five independent amplifiers. The
operational amplifiers are usually used to drive VCOM
and the gamma correction divider string for TFT-LCD.
The output resistors and capacitors of amplifiers are
used as low pass filters and compensators for unity gain
stable.
–
–
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AAT1164/AAT1164B/AAT1164C
Soft Start Waveform
LAYOUT CONSIDERATION
supply. The ground connection of the VDD and VREF
The system’s performances including switching noise,
transient response, and PWM feedback loop stability
bypass capacitor should be connected to the analog
ground pin (GND) with a wide trace.
are greatly affected by the PC board layout and
Output Capacitors
grounding. There are some general guidelines for
Place output capacitors as close as possible to the IC.
layout:
Minimize the length and maximize the width of traces to
get the best transient response and reduce the ripple
Inductor
Always try to use a low EMI inductor with a ferrite core.
noise. We choose 10µF ceramics capacitor to reduce
the ripple voltage, and use 0.1µF ceramics capacitor to
reduce the ripple noise.
Filter Capacitors
Place low ESR ceramics filter capacitors (between
0.1µF and 0.22µF) close to VDD and VREF pins. This
will eliminate as much trace inductance effects as
possible and give the internal IC rail a cleaner voltage
–
–
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AAT1164/AAT1164B/AAT1164C
Feedback
If external compensation components are needed for
stability, they should also be placed close to the IC.
Take care to avoid the feedback voltage-divider
resistors’ trace near the SW. Minimize feedback track
lengths to avoid the digital signal noise of TFT control
board.
Ground Plane
The grounds of the IC, input capacitors, and output
capacitors should be connected close to a ground plane.
It would be a good design rule to have a ground plane
on the PCB. This will reduce noise and ground loop
errors as well as absorb more of the EMI radiated by the
inductor. For boards with more than two layers, a
ground plane can be used to separate the power plane
and the signal plane for improved performance.
PC Board Layout
–
–
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AAT1164/AAT1164B/AAT1164C
PACKAGE DIMENSION
VQFN32
C
PIN 1 INDENT
b
E2
E
e
A1
D
A
D2
L
Symbol
A
A1
b
C
D
D2
E
E2
e
L
y
Dimensions In Millimeters
MIN
TYP
MAX
0.8
0.9
1.0
0.00
0.02
0.05
0.18
0.25
0.30
-----0.2
-----4.9
5.0
5.1
3.05
3.10
3.15
4.9
5.0
5.1
3.05
3.10
3.15
-----0.5
-----0.35
0.40
0.45
0.000
-----0.075
–
–
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