TI TUSB2040

TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
D
D
D
D
D
D
D
D
OVRCUR2
PWRON1
OVRCUR1
DP0
DM0
GND
DP1
DM1
BUSPWR/SCL
GANGED/SDA
DP2
DM2
VCC
DP3
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
PWRON2
VCC
OVRCUR3
PWRON3
GND
XTAL1
XTAL2
EXTMEM
PWRON4
OVRCUR4
RESET
DM4
DP4
DM3
PT PACKAGE
(TOP VIEW)
48
47
description
If programmable vendor ID(VID) and product
ID(PID) descriptors are desired, pin 21 must be
high (EXTMEM = 1) and a SGS Thompson
M93C46 or equivalent EEPROM must be
connected to pins 9 and 10. For this configuration,
the values for BUSPWR and GANGED are stored
in the EEPROM and pins 9 and 10 become the
EEPROM interface.
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
GND
XTAL1
XTAL2
NC
EXTMEM
NC
NC
PWRON4
NC
OVRCUR4
NC
RESET
13
14
15
16
17
18
19
20
21
22
23
24
DP0
DM0
GND
NC
NC
DP1
DM1
NC
NC
BUSPWR/SCL
GANGED/SDA
NC
DP2
DM2
V CC
NC
NC
DP3
DM3
SUSPND
NC
NC
DP4
DM4
The TUSB2040A hub is a 3.3-V CMOS device
that provides up to four downstream ports in
compliance with the USB specification 1.0
version. Pin 21 (EXTMEM) enables or disables
the EEPROM interface. When EXTMEM is low,
the TUSB2040A is functionally equivalent to the
TUSB2040 hub and the product ID (PID)
displayed during enumeration is General Purpose
USB Hub. For this configuration, pins 9 and 10 are
the BUSPWR and GANGED input pins,
respectively.
1
46
45
44
43
42
41
40
39
38
37
D
D
D
N PACKAGE
(TOP VIEW)
Universal Serial Bus (USB) Version 1.0
Compliant
Integrated USB Transceivers
Four Downstream Ports
Two Power Source Modes
– Self-Powered Mode
– Bus-Powered Mode
Power Switching and Overcurrent
Reporting is Provided Ganged or Per Port
All Downstream Ports Support Full-Speed
and Low-Speed Operations
Supports Suspend and Resume Operations
Pin-to-Pin Compatible with the TUSB2040
Device when EXTMEM Pin is Low
Supports Programmable Vendor ID and
Product ID With External Serial EEPROM
Tri-State EEPROM Interface Allows
EEPROM Sharing
Available in 28-Pin DIP and 48-Pin TQFP
Packages
3.3-V Operation
OVRCUR1
PWRON1
OVRCUR2
NC
PWRON2
NC
NC
V CC
NC
NC
OVRCUR3
PWRON3
D
† JEDEC descriptor S–PQFP–G for thin quad flatpack (TQFP)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
description (continued)
The TUSB2040A supports bus-power and self-power modes. The power switching to the downstream ports can
either be controlled individually or ganged using external devices to switch power and to detect overcurrent
conditions. Outputs from the external power devices provide overcurrent inputs to the TUSB2040A OVRCUR
pins and in the case of an overcurrent condition, the corresponding PWRON pins will be disabled by the
TUSB2040A. In the GANGED operation, all PWRON signals transition simultaneously, and any OVRCUR input
can be used.
The hub requires a 48-MHz clock signal to sample data from the upstream port and generate a synchronized
12-MHz USB clock signal. The hub supports the flexibility to use any device that generates a 48-MHz clock.
Because the majority of oscillators are active devices, the low power suspend mode of the TUSB2040A will not
function because there is no way to stop the oscillator from driving the internal clock. An oscillator with a TTL
output not exceeding 3.6 V can be used by connecting its output to the XTAL1 terminal and leaving the XTAL2
terminal open. For crystal or resonator implementations, use the XTAL1 terminal as the input and the XTAL2
terminal as the feedback path. Because the crystal is required to resonate at 48 MHz, a tuning circuit as shown
in Figure 8 may be required.
The upstream port and all downstream ports are USB-compliant transceivers. Every downstream port supports
both full-speed and low-speed connections by automatically setting the slew rate according to the speed of the
device attached to the port.
2
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TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
functional block diagram
DP0
4
DM0
5
USB
Transceiver
23
OSC
Suspend / Resume
Logic and
Frame Timer
Hub Repeater
SIE
XTAL1
22
XTAL2
18
RESET
21
SIE Interface
Logic
EXTMEM
10
Serial
EEPROM
Interface
9
GANGED/SDA
BUSPWR/SCL
Port 1
Logic
Hub / Device
Command
Decoder
Port 4
Logic
USB
Transceiver
16
DP4
17
DM4
USB
Transceiver
7
8
DP1
DM1
Hub
Power
Logic
3, 1, 26, 19
2, 28, 25, 20
OVRCUR1 – OVRCUR4
PWRON1 – PWRON4
NOTE: Terminal numbers shown are for the N package.
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3
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
Terminal Functions
TERMINAL
I/O
DESCRIPTION
10
I/O
Power source input/EEPROM serial clock. When EXTMEM is low, BUSPWR/SCL is an active
low input that indicates whether the ports and the hub derive power from the bus or the local
supply. When EXTMEM is high, BUSPWR/SCL acts as a tri-state serial clock output to the
EEPROM with a 100 µA internal pulldown. This standard TTL input must not change dynamically
during operation.
NAME
N
PT
BUSPWR/SCL
9
DM0
5
2
I/O
Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
8, 12,
15, 17
7, 14,
19, 24
I/O
USB differential data minus. DM1 – DM4 paired with DP1 – DP4 support up to four downstream
USB ports.
4
1
I/O
Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
7, 11,
14, 16
6, 13,
18, 23
I/O
USB differential data plus. DP1 – DP4 paired with DM1 – DM4 support up to four downstream
USB ports.
10
11
I/O
Power switching and overcurrent detection mode/EEPROM serial data I/O. When EXTMEM is
low, GANGED/SDA selects between gang or per port switching for the overcurrent detection of
the downstream ports. When EXTMEM is high, GANGED/SDA acts as a tri-state serial data I/O
to and from the EEPROM with a 100 µA internal pull-down. This standard TTL input must not
change dynamically during operation.
6, 24
3, 36
21
32
I
EEPROM read enable. When EXTMEM is low, it disables the serial EEPROM interface of the
device. Pins 9 and 10 are configured as BUSPWR and GANGED, respectively. When EXTMEM
is high, it enables the serial EEPROM interface and pins 9 and 10 are configured as SCL and
SDA, respectively.
OVRCUR1 –
OVRCUR4
3, 1,
26, 19
48, 46,
38, 27
I
Overcurrent indicators. OVRCUR1 – OVRCUR4 are active low, standard TTL inputs. One
overcurrent indicator is available for each of the four downstream ports. In GANGED mode, one
implementation is to tie these inputs together. Alternatively, one OVRCUR input pin may be used
with the remaining OVRCUR pins tied to VCC.
PWRON1 –
PWRON4
2, 28,
25, 20
47, 44,
37, 29
O
Power-on/-off control signals. PWRON1 – PWRON4 are active low, open-drain outputs. One
power-on/-off control switch is used for each of the four downstream ports. In GANGED mode,
all outputs are switched together.
18
25
I
Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When
RESET is asserted, it initializes all logic.
20
O
Suspend status. SUSPND is an active high output that is available for external logic power down
operations. During the SUSPEND mode, SUSPND is high. SUSPND is low for normal operation.
DM1 – DM4
DP0
DP1 – DP4
GANGED/SDA
GND
EXTMEM
RESET
SUSPND
Ground. GND terminals must be tied to ground for proper operation.
VCC
XTAL1
13, 27
15, 41
23
35
I
3.3-V supply voltage
Crystal 1. XTAL1 is a 48-MHz crystal input with 50% duty cycle. Operation at 48-MHz is four times
the USB full-speed bit rate of 12 Mbps.
XTAL2
22
34
O
Crystal 2. XTAL2 is a 48-MHz crystal output. Operation at 48-MHz is four times the USB full-speed
bit rate of 12 Mbps. This terminal is left open when using an oscillator.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 3.8 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK, (VI < 0 V or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK, (VO < 0 V or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.
4
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TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC
3
3.3
3.6
V
Input voltage, TTL/LVCMOS, VI
0
0
VCC
VCC
V
Output voltage, TTL/LVCMOS, VO
High-level input voltage, signal-ended receiver, VIH(REC)
2
VCC
0.8
V
2
VCC
0.8
V
0
70
°C
Low-level input voltage, signal-ended receiver, VIL(REC)
High-level input voltage, TTL/LVCMOS, VIH(TTL)
Low-level input voltage, TTL/LVCMOS, VIL(TTL)
Operating free-air temperature, TA
External series, differential driver resistor, R(DRV)
22 (–5%)
Operating (dc differential driver) low speed mode, f(OPRL)
Input transition times, tt, TTL/LVCMOS
V
V
V
22 (+5%)
Operating (dc differential driver) high speed mode, f(OPRH)
Common mode, input range, differential receiver, V(ICR)
UNIT
Ω
12
Mb/s
1.5
Mb/s
0.8
2.5
V
0
6
ns
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETER
VOH
High level output voltage
High-level
VOL
Low-level output voltage
TEST CONDITIONS
USB data lines
TTL /LVCMOS
VIT
IT+
VIT
IT–
USB data lines
R(DRV) = 15 kΩ, to GND
IOH = – 12 mA (without R(DRV))
IOL = 4 mA
MIN
MAX
2.8
3.6
VCC – 0.5
Single-ended
0.5
0.3
IOL = 12 mA (without R(DRV))
0.5
2
V
0.8 V ≤ VICR ≤ 2.5 V
1.8
V
TTL /LVCMOS
Negative input threshold voltage
Negative-input
Vh
hys
Input hysteresis† (VT+ – VT–)
IOZ
High impedance output current
High-impedance
IIL
IIH
Single-ended
V
R(DRV) = 1.5 k Ω to 3.6 V
TTL /LVCMOS
Positive input threshold voltage
UNIT
0.8
0.8 V ≤ VICR ≤ 2.5 V
TTL /LVCMOS
V
V
1
V
0.25
0.7
V
300
500
mV
Single-ended
0.8 V ≤ VICR ≤ 2.5 V
TTL/LVCMOS
V = VCC or GND‡
± 10
µA
USB data lines
0 V ≤ VO ≤ VCC
± 10
µA
Low-level input current
TTL/LVCMOS
µA
TTL/LVCMOS
VI = GND
VI = VCC
–1
High-level input current
1
µA
zo(DRV)
Driver output impedance
USB data lines
Static VOH or VOL
7.1
19.9
Ω
VID
Differential input voltage
USB data lines
0.8 V ≤ VICR ≤ 2.5 V
0.2
ICC
Input supply current
Normal operation
Suspend mode
V
100
mA
1
µA
† Applies for input buffers with hysteresis
‡ Applies for open drain buffers
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5
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
differential driver switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 50 pF unless otherwise noted (see Figures 1 and 2)
full speed mode
PARAMETER
TEST CONDITIONS
tr
tf
Transition rise time for DP or DM
See Figure 1 and Figure 2
Transition fall time for DP or DM
See Figure 1 and Figure 2
t(RFM)
VO(CRS)
Rise/fall time matching
(tr/tf) x 100
Signal crossover output voltage
MIN
MAX
4
20
UNIT
ns
4
20
ns
90
110
%
1.3
2.0
V
MIN
MAX
UNIT
low speed mode
PARAMETER
TEST CONDITIONS
tr
tf
Transition rise time for DP to DM
CL = 50 pF to 350 pF,
See Figure 1 and Figure 2
75
300
ns
Transition fall time for DP to DM
CL = 50 pF to 350 pF,
See Figure 1 and Figure 2
75
300
ns
t(RFM)
VO(CRS)
Rise/fall time matching
(tr/tf) x 100
CL = 50 pF to 350 pF
80
120
%
1.3
2.0
V
Signal crossover output voltage
Characterization
measurement point
DP
V(TERM) = 2.8 V
22 Ω
Full
15 kΩ
DM
1.5 kΩ
CL
22 Ω
Low
15 kΩ
CL
Figure 1. Differential Driver Switching Load
DM
DP
90%
VOH
90%
10%
10%
tr
tf
Figure 2. Differential Driver Timing Waveforms
6
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VOL
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
V ID – Differential Receiver Input Sensitivity – V
1.5
1.3
1
0.5
0.2
0
0
3
1
2
3.6
0.8
2.5
VICR – Common Mode Input Range – V
4
Figure 3. Differential Receiver Input Sensitivity vs. Common Mode Input Range
Vhys
Logic high
VCC
VIH
VIT+
VIT–
VIL
Logic low
0V
Figure 4. Single-Ended Receiver Input Signal Parameter Definitions
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7
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
APPLICATION INFORMATION
A major advantage of USB is the ability to connect 127 functions configured in up to six logical layers (tiers) to
a single personal computer (see Figure 5).
PC
With Root Hub
Monitor
With 4-Port Hub (Self-Powered)
Keyboard
With 4-Port Hub
(Bus-Powered)
Left
Speaker
Mouse
Modem
Telephone
Right
Speaker
Printer
With 4-Port Hub
(Self-Powered)
Scanner
Digital
Scanner
Figure 5. USB Tiered Configuration Example
Another advantage of USB is that all peripherals are connected using a standardized four wire cable that
provides both communication and power distribution. The three power configurations are bus-powered,
self-powered and high-powered modes. For all three configurations, 100 mA is the maximum current that may
be drawn from the USB 5-V line during power up. For the bus-powered mode, a hub can draw a maximum of
500 mA from the 5-V line of the USB cable. A bus-powered hub must always be connected downstream to a
self-powered hub unless it is the only hub connected to the PC and there are no high-powered functions
connected downstream. In the self-powered mode, the hub is connected to its own power supply and can supply
up to 500 mA to each downstream port. High-powered functions may draw a maximum of 500 mA and may only
be connected downstream to self-powered hubs.
Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two
types of protection are individual port management (individual port basis) or ganged port management (multiple
port basis). Individual port management requires power management devices for each individual downstream
port, but adds robustness to the USB system because, in the event of an overcurrent condition, the USB host
powers down the port that has the condition. The ganged configuration uses fewer power management devices
and thus has lower system costs, but in the event of an overcurrent condition on any of the downstream ports,
all the ganged ports are disabled by the USB host.
Using a combination of the BUSPWR and GANGED inputs, the TUSB2040A supports four modes of power
management: bus-powered hub with either individual port power management, or ganged port power
management and the self-powered hub with either individual port power management, or ganged port power
management. Texas Instruments supplies the complete hub solution because we offer this TUSB2040A, the
TUSB2070 (7–port) and the TUSB2140A (4-port with I2C) hubs along with the power management chips
needed to implement a fully USB Specification 1.0 compliant system.
8
POST OFFICE BOX 655303
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TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
APPLICATION INFORMATION
USB design notes
The following sections provide block diagram examples of how to implement the TUSB2040A device. Please
note, even though no resistors are shown, pull-up, pull-down and series resistors must still be used to properly
implement this device. Figure 1 shows a few resistors that must be used for the USB lines, and for a general
reference design, one is available on the TI USB web site.
Figure 6 is a block diagram example of how to connect the external EEPROM if configurable Product ID and
Vendor ID are desired. Please note that the pin numbers in Figure 6 are for the DIP package.
Figure 7 and 8 are examples of how to generate the 48-MHz clock signal. Figure 9 shows the EEPROM Read
Operation Timing Diagram. Figures 10, 11 and 12 illustrate how to connect the TUSB2040A device for different
power source and port power management combinations.
TUSB2040A USB Hub
48-MHz Clock
Signal†
5 V GND
23
XTAL1
13, 27
22
VCC
XTAL2
Bus or Local Power
Regulator
3.3 V
18
System
Power-On Reset
RESET
GND
6, 24
21
EXTMEM
4
5
EEPROM
6
D
ORG
DM0
1 kΩ
8
5
VCC
Q
VSS
C
SDA
OVRCUR1 –
OVRCUR4
SCL
PWRON1 –
PWRON4
9
4
4
8, 12, 15, 17
4
3, 1, 26, 19
4
DM1 – DM4
10
3
7, 11, 14, 16
DP1 – DP4
DP0
2, 28, 25, 20
Power
Switching
4
GND
USB Data lines
and Power to
Downstream
Ports
Vbus
2
S
1
† Figures 7 and 8 are two examples of how to generate the 48-MHz clock signal.
‡ Pin numbers shown are for the N package.
Figure 6. Typical Application of the TUSB2040 USB Hub
Ceralock
Resonator
XTAL1
220 Ω
XTAL2
NOTE A: A simple way to achieve the required 48-MHz clock signal is to use a resonator such as the Ceralock resonator in Figure 7.
MuRata Electronics, Inc. manufactures a surface mount version, P/N CSACV48.00MXJ040, and a dip version, P/N
CSA48.00MXZ040. The 220 Ω resistor is used to tune the 48-MHz signal. The circuit functions properly without the capacitors,
but in order to decrease EMI emissions, the capacitors are used to decrease the amplitude of the signal. The exact values of the
capacitors are dependent on the capacitance of the board layout. Increasing the capacitance decreases the amplitude of the clock
signal. For the 4-layer PCB tested, 22 pF capacitors were used. If the capacitors are too large, the amplitude of the clock signal
will not be large enough for the successful numeration of the TUSB2040A by the USB host.
Figure 7. Resonator Clock Circuit
Ceralock is a trademark of MuRata Electronics Incorporated
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9
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
APPLICATION INFORMATION
R70
2.2 kΩ
XTAL2
XTAL1
Y1
C66
47 pF
C68
1000 pF
5.6 µH
L1
C67
12 pF
NOTE B: This application shows a third harmonic 48-Mhz crystal, P/N HC-18/U 48-MHz, manufactured by US Crystal, Inc. Since the first
harmonic of most crystals is not 48-MHz, a tuning circuit such as this must be used to tune the crystal to the required 48-MHz clock
signal. When tuning the crystal (Y1) for different board implementations, the capacitor (C67) and the resistor (R70) are subject to
change and the other components should remain the same.
Figure 8. Crystal Tuning Circuit
programming the EEPROM
An SGS Thompson M93C46 EEPROM or equivalent is used for storing the programmable VID and PID. When
the EEPROM interface is enabled (EXTMEM = 1), the SCL and SDA are internally pulled down (100 µA) inside
the TUSB2040A. However, in low-power suspend mode, the BUSPWR/SCL pin must be externally pulled down
because the internal pulldowns are disabled. The internal pulldowns are also disabled when the EEPROM
interface is disabled (EXTMEM = 0).
The EEPROM is programmed with the three 16-bit locations as shown in Table 1. Connecting pin 6 of the
EEPROM high (ORG = 1) organizes the EEPROM memory into 64×16 bit words.
Table 1. EEPROM Memory Map
ADDRESS
D15
D14
D13
D12–D8
D7–D0
00000
0
GANGED
BUSPWR
00000
00000000
00001
VID High-byte
00010
PID High-byte
VID Low-byte
PID Low-byte
XXXXXXXX
The D and Q signals of the EEPROM must be tied together using a 1 kΩ resistor with the common I/O operations
forming a single-wire bus. After system power-on reset, the TUSB2040A performs a one-time access read
operation from the EEPROM if the EXTMEM pin is pulled high and the chip select of the EEPROM is connected
to the system power-on reset. Initially, the SDA pin will be driven by the TUSB2040A to send a start bit (1) which
is followed by the read instruction (10) and the starting-word address (00000). Once the read instruction is
received, the instruction and address are decoded by the EEPROM, which then sends the data to the output
shift register. At this point, the hub stops driving the SDA pin and the EEPROM starts driving. A dummy (0) bit
is then output and the first three 16-bit words in the EEPROM are output with the most significant bit (MSB) first.
The output data changes are triggered by the rising edge of the clock provided by the TUSB2040A on the SCL
pin. The SGS-Thompson M936C46 EEPROM is recommended because it advances to the next memory
location by automatically incrementing the address internally. Any EEPROM used must have the automatic
internal address advance function. After reading the three words of data from the EEPROM, the TUSB2040A
puts the EEPROM interface into a high-impedance condition (pulled down internally) to allow other logic to share
the EEPROM. The EEPROM read operation is summarized in Figure 9. For more details on EEPROM
operation, refer to SGS-Thompson Microelectronics M93C46 Serial Microwire Bus EEPROM data sheet.
10
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D
C
S
Start
A5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Other
Address
Bits
A1
6 Bit Address (000000)
A0
Dummy
Bit
MSB of The
First Word
D15
Other
LSB of
Data Bits Third Word
D0
EEPROM Driving Data Line
D14
48 Data Bits
Figure 9. EEPROM Read Operation Timing Diagram
Hub Driving Data Line
Read OP Code(10)
MSB of
Fourth Word
XX
Don’t Care
TRI-STATED
With Internal
Pull Down
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH EEPROM INTERFACE
SLLS288B – FEBRUARY 1998 – REVISED MARCH 1998
11
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – JANUARY 1998 – REVISED MARCH 1998
APPLICATION INFORMATION
bus-powered hub, ganged port power management
A bus-powered TUSB2040A supports up to four downstream ports and is capable of supplying 100 mA of
current for low-power device class functions to each downstream port. Bus-powered hubs must implement
power switching. Ganged power management (see Figure 10) utilizes the TPS2014 power switch device and
provides overcurrent protection for downstream ports. Individual SN75240 transient suppressors reduce
in-rush current and voltage spikes. The TPS7133 low-dropout voltage regulator provides a power good (PG)
signal for reset at power up. OVRCUR1 – OVRCUR4 inputs can be tied together for ganged mode operation.
TUSB2040A
BUSPWR/SCL
Upstream
Port
D+
D–
SN75240†
DP0
GANGED/SDA
DP1
DM0
DM1
A C
B D
4.7 µF
0.1 µF
GND
D+
A C
B D
DM2
D–
GND
5V
120 µF§
DP3
5V
3.3 V
Ferrite Beads
SN75240†
DP2
TPS7133†
5V
Downstream
Ports
3.3 V
4.7 µF
VCC
DM3
GND
A C
B D
PG
SN75240†
D+
D–
Ferrite Beads
GND
DP4
XTAL1
48-MHz Clock
Signal‡
DM4
PWRON1
XTAL2
5V
TPS2014†
EN
IN
1 µF
PWRON2
PWRON3
120 µF§
OC OUT
D+
PWRON4
D–
Ferrite Beads
EXTMEM
GND
OVRCUR1
RESET
5V
OVRCUR2
OVRCUR3
OVRCUR4
120 µF§
GND
D+
Ferrite Beads
D–
GND
5V
† TPS2014, TPS7133, and SN75240 are Texas Instruments devices.
‡ See Figures 7 and 8.
§ Minimum value required per USB specification, version 1.0.
120 µF§
Figure 10. TUSB2040A Bus-Powered Hub, Ganged Port Power Management Application
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – JANUARY 1998 – REVISED MARCH 1998
APPLICATION INFORMATION
self-powered hub, ganged port power management
A self-powered TUSB2040A can also be implemented using ganged port power management (see Figure 11).
This implementation is similar to the individual power management except one TPS2015 provides power
switching and overcurrent protection for two ports. Although this is a more economical solution, a fault on one
downstream port causes power to be removed from both downstream ports.
TUSB2040A
Upstream
Port
D+
D–
SN75240†
DP0
BUSPWR/SCL
DM0
GANGED/SDA
Downstream
Ports
DP1
A C
B D
5V
3.3 V
D+
D–
DM1
TPS7133†
4.7 µF
0.1 µF
GND
5V
3.3 V
Ferrite Beads
A C
B D
4.7 µF
VCC
DP2
GND
GND
SN75240†
5V
DM2
PG
120 µF§
DP3
DM3
A C
B D
XTAL1
48-MHz Clock
Signal‡
D+
SN75240†
DP4
D–
Ferrite Beads
GND
DM4
XTAL2
5V
120 µF§
TPS2015†
PWRON1
EN
EXTMEM
IN
D+
0.1 µF
RESET
GND
PWRON2
NC
PWRON3
NC
PWRON4
NC
D–
Ferrite Beads
OC OUT
GND
5V
120 µF§
OVRCUR1
OVRCUR2
OVRCUR3
OVRCUR4
D+
TPS2015†
EN
D–
Ferrite Beads
IN
GND
0.1 µF
5V
OC OUT
120 µF§
† TPS2015, TPS7133, and SN75240 are Texas Instruments devices.
‡ See Figures 7 and 8.
§ Minimum value required per USB specification, version 1.0.
5 V Board Power
Supply
Figure 11. TUSB2040A Self-Powered Hub, Ganged Port Power Management
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – JANUARY 1998 – REVISED MARCH 1998
APPLICATION INFORMATION
self-powered hub, individual port power management
A self-powered TUSB2040A is capable of supplying 500 mA of current for low-power or high-power device class
functions to each downstream port. Self-powered hubs are required to implement overcurrent protection.
Individual port-power management (see Figure 12) utilizes the TPS2014 power switching and overcurrent
protection that provide maximum robustness to the hub system. When the hub detects a downstream port fault,
power is removed from the faulty port only, thus allowing other ports to continue normal operation. Individual
SN75240 transient suppressors reduce in-rush current and voltage spikes. The TPS7133 low-dropout regulator
provides a power good (PG) signal for reset at power up.
TUSB2040A
Upstream
Port
Downstream
Ports
BUSPWR/SCL
DP0
D+
D–
3.3 V
DM0
SN75240†
0.1 µF
DM2
5V
3.3 V
4.7 µF
VCC
5V
120 µF§
DP3
DM3
GND
PG
GND
GND
SN75240†
DP2
TPS7133†
4.7 µF
D–
A C
B D
GANGED/SDA
A C
B D
5V
D+
DP1
DM1
D+
A C
B D
D–
SN75240†
GND
DP4
DM4
5V
TPS2014†
PWRON1
EN
IN
0.1 µF
XTAL1
48-MHz Clock
Signal‡
120 µF§
OC OUT
XTAL2
D+
PWRON2
PWRON3
PWRON4
D–
TPS2014†
EN
IN
GND
0.1 µF
EXTMEM
5V
OC OUT
OVRCUR1
OVRCUR2
RESET
120 µF§
TPS2014†
EN
IN
D+
0.1 µF
GND
OVRCUR3
OVRCUR4
D–
OC OUT
GND
TPS2014†
EN
5V
IN
0.1 µF
120 µF§
OC OUT
† TPS2014, TPS7133, and SN75240 are Texas Instruments devices.
‡ See Figures 7 and 8.
§ Minimum value required per USB specification, version 1.0.
5-V Board Power
Supply
Figure 12. TUSB2040A Self-Powered Hub, Individual Port-Power Management Application
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – JANUARY 1998 – REVISED MARCH 1998
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.610 (15,49)
0.590 (14,99)
0.020 (0,51) MIN
Seating Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.125 (3,18) MIN
0.010 (0,25) M
PINS **
0°– 15°
0.010 (0,25) NOM
24
28
32
40
48
52
A MAX
1.270
(32,26)
1.450
(36,83)
1.650
(41,91)
2.090
(53,09)
2.450
(62,23)
2.650
(67,31)
A MIN
1.230
(31,24)
1.410
(35,81)
1.610
(40,89)
2.040
(51,82)
2.390
(60,71)
2.590
(65,79)
DIM
4040053 / B 04/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MS-011
Falls within JEDEC MS-015 (32-pin only)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TUSB2040A
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS288B – JANUARY 1998 – REVISED MARCH 1998
MECHANICAL DATA
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
1,60 MAX
0°– 7°
0,75
0,45
0,10
4040052 / C 11/96
NOTES: A.
B.
C.
D.
16
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
This may also be a thermally enhanced plastic package with leads conected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current and complete.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright  1998, Texas Instruments Incorporated