TI TUSB2046BVFR

 SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
D Universal Serial Bus (USB) Version 1.1
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
SUSPND
TSTMODE
XTAL1
XTAL2
GND
TSTPLL/48MCLK
EXTMEM
VCC
D
D
D
VF PACKAGE
(TOP VIEW)
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
17
8
DP4
DM4
OVRCUR4
PWRON4
DP3
DM3
OVRCUR3
PWRON3
9 10 11 12 13 14 15 16
PWRON1
OVRCUR1
DM1
DP1
PWRON2
OVRCUR2
DM2
DP2
D
Compliant
32-Terminal LQFP† Package With a 0.8-mm
Terminal Pitch
3.3-V Low Power ASIC Logic
Integrated USB Transceivers
State Machine Implementation Requires No
Firmware Programming
One Upstream Port and Four Downstream
DP0
Ports
DM0
All Downstream Ports Support Full-Speed
VCC
and Low-Speed Operations
RESET
Two Power Source Modes
EECLK
− Self-Powered Mode
EEDATA/GANGED
− Bus-Powered Mode
GND
BUSPWR
Power Switching and Overcurrent
Reporting Is Provided Ganged or Per Port
Supports Suspend and Resume Operations
Supports Programmable Vendor ID and
Product ID With External Serial EEPROM
3-State EEPROM Interface Allows EEPROM
Sharing
Push-Pull Outputs for PWRON Eliminate
the Need for External Pullup Resistors
Noise Filtering on OVRCUR Provides
Immunity to Voltage Spikes
Package Pinout Allows 2-Layer PCB
Low EMI Emission Achieved by a 6-MHz
Crystal Input
Migrated From Proven TUSB2040 Hub
Lower Cost Than the TUSB2040 Hub
Enhanced System ESD Performance
Supports 6-MHz Operation Through a
Crystal Input or a 48-MHz Input Clock
description
The TUSB2046B is a 3.3-V CMOS hub device that provides one upstream port and four downstream ports in
compliance with the 1.1 Universal Serial Bus (USB) specification. Because this device is implemented with a
digital state machine instead of a microcontroller, no firmware programming is required. Fully-compliant USB
transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support
both full-speed and low-speed devices by automatically setting the slew rate according to the speed of the
device attached to the ports. The configuration of the BUSPWR terminal selects either the bus-powered or the
self-powered mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†JEDEC descriptor S-PQFP-G for low profile quad flat pack (LQFP).
Copyright  2004, Texas Instruments Incorporated
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1
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
description (continued)
Configuring the GANGED input determines the power switching and overcurrent detection modes for the
downstream ports. External power-management devices, such as the TPS2044, are required to control the 5-V
source to the downstream ports according to the corresponding values of the PWRON terminal. Upon detecting
any overcurrent conditions, the power-management device sets the corresponding OVRCUR terminal of the
TUSB2046B to a logic low. If GANGED is high, all PWRON outputs switch together and if any OVRCUR is
activated, all ports transition to the power-off state. If GANGED is low, the PWRON outputs and OVRCUR inputs
operate on a per-port basis.
The TUSB2046B provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the TSTMODE
terminal controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL
circuitry is selected to drive the internal core of the device. When TSTMODE is high, the TSTPLL/48MCLK input
is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal
oscillator cell is also powered down while TSTMODE is high.
Low EMI emission is achieved because the TUSB2046B is able to utilize a 6-MHz crystal input. Connect the
crystal as shown in Figure 6. An internal PLL then generates the 48-MHz clock used to sample data from the
upstream port and to synchronize the 12 MHz used for the USB clock. If low-power suspend and resume are
desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting
the output to the XTAL1 terminal and leaving the XTAL2 terminal open. The oscillator TTL output must not
exceed 3.6 V.
For 48-MHz operation, the clock can not be generated with a crystal, using the XTAL2 output, since the internal
oscillator cell only supports the fundamental frequency.
Refer to Figure 7 and Figure 8 in the input clock configuration section for more detailed information regarding
the input clock configuration.
The EXTMEM terminal enables or disables the optional EEPROM interface. When the EXTMEM terminal is
high, the product ID (PID) displayed during enumeration is the general-purpose USB hub. For this default,
terminal 5 is disabled and terminal 6 functions as the GANGED input terminal. If custom PID and vendor ID (VID)
descriptors are desired, the EXTMEM terminal must be low (EXTMEM = 0). For this configuration, terminals
5 and 6 function as the EEPROM interface with terminals 5 and 6 functioning as EECLK and EEDATA,
respectively. See Table 1 for a description of the EEPROM memory map.
Other useful features of the TUSB2046B include a package with a 0.8-mm terminal pitch for easy PCB routing
and assembly, push-pull outputs for the PWRON terminals eliminate the need for pullup resistors required by
traditional open collector I/Os, and OVRCUR terminals have noise filtering for increased immunity to voltage
spikes.
2
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SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
functional block diagram
DP0
1
DM0
2
USB
Transceiver
32
27
30
29
Suspend / Resume
Logic and
Frame Timer
Hub Repeater
OSC/PLL
SUSPND
TSTPLL/48MCLK
XTAL1
XTAL2
SIE
4
RESET
26
6
SIE Interface
Logic
Serial
EEPROM
Interface
5
EXTMEM
EEDATA/GANGED
EECLK
Port 1
Logic
Port 2
Logic
Hub / Device
Command
Decoder
Port 3
Logic
8
Port 4
Logic
USB
Transceiver
24
23
USB
Transceiver
20
19
USB
Transceiver
16
15
USB
Transceiver
12
Hub
Power
Logic
10, 14, 18, 22
11
9, 13, 17, 21
DP4
DM4
DP3
DM3
DP2 DM2
DP1
DM1
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BUSPWR
OVRCUR1 − OVRCUR4
PWRON1 − PWRON4
3
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Power source indicator. BUSPWR is an active-high input that indicates whether the downstream ports
source their power from the USB cable or a local power supply. For the bus-power mode, this terminal must
be pulled to 3.3 V, and for the self-powered mode, this terminal must be pulled low. Input must not change
dynamically during operation.
BUSPWR
8
I
DM0
2
I/O
Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
11, 15,
19, 23
I/O
USB differential data minus. DM1 − DM4 paired with DP1 − DP4 support up to four downstream USB ports.
DM1 − DM4
DP0
1
I/O
Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
12, 16,
20, 24
I/O
USB differential data plus. DP1 − DP4 paired with DM1 − DM4 support up to four downstream USB ports.
EECLK
5
O
EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK terminal
is disabled and must be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state serial
clock output to the EEPROM with a 100-µA internal pulldown.
EEDATA/
GANGED
6
I/O
EEPROM serial data/power-management mode indicator. When EXTMEM is high, EEDATA/GANGED
selects between ganged or per-port power overcurrent detection for the downstream ports. When
EXTMEM is low, EEDATA/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down
with a 100-µA pulldown. This standard TTL input must not change dynamically during operation.
EXTMEM
26
I
EEPROM read enable. When EXTMEM is high, the serial EEPROM interface of the device is disabled.
When EXTMEM is low, terminals 5 and 6 are configured as the clock and data terminals of the serial
EEPROM interface, respectively.
DP1 − DP4
GND
7, 28
Ground. GND terminals must be tied to ground for proper operation.
OVRCUR1 −
OVRCUR4
10, 14,
18, 22
I
Overcurrent input. OVRCUR1 − OVRCUR4 are active low. For per-port overcurrent detection, one
overcurrent input is available for each of the four downstream ports. In the ganged mode, any OVRCUR
input may be used and all OVRCUR terminals must be tied together. OVRCUR terminals are active low
inputs with noise filtering logic.
PWRON1 −
PWRON4
9, 13,
17, 21
O
Power-on/-off control signals. PWRON1 − PWRON4 are active low, push-pull outputs. Push-pull outputs
eliminate the pullup resistors which open-drain outputs require. However, the external power switches that
connect to these terminals must be able to operate with 3.3-V inputs because these outputs cannot drive
5-V signals.
RESET
4
I
Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET
is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 µs and 1 ms is
recommended after 3.3-V VCC reaches its 90%. Clock signal has to be active during the last 60 µs of the
reset window.
SUSPND
32
O
Suspend status. SUSPND is an active high output available for external logic power-down operations.
During the suspend mode, SUSPND is high. SUSPND is low for normal operation.
TSTMODE
31
I
Test/mode terminal. TSTMODE is used as a test terminal during production testing. This terminal must
be tied to ground or 3.3-V VCC for normal 6-MHz or 48-MHz operation, respectively.
TSTPLL/
48MCLK
27
I/O
Test/48-MHz clock input. TSTPLL/48MCLK is used as a test terminal during production testing. This
terminal must be tied to ground for normal 6-MHz operation. If 48-MHz input clock is desired, a 48-MHz
clock source (no crystal) can be connected to this input terminal.
VCC
XTAL1
3, 25
30
I
Crystal 1. XTAL1 is a 6-MHz crystal input with 50% duty cycle. An internal PLL generates the 48-MHz and
12-MHz clocks used internally by the ASIC logic.
XTAL2
29
O
Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal must be left open when using an oscillator.
4
3.3-V supply voltage
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SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK, (VI < 0 V or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK, (VO < 0 V or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Operating free-air temperature range, TA, TUSB2046B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TUSB2046BI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.
recommended operating conditions
MIN
NOM
TUSB2046B
3
3.3
TUSB2046BI
3.3
3.6
Input voltage, TTL/LVCMOS, VI
0
0
VCC
VCC
V
Output voltage, TTL/LVCMOS, VO
High-level input voltage, signal-ended receiver, VIH(REC)
2
VCC
0.8
V
2
V
Supply voltage, VCC
Low-level input voltage, signal-ended receiver, VIL(REC)
High-level input voltage, TTL/LVCMOS, VIH(TTL)
UNIT
3.6
V
V
V
0
VCC
0.8
TUSB2046B
0
70
TUSB2046BI
−40
85
22 (−5%)
22 (5%)
Ω
12
Mb/s
1.5
Mb/s
2.5
V
Low-level input voltage, TTL/LVCMOS, VIL(TTL)
Operating free-air temperature, TA
MAX
External series, differential driver resistor, R(DRV)
Operating (dc differential driver) high speed mode, f(OPRH)
Operating (dc differential driver) low speed mode, f(OPRL)
Common mode, input range, differential receiver, V(ICR)
0.8
V
°C
Input transition times, tt, TTL/LVCMOS
0
25
ns
Junction temperature range, TJ
0
115
°C
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5
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TTL/LVCMOS
VOH
High-level output voltage
USB data lines
TTL /LVCMOS
VOL
Low-level output voltage
USB data lines
MIN
MAX
IOH = −4 mA
R(DRV) = 15 kΩ, to GND
VCC − 0.5
2.8
IOH = − 12 mA (without R(DRV))
IOL = 4 mA
VCC − 0.5
Positive input threshold voltage
VIT−
Negative-input threshold voltage
Single-ended
0.5
0.3
IOL = 12 mA (without R(DRV))
0.5
0.8 V ≤ VICR ≤ 2.5 V
TTL /LVCMOS
Vhys
Input hysteresis† (VT+ − VT−)
Single-ended
0.8 V ≤ VICR ≤ 2.5 V
V = VCC or GND‡
V
300
High-impedance output current
USB data lines
0 V ≤ VO ≤ VCC
IIL
IIH
Low-level input current
TTL/LVCMOS
High-level input current
TTL/LVCMOS
VI = GND
VI = VCC
zo(DRV)
Driver output impedance
USB data lines
Static VOH or VOL
7.1
VID
Differential input voltage
USB data lines
0.8 V ≤ VICR ≤ 2.5 V
0.2
0.7
V
500
mV
± 10
µA
± 10
µA
−1
µA
1
µA
19.9
Ω
V
Normal operation
Input supply current
V
V
IOZ
ICC
V
1.8
1
0.3
TTL/LVCMOS
V
1.8
0.8
0.8 V ≤ VICR ≤ 2.5 V
TTL /LVCMOS
Single-ended
V
R(DRV) = 1.5 kΩ to 3.6 V
TTL /LVCMOS
VIT+
UNIT
Suspend mode
40
mA
1
µA
† Applies for input buffers with hysteresis
‡ Applies for open drain buffers
differential driver switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 50 pF (unless otherwise noted)
full speed mode
PARAMETER
tr
tf
t(RFM)
VO(CRS)
TEST CONDITIONS
Transition rise time for DP or DM
See Figure 1 and Figure 2
Transition fall time for DP or DM
Rise/fall time matching§
See Figure 1 and Figure 2
(tr/tf) × 100
Signal crossover output voltage§
MIN
MAX
4
20
UNIT
ns
ns
4
20
90%
110%
1.3
2.0
MIN
MAX
UNIT
75
300
ns
ns
V
§ Characterized only. Limits are approved by design and are not production tested.
low speed mode
PARAMETER
TEST CONDITIONS
tr
tf
Transition rise time for DP or DM§
Transition fall time for DP or DM§
CL = 200 pF to 600 pF,
See Figure 1 and Figure 2
CL = 200 pF to 600 pF,
See Figure 1 and Figure 2
t(RFM)
VO(CRS)
Rise/fall time matching§
(tr/tf) × 100
CL = 200 pF to 600 pF
Signal crossover output voltage§
§ Characterized only. Limits are approved by design and are not production tested.
6
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75
300
80%
120%
1.3
2.0
V
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
Characterization
measurement point
DP
V(TERM) = VCC
22 Ω
Full
15 kΩ
DM
1.5 kΩ
CL
22 Ω
Low
15 kΩ
CL
Figure 1. Differential Driver Switching Load
tf
DM
90%
10%
90%
10%
DP
tf
90%
10%
VOH
90%
10%
tr
VOL
tr
NOTE: The tr/tf ratio is measured as tr(DP)/tf(DM) and tr(DM)/tf(DP) at each crossover point.
Figure 2. Differential Driver Timing Waveforms
V ID − Differential Receiver Input Sensitivity − V
1.5
1.3
1
0.5
0.2
0
0
3
1
2
3.6
0.8
2.5
VICR − Common Mode Input Range − V
4
Figure 3. Differential Receiver Input Sensitivity vs Common Mode Input Range
Vhys
Logic high
VCC
VIH
VIT+
VIT−
VIL
Logic low
0V
Figure 4. Single-Ended Receiver Input Signal Parameter Definitions
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SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
A major advantage of USB is the ability to connect 127 functions configured in up to 6 logical layers (tiers) to
a single personal computer (see Figure 5).
PC
With Root Hub
Monitor
With 4-Port Hub (Self-Powered)
Keyboard
With 4-Port Hub
(Bus-Powered)
Left
Speaker
Mouse
Modem
Telephone
Right
Speaker
Printer
With 4-Port Hub
(Self-Powered)
Scanner
Digital
Scanner
Figure 5. USB-Tiered Configuration Example
Another advantage of USB is that all peripherals are connected using a standardized four-wire cable that
provides both communication and power distribution. The power configurations are bus-powered and
self-powered modes. The maximum current that may be drawn from the USB 5-V line during power up is
100 mA. For the bus-powered mode, a hub can draw a maximum of 500 mA from the 5-V line of the USB cable.
A bus-powered hub must always be connected downstream to a self-powered hub unless it is the only hub
connected to the PC and there are no high-powered functions connected downstream. In the self-powered
mode, the hub is connected to an external power supply and can supply up to 500 mA to each downstream port.
High-powered functions may draw a maximum of 500 mA from each downstream port and may only be
connected downstream to self-powered hubs. Per the USB specification, in the bus-powered mode, each
downstream port can provide a maximum of 100 mA of current, and in the self-powered mode, each
downstream port can provide a maximum of 500 mA of current.
Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two
types of protection are individual-port management (individual-port basis) or ganged-port management
(multiple-port basis). Individual-port management requires power-management devices for each individual
downstream port, but adds robustness to the USB system because, in the event of an overcurrent condition,
the USB host only powers down the port that has the condition. The ganged configuration uses fewer power
management devices and thus has lower system costs, but in the event of an overcurrent condition on any of
the downstream ports, all the ganged ports are disabled by the USB host.
Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2046B supports four modes of
power management: bus-powered hub with either individual-port power management or ganged-port power
management, and the self-powered hub with either individual-port power management or ganged-port power
management. Texas Instruments supplies the complete hub solution because we offer this TUSB2046B, the
TUSB2077 (7-port), and the TUSB2140B (4-port with I2C) hubs along with the power-management devices
needed to implement a fully USB Specification 1.1-compliant system.
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APPLICATION INFORMATION
USB design notes
The following sections provide block diagram examples of how to implement the TUSB2046B device. Note,
even though no resistors are shown, pullup, pulldown, and series resistors must be used to properly implement
this device.
Figure 6 is an example of how to generate the 6 MHz clock signal.
CL
XTAL1
XTAL2
Rd
C1
C2
NOTE A: Figure 6 assumes a 6-MHz fundamental crystal that is parallel loaded. The component values of C1, C2, and Rd are determined using
a crystal from Fox Electronics − part number HC49U−6.00MHz30\50\0 ±70\20 which means ±30 ppm at 25°C and 50 ppm from 0°C
to 70°C. The characteristics for the crystal include a load capacitance (CL) of 20 pF, maximum shunt capacitance (Co) of 7 pF, and
the maximum ESR of 50 Ω. In order to insure enough negative resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the
gain, and Rd = 1.5 kΩ Figure 6. Crystal Tuning Circuit
input clock configuration
The input clock configuration logic of TUSB2046B is enhanced to accept a 6-MHz crystal or 48-MHz
on-the-board clock source with a simple tie-off change on TSTMODE (terminal 31).
D A 6-MHz input clock configuration is shown in Figure 7.
In this mode, both TSTMODE and TSTPLL/48MCLK terminals must be tied to ground. The hub is configured
to use the 6-MHz clock on terminals 30 and 29, which are XTAL1 and XTAL2, respectively, on the
TUSB2046B. This is identical to the TUSB2046.
TUSB2046B USB HUB
6-MHz
Clock Signal
30
XTAL1
29
XTAL2
31
TSTMODE
27
TSTPLL/48MCLK
Figure 7. 6-MHz Input Clock Configuration
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SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
input clock configuration (continued)
D A 48-MHz input clock configuration is shown in Figure 8.
In this mode, both TSTMODE and XTAL1 terminals must be tied to 3.3-V VCC. The hub accepts the 48-MHz
clock input on TSTPLL/48MCLK (terminal 27). XTAL2 must be left floating (open) for this configuration. Only
the oscillator or the onboard clock source is accepted for this mode. A crystal can not be used for this mode,
since the chip’s internal oscillator cell only supports the fundamental frequency.
TUSB2046B USB HUB
3.3 V
30
XTAL1
29
Open
XTAL2
31
TSTMODE
48-MHz Oscillator
or on Board Clock Source 27
TSTPLL/48MCLK
Figure 8. 48-MHz Input Clock Configuration
Figure 9 is a block diagram example of how to connect the external EEPROM if a custom product ID and vendor
ID are desired.
Figure 10 shows the EEPROM read operation timing diagram. Figures 11, 12, and 13 illustrate how to connect
the TUSB2046B device for different power source and port power-management combinations.
TUSB2046B USB Hub
6-MHz Clock
Signal
Bus or Local Power
5 V GND
30
XTAL1
3, 25
29
VCC
XTAL2
Regulator
3.3 V
System
Power-On Reset
4
RESET
GND
7, 28
26
EXTMEM
1
DP0
2
EEPROM
6
D
ORG
DM0
EEDATA
1 kΩ
8
5
VCC
Q
VSS
C
4
4
11, 15, 19, 23
4
10, 14, 18, 22
4
DM1 − DM4
6
3
12, 16, 20, 24
DP1 − DP4
5
EECLK
OVRCUR1 −
OVRCUR4
PWRON1 −
PWRON4
9, 13, 17, 21
Power
Switching
2
S
1
Figure 9. Typical Application of the TUSB2046B USB Hub
10
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4
GND
Vbus
USB Data lines
and Power to
Downstream
Ports
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
programming the EEPROM
An SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID and PID. When the
EEPROM interface is enabled (EXTMEM = 0), the EECLK and EEDATA are internally pulled down (100 µA)
inside the TUSB2046B. The internal pulldowns are disabled when the EEPROM interface is disabled
(EXTMEM = 1).
The EEPROM is programmed with the three 16-bit locations as shown in Table 1. Connecting terminal 6 of the
EEPROM high (ORG = 1) organizes the EEPROM memory into 64×16-bit words.
Table 1. EEPROM Memory Map
ADDRESS
D15
D14
D13
D12−D8
D7−D0
00000
0
GANGED
00000
00000
00000000
00001
VID High-byte
VID Low-byte
00010
PID High-byte
PID Low-byte
XXXXXXXX
The D and Q signals of the EEPROM must be tied together using a 1-kΩ resistor with the common I/O operations
forming a single-wire bus. After system power-on reset, the TUSB2046B performs a one-time access read
operation from the EEPROM if the EXTMEM terminal is pulled low and the chip select(s) of the EEPROM is
connected to the system power-on reset. Initially, the EEDATA terminal is driven by the TUSB2046B to send
a start bit (1) which is followed by the read instruction (10) and the starting-word address (00000). Once the read
instruction is received, the instruction and address are decoded by the EEPROM, which then sends the data
to the output shift register. At this point, the hub stops driving the EEDATA terminal and the EEPROM starts
driving. A dummy (0) bit is then output and the first three 16-bit words in the EEPROM are output with the most
significant bit (MSB) first.
The output data changes are triggered by the rising edge of the clock provided by the TUSB2046B on the EECLK
terminal. The SGS-Thompson M936C46 EEPROM is recommended because it advances to the next memory
location by automatically incrementing the address internally. Any EEPROM used must have the automatic
internal address advance function. After reading the three words of data from the EEPROM, the TUSB2046B
puts the EEPROM interface into a high-impedance condition (pulled down internally) to allow other logic to share
the EEPROM. The EEPROM read operation is summarized in Figure 10. For more details on EEPROM
operation, refer to SGS-Thompson Microelectronics M93C46 Serial Microwire Bus EEPROM data sheet.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
12
POST OFFICE BOX 655303
D
C
S
Start
• DALLAS, TEXAS 75265
A5
Other
Address
Bits
A1
6 Bit Address (000000)
A0
Dummy
Bit
MSB of The
First Word
D15
Other
LSB of
Data Bits Third Word
D0
EEPROM Driving Data Line
D14
48 Data Bits
Figure 10. EEPROM Read Operation Timing Diagram
Hub Driving Data Line
Read OP Code(10)
MSB of
Fourth Word
XX
Don’t Care
3-Stated
With Internal
Pulldown
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
Figure 10.
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
bus-powered hub, ganged-port power management
When used in bus-powered mode, the TUSB2046B supports up to four downstream ports by controlling a
TPS2041 device which is capable of supplying 100 mA of current to each downstream port. Bus-powered hubs
must implement power switching to ensure current demand is held below 100 mA when the hub is hot-plugged
into the system. Utilizing the TPS2041 for ganged-port power management provides overcurrent protection for
the downstream ports. The SN75240 transient suppressors reduce inrush current and voltage spikes on the
data lines. The OVRCUR signals must be tied together for a ganged operation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
bus-powered hub, ganged-port power management (continued)
3.3 V
TUSB2046B
BUSPWR
3.3 V
EEDATA/GANGED
Upstream
Port
1.5 kΩ
¶
DP1
DP0
D+
D−
DM0
SN75240†
A C
B D
4.7 µF
0.1 µF
GND
D+
DM1
A C
B D
15 kΩ
15 kΩ
Ferrite Beads
DP2
D−
GND
SN75240†
DM2
3.3 V LDO§
5V
Downstream
Ports
5V
100 µF‡
15 kΩ
15 kΩ
5V
3.3 V
4.7 µF
VCC
GND
D+
D−
DP3
Ferrite Beads
DM3
GND
A C
B D
15 kΩ
15 kΩ
XTAL1
5V
SN75240†
6-MHz Clock
Signal
DP4
100 µF‡
DM4
XTAL2
3.3 V
15 kΩ
15 kΩ
EN
PWRON2
RESET
D−
TPS2041†
EXTMEM
PWRON1
System
Power-On Reset
D+
Ferrite Beads
GND
IN
IN
5V
1 µF
PWRON3
100 µF‡
PWRON4
OUT
OUT
OUT
GND
OVRCUR1
OC
D+
D−
Ferrite Beads
OVRCUR2
GND
OVRCUR3
OVRCUR4
5V
100 µF‡
† TPS2041 and SN75240 are Texas Instruments devices.
‡ 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100-µF, low ESR, tantalum capacitor
per port for immunity to voltage droop.
§ LDO is a 5-V-to-3.3-V voltage regulator
¶ All USB DP, DM signal pairs require series resistors of approximately 27 Ω to ensure proper termination. An optional filter capacitor of about
22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per
section 7.1.6 of the USB specification.
Figure 11. TUSB2046B Bus-Powered Hub, Ganged-Port Power-Management Application
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
self-powered hub, ganged-port power management
The TUSB2046B can also be implemented for ganged-port power management in a self-powered
configuration. The implementation is very similar to the bus-powered example with the exception that a
self-powered port supplies 500 mA of current to each downstream port. The overcurrent protection can be
provided by a TPS2044 quad device or a TPS2024 single power switch.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
self-powered hub, ganged-port power management (continued)
TUSB2046B
3.3 V
EEDATA/GANGED
Upstream
Port
1.5 kΩ
¶
DP1
DM0
SN75240†
Downstream
Ports
BUSPWR
DP0
D+
D−
3.3 V
D+
D−
DM1
15 kΩ
15 kΩ
A C
B D
5V
A C
B D
3.3 V LDO§
4.7 µF
0.1 µF
GND
3.3 V
4.7 µF
GND
SN75240†
DP2
5V
Ferrite Beads
5V
DM2
VCC
100 µF‡
15 kΩ
15 kΩ
GND
D+
DP3
D−
DM3
XTAL1
15 kΩ
15 kΩ
6-MHz Clock
Signal
A C
B D
GND
SN75240†
DP4
XTAL2
Ferrite Beads
5V
DM4
15 kΩ
15 kΩ
100 µF‡
TPS2044†
PWRON1
3.3 V
System
Power-On Reset
EXTMEM
RESET
PWRON2
EN1
EN2
PWRON3
EN3
PWRON4
EN4
OVRCUR1
OVRCUR2
OC1
OC2
OVRCUR3
OC3
OVRCUR4
OC4
D+
IN1
D−
IN2
Ferrite Beads
GND
0.1 µF
5V
GND
100 µF‡
D+
D−
OUT1
OUT2
Ferrite Beads
GND
OUT3
OUT4
5V
100 µF‡
5 V Board Power
† TPS2044, TPS2042, and SN75240 are Texas Instruments devices.
Supply
The TPS2024 can be substituted for the TPS2044.
‡ 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100-µF, low ESR, tantalum capacitor
per port for immunity to voltage droop.
§ LDO is a 5-V-to-3.3-V voltage regulator
¶ All USB DP, DM signal pairs require series resistors of approximately 27 Ω to ensure proper termination. An optional filter capacitor of about
22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per
section 7.1.6 of the USB specification.
Figure 12. TUSB2046B Self-Powered Hub, Ganged-Port Power-Management Application
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
self-powered hub, individual-port power management
In a self-powered configuration, the TUSB2046B can be implemented for individual-port power management
when used with the TPS2044, because it is capable of supplying 500 mA of current to each downstream port
and can provide current limiting on a per-port basis. When the hub detects a fault on a downstream port, power
is removed from only the port with the fault and the remaining ports continue to operate normally. Self-powered
hubs are required to implement overcurrent protection and report overcurrent conditions. The SN75240
transient suppressors reduce inrush current and voltage spikes on the data lines.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
APPLICATION INFORMATION
self-powered hub, individual-port power management (continued)
TUSB2046B
Downstream
Ports
3.3 V
¶
Upstream
Port
DM0
SN75240†
D−
15 kΩ
15 kΩ
BUSPWR
EEDATA/GANGED
A C
B D
5V
D+
DM1
DP0
D+
D−
DP1
1.5 kΩ
0.1 µF
GND
5V
DM2
3.3 V LDO§
100 µF‡
15 kΩ
15 kΩ
5V
3.3 V
4.7 µF
GND
SN75240†
DP2
4.7 µF
A C
B D
VCC
D+
DP3
GND
D−
DM3
A C
B D
GND
SN75240†
5V
15 kΩ
15 kΩ
DP4
DM4
XTAL1
15 kΩ
15 kΩ
6-MHz Clock
Signal
TPS2044†
XTAL2
3.3 V
EXTMEM
100 µF‡
PWRON1
EN1
D+
PWRON2
EN2
D−
PWRON3
EN3
PWRON4
EN4
GND
OUT1
5V
OUT2
System
Power-On Reset
OUT3
RESET
100 µF‡
OUT4
GND
OVRCUR1
OC1
IN1
OVRCUR2
OC2
IN2
OVRCUR3
OC3
OVRCUR4
OC4
D+
D−
GND
0.1 µF
5V
100 µF‡
5-V Board Power
Supply
† TPS2042 and SN75240 are Texas Instruments devices. Two TPS2042 devices can be substituted for the TPS2044.
‡ 120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100-µF, low ESR, tantalum
capacitor per port for immunity to voltage droop.
§ LDO is a 5-V-to-3.3-V voltage regulator
¶ All USB DP, DM signal pairs require series resistors of approximately 27 Ω to ensure proper termination. An optional filter capacitor of about
22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per
section 7.1.6 of the USB specification.
Figure 13. TUSB2046B Self-Powered Hub, Individual-Port Power-Management Application
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLLS413B − FEBRUARY 2000 − REVISED DECEMBER 2004
MECHANICAL DATA
VF (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,45
0,30
0,80
24
0,22 M
17
25
16
32
9
0,13 NOM
1
8
5,60 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
1,60 MAX
0°−ā 7°
0,75
0,45
0,10
4040172 / C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TUSB2046BIVFR
ACTIVE
LQFP
VF
32
1000
None
Call TI
Level-3-220C-168 HR
TUSB2046BVF
ACTIVE
LQFP
VF
32
250
None
CU NIPDAU
Level-3-235C-168 HR
TUSB2046BVFG4
ACTIVE
LQFP
VF
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TUSB2046BVFR
ACTIVE
LQFP
VF
32
1000
None
CU NIPDAU
Level-3-235C-168 HR
TUSB2046BVFRG4
ACTIVE
LQFP
VF
32
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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