TI JL118SPA

LM118JAN
LM118JAN Operational Amplifier
Literature Number: SNOSAM8
LM118JAN
Operational Amplifier
General Description
The LM118 is a precision high speed operational amplifier
designed for applications requiring wide bandwidth and high
slew rate. It features a factor of ten increase in speed over
general purpose devices without sacrificing DC performance.
The LM118 has internal unity gain frequency compensation.
This considerably simplifies its application since no external
components are necessary for operation. However, unlike
most internally compensated amplifiers, external frequency
compensation may be added for optimum performance. For
inverting applications, feed forward compensation will boost
the slew rate to over 150V/µs and almost double the bandwidth. Overcompensation can be used with the amplifier for
greater stability when maximum bandwidth is not needed.
Further, a single capacitor can be added to reduce the 0.1%
settling time to under 1 µs.
The high speed and fast settling time of this op amp makes
it useful in A/D converters, oscillators, active filters, sample
and hold circuits, or general purpose amplifiers. This device
is easy to apply and offers an order of magnitude better AC
performance than industry standards such as the LM709.
Features
n
n
n
n
n
n
n
15 MHz small signal bandwidth
Guaranteed 50V/µs slew rate
Maximum bias current of 250 nA
Operates from supplies of ± 5V to ± 20V
Internal frequency compensation
Input and output overload protected
Pin compatible with general purpose op amps
Ordering Information
NS Part Number
JAN Part Number
NS Package Number
Package Description
JL118BGA
JM38510/10107BGA
H08C
8LD TO-99 Metal Can
JL118BPA
JM38510/10107BPA
J08A
8LD CERDIP
JL118BCA
JM38510/10107BCA
J14A
14LD CERDIP
JL118BHA
JM38510/10107BHA
W10A
10LD CERPACK
JL118SGA
JM38510/10107SGA
H08C
8LD TO-99 Metal Can
JL118SPA
JM38510/10107SPA
J08A
8LD CERDIP
JL118SHA
JM38510/10107SHA
W10A
10LD CERPACK
Fast Voltage Follower
(Note 1)
20141913
Note 1: Do not hard-wire as voltage follower (R1 ≥ 5 kΩ)
© 2005 National Semiconductor Corporation
DS201419
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LM118JAN Operational Amplifier
July 2005
LM118JAN
Connection Diagram
Metal Can Package
(Note 2)
Dual-In-Line Package
20141902
20141924
Top View
See NS Package Number J14A
Top View
See NS Package Number H08C
Dual-In-Line Package
Ceramic Flatpack Package
20141963
Top View
See NS Package Number W10A
20141903
Top View
See NS Package Number J08A
www.national.com
Note 2: Pin connections shown on schematic diagram and typical applications are for TO-5 package.
2
LM118JAN
Schematic Diagram
20141901
3
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LM118JAN
Absolute Maximum Ratings (Note 3)
± 20V
Supply Voltage
Power Dissipation (Note 4)
8 LD Metal Can
750mW
8LD CERDIP
1000mW
14LD CERDIP
1250mW
10LD CERPACK
600mW
± 10 mA
± 15V
Differential Input Current (Note 5)
Input Voltage (Note 6)
Output Short-Circuit Duration
Continuous
Operating Temperature Range
−55˚C ≤ TA ≤ +125˚C
Thermal Resistance
θJA
8 LD Metal Can (Still Air @ 0.5W)
160˚C/W
8 LD Metal Can (500LF / Min Air flow @ 0.5W)
86˚C/W
8LD CERDIP (Still Air @ 0.5W)
120˚C/W
8LD CERDIP (500LF / Min Air flow @ 0.5W)
66˚C/W
14LD CERDIP (Still Air @ 0.5W)
87˚C/W
14LD CERDIP (500LF / Min Air flow @ 0.5W)
51˚C/W
10LD CERPACK (Still Air @ 0.5W)
198˚C/W
10LD CERPACK (500LF / Min Air flow @ 0.5W)
124˚C/W
θJC
8 LD Metal Can
48˚C/W
8LD CERDIP
17˚C/W
14LD CERDIP
17˚C/W
10LD CERPACK
22˚C/W
−65˚C ≤ TA ≤ +150˚C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
300˚C
ESD Tolerance (Note 7)
2000V
Quality Conformance Inspection
Mil-Std-883, Method 5005; Group A
Subgroup
Description
1
Static tests at
25
2
Static tests at
125
3
Static tests at
-55
4
Dynamic tests at
25
5
Dynamic tests at
125
6
Dynamic tests at
-55
7
Functional tests at
25
8A
Functional tests at
125
8B
Functional tests at
-55
9
Switching tests at
25
10
Switching tests at
125
11
Switching tests at
-55
12
Settling time at
25
13
Settling time at
125
14
Settling time at
-55
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4
Temp˚C
LM118JAN
LM118 JAN Electrical Characteristics
DC Parameters
The following conditions apply to all the following parameters, unless otherwise specified.
DC:
VCC = ± 20V
Symbol
VIO
Parameter
Input Offset Voltage
Conditions
Notes
Max
Unit
+VCC = 35V, -VCC = -5V,
VCM = -15V
-4.0
4.0
mV
1
-6.0
6.0
mV
2, 3
+VCC = 5V, -VCC = -35V,
VCM = 15V
-4.0
4.0
mV
1
-6.0
6.0
mV
2, 3
VCM = 0V
+VCC = 5V, -VCC = -5V,
VCM = 0V
IIO
± IIB
Input Offset Current
Input Bias Current
-PSRR
Power Supply Rejection Ratio
Power Supply Rejection Ratio
-4.0
4.0
mV
1
-6.0
6.0
mV
2, 3
-4.0
4.0
mV
1
2, 3
-6.0
6.0
mV
+VCC = 35V, -VCC = -5V,
VCM = -15V, RS = 100KΩ
(Note 11)
-40
40
nA
1
(Note 11)
-80
80
nA
2, 3
+VCC = 5V, -VCC = -35V,
VCM = 15V, RS = 100KΩ
(Note 11)
-40
40
nA
1
(Note 11)
-80
80
nA
2, 3
VCM = 0V, RS = 100KΩ
(Note 11)
-40
40
nA
1
(Note 11)
-80
80
nA
2, 3
+VCC = 5V, -VCC = -5V,
VCM = 0V, RS = 100KΩ
(Note 11)
-40
40
nA
1
(Note 11)
-80
80
nA
2, 3
+VCC = 35V, -VCC = -5V,
VCM = -15V, RS = 100KΩ
(Note 11)
1.0
250
nA
1, 2
(Note 11)
1.0
400
nA
3
+VCC = 5V, -VCC = -35V,
VCM = 15V, RS = 100KΩ
(Note 11)
1.0
250
nA
1, 2
(Note 11)
1.0
400
nA
3
VCM = 0V, RS = 100KΩ
(Note 11)
1.0
250
nA
1, 2
(Note 11)
1.0
400
nA
3
(Note 11)
1.0
250
nA
1, 2
(Note 11)
1.0
400
nA
3
+VCC = 5V, -VCC = -5V,
VCM = 0V, RS = 100KΩ
+PSRR
+VCC = 10V, -VCC = -20V
+VCC = 20V, -VCC = -10V
-100
100
µV/V
1
-150
150
µV/V
2, 3
-100
100
µV/V
1
-150
150
µV/V
2, 3
dB
1, 2, 3
CMRR
Common Mode Rejection Ratio VCM = ± 15V,
VCC = ± 35V to ± 5V
80
+VIO adj.
Offset Null
7.0
-VIO adj.
Offset Null
Delta VIO /
Delta T
Temperature Coefficient of
Input Offset Voltage
25˚C ≤ TA ≤ 125˚C
(Note 9)
-55˚C ≤ TA ≤ 25˚C
(Note 9)
Delta IIO /
Delta T
Temperature Coefficient of
Input Offset Current
25˚C ≤ TA ≤ 125˚C
(Note 9)
-55˚C ≤ TA ≤ 25˚C
(Note 9)
+IOS
Short Circuit Current
+VCC = 15V, -VCC = -15V,
t ≤ 25mS, VCM = -15V
-IOS
Short Circuit Current
+VCC = 15V, -VCC = -15V,
t ≤ 25mS, VCM = 15V
ICC
+VOpp
Power Supply Current
Output Voltage Swing
Subgroups
Min
mV
1, 2, 3
-7.0
mV
1, 2, 3
-50
50
µV/˚C
2
-50
50
µV/˚C
3
-1000 1000
pA/˚C
2
-1000 1000
pA/˚C
3
mA
1, 2, 3
65
mA
1, 2
80
mA
3
-65
+VCC = 15V, -VCC = -15V
8.0
mA
1
7.0
mA
2
9.0
mA
3
RL = 10KΩ, VCM = -20V
17
V
4, 5, 6
RL = 2KΩ, VCM = -20V
16
V
4, 5, 6
5
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LM118JAN
LM118 JAN Electrical Characteristics
(Continued)
DC Parameters
(Continued)
The following conditions apply to all the following parameters, unless otherwise specified.
DC:
VCC = ± 20V
Symbol
Parameter
Conditions
-VOpp
Output Voltage Swing
RL = 10KΩ, VCM = 20V
+AVS
Open Loop Voltage Gain
VO = 15V, RL = 2KΩ
Notes
Min
RL = 2KΩ, VCM = 20V
Open Loop Voltage Gain
Open Loop Voltage Gain
Subgroups
-17
V
4, 5, 6
V
4, 5, 6
-16
50
V/mV
4
(Note 8)
32
V/mV
5, 6
(Note 8)
50
V/mV
4
(Note 8)
32
V/mV
5, 6
(Note 8)
50
V/mV
4
(Note 8)
32
V/mV
5, 6
(Note 8)
50
V/mV
4
(Note 8)
32
V/mV
5, 6
± VCC = ± 5V, VO = ± 2V,
RL = 2KΩ
(Note 8)
10
V/mV
4, 5, 6
± VCC = ± 5V, VO = ± 2V,
RL = 10KΩ
(Note 8)
10
V/mV
4, 5, 6
Max
Unit
Subgroups
VO = -15V, RL = 2KΩ
VO = -15V, RL = 10KΩ
AVS
Unit
(Note 8)
VO = 15V, RL = 10KΩ
-AVS
Max
AC Parameters
The following conditions apply to all the following parameters, unless otherwise specified.
AC:
VCC = ± 20V
Symbol
Parameter
Conditions
Notes
Min
NIBB
Noise Input Broadband
BW = 10Hz to 5KHz,
RS = 0Ω
25
µVRMS
7
NIPC
Noise Input Popcorn
BW = 10Hz to 5KHz,
RS = 20KΩ
80
µVPK
7
TRtR
Transient Response: Rise Time VI = 50mV, PRR = 1KHz
40
nS
7, 8A, 8B
TROS
Transient Response: Overshoot VI = 50mV, PRR = 1KHz
50
%
7, 8A, 8B
+SR
Slew Rate
50
V/µS
7, 8B
40
V/µS
8A
50
V/µS
7, 8B
40
V/µS
8A
-SR
+tS
-tS
Slew Rate
Settling Time
Settling Time
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AV = 1, VI = -5V to +5V
AV = 1, VI = +5V to -5V
VI = -5V to +5V
VI = +5V to -5V
6
(Note 10)
800
nS
12
(Note 10)
1200
nS
13, 14
(Note 10)
800
nS
12
(Note 10)
1200
nS
13, 14
LM118JAN
LM118 JAN Electrical Characteristics
(Continued)
DC Drift Parameters
The following conditions apply to all the following parameters, unless otherwise specified.
DC:
VCC = ± 20V
Delta calculations performed on JAN S devices at group B, subgroup 5 only.
Symbol
Parameter
Conditions
Notes
Min
Max
Unit
Subgroups
VIO
Input Offset Voltage
VCM = 0V
-1.0
1.0
mV
1
± IIB
Input Bias Current
VCM = 0V, RS = 100KΩ
-25
25
nA
1
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction
to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the
number given in the Absolute Maximum Ratings, whichever is lower.
Note 5: The inputs are shunted with back-to-back diodes for over voltage protection. Therefore, excessive current will flow if a differential input voltage in excess
of 1V is applied between the inputs unless some limiting resistance is used.
Note 6: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 7: Human body model, 1.5 kΩ in series with 100 pF.
Note 8: Datalog in K = V/mV
Note 9: Calculated parameter.
Note 10: Errorband = ± 2%.
Note 11: Slash Sheet: RS = 20KΩ, tested with RS = 100KΩ for better resolution.
7
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LM118JAN
Typical Performance Characteristics
Input Current
Voltage Gain
20141926
20141925
Power Supply Rejection
Input Noise Voltage
20141927
20141928
Common Mode Rejection
Supply Current
20141929
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20141930
8
LM118JAN
Typical Performance Characteristics
(Continued)
Closed Loop Output
Impedance
Current Limiting
20141932
20141931
Input Current
Unity Gain Bandwidth
20141934
20141933
Voltage Follower Slew Rate
Inverter Settling Time
20141936
20141935
9
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LM118JAN
Typical Performance Characteristics
(Continued)
Large Signal Frequency
Response
Open Loop Frequency
Response
20141937
20141938
Voltage Follower Pulse
Response
Large Signal Frequency
Response
20141940
20141939
Open Loop Frequency
Response
Inverter Pulse Response
20141942
20141941
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10
LM118JAN
Auxiliary Circuits
Offset Balancing
Feedforward Compensation
for Greater Inverting Slew Rate
(Note 12)
20141910
Isolating Large Capacitive Loads
20141908
*Balance circuit necessary for increased slew.
Note 12: Slew rate typically 150V/µs.
Compensation for Minimum Settling Time
(Note 13)
20141911
Overcompensation
20141912
20141909
Note 13: Slew and settling time to 0.1% for a 10V step change is 800 ns.
11
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LM118JAN
Typical Applications
Fast Voltage Follower
(Note 14)
20141913
Integrator or Slow Inverter
20141914
CF = Large
(CF ≥ 50 pF)
*Do not hard-wire as integrator or slow inverter; insert a 10k-5 pF network in series with the input, to prevent oscillation.
Note 14: Do not hard-wire as voltage follower (R1 ≥ 5 kΩ)
Differential Amplifier
Fast Summing Amplifier
20141916
20141915
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12
LM118JAN
Typical Applications
(Continued)
Fast Sample and Hold
20141918
D/A Converter Using Ladder Network
20141919
*Optional — Reduces settling time.
13
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LM118JAN
Typical Applications
(Continued)
Four Quadrant Multiplier
20141917
∆Output zero.
*“Y” zero
+“X” zero
‡ Full scale adjust.
D/A Converter Using Binary Weighted Network
20141920
*Optional — Reduces settling time.
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14
LM118JAN
Typical Applications
(Continued)
Fast Summing Amplifier with Low Input Current
20141921
Instrumentation Amplifier
Wein Bridge Sine Wave Oscillator
20141922
20141923
15
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LM118JAN
Revision History Section
Date
Released
07/12/05
www.national.com
Revision
A
Section
Originator
New Release, Corporate format
L. Lytle
16
Changes
1 MDS data sheet, MJLM118–X Rev 0A0
was converted into the Corp. datasheet
format. MDS datasheet will be archived.
LM118JAN
Physical Dimensions
inches (millimeters) unless otherwise noted
Metal Can Package (H)
NS Package Number H08C
Ceramic Dual-In-Line Package (J)
NS Package Number J08A
Ceramic Dual-In-Line Package (J)
NS Package Number J14A
17
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LM118JAN Operational Amplifier
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Ceramic SOIC (W)
NS Package Number W10A
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