TI DS90UH926QSQX

DS90UH926Q
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SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP
Check for Samples: DS90UH926Q
FEATURES
DESCRIPTION
•
The DS90UH926Q deserializer, in conjunction with
the DS90UH925Q serializer, provides a solution for
secure distribution of content-protected digital video
within automotive entertainment systems. This
chipset translates a parallel RGB Video Interface into
a single pair high-speed serialized interface. The
digital video data is protected using the industry
standard HDCP copy protection scheme. The serial
bus scheme, FPD-Link III, supports full duplex of high
speed forward data transmission and low speed
backchannel communication over a single differential
link. Consolidation of video data and control over a
single differential pair reduces the interconnect size
and weight, while also eliminating skew issues and
simplifying system design.
1
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•
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Integrated HDCP Cipher Engine with On-Chip
Key Storage
Bidirectional Control Interface Channel
Interface with I2C Compatible Serial Control
Bus
Supports High Definition (720p) Digital Video
Format
RGB888 + VS, HS, DE and Synchronized I2S
Audio Supported
5 to 85 MHz PCLK Supported
Single 3.3V Operation with 1.8V or 3.3V
compatible LVCMOS I/O Interface
AC-coupled STP Interconnect up to 10 Meters
Parallel LVCMOS Video Outputs
I2C Compatible Serial Control Bus for
Configuration
DC-Balanced & Scrambled Data w/ Embedded
Clock
Adaptive Cable Equalization
Supports HDCP Repeater Application
@ SPEED Link BIST Mode and LOCK Status
Pin
Image Enhancement (White Balance and
Dithering) and Internal Pattern Generation
EMI Minimization (SSCG and EPTO)
Low Power Modes Minimize Power Dissipation
Automotive Grade Product: AEC-Q100 Grade 2
qualified
>8kV HBM and ISO 10605 ESD rating
Backward Compatible Modes
The DS90UH926Q deserializer recovers the RGB
data, three video control signals and four
synchronized I2S audio signals. It extracts the clock
from a high speed serial stream. An output LOCK pin
provides the link status if the incoming data stream is
locked, without the use of a training sequence or
special SYNC patterns, as well as a reference clock.
The DS90UH926Q deserializer has a 31-bit parallel
LVCMOS output interface to accommodate the RGB,
video control, and audio data.
An adaptive equalizer optimizes the maximum cable
reach. EMI is minimized by output SSC generation
(SSCG) and Enhanced Progressive Turn-On (EPTO)
features.
The HDCP cipher engine is implemented in both the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
APPLICATIONS
•
•
Automotive Display for Navigation
Rear Seat Entertainment Systems
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
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Applications Diagram
HOST
Graphics
Processor
RGB Digital Display Interface
VDD33
VDDIO
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
DOUT+
RIN+
DOUT-
RIN100 ohm STP Cable
PDB
OSS_SEL
OEN
MODE_SEL
MODE_SEL
INTB
INTB_IN
DS90UH925Q
Serializer
PDB
I2S AUDIO
(STEREO)
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
3
/
SCL
SDA
IDx
DS90UH926Q
Deserializer
DAP
LOCK
PASS
3
/
SCL
SDA
IDx
RGB Display
720p
24-bit color depth
I2S AUDIO
(STEREO)
MCLK
DAP
I2S_DA/GPO_REG6
BISTEN
RES1
PASS
R0/GPIO0
R1/GPIO1
R2
VDDIO
R3
R4
R5
R6
R7
LOCK
OEN
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
DS90UH926Q Pin Diagram
OSS_SEL
46
30
I2S_WC/GPO_REG7
RES0
47
29
VDD33_B
VDD33_A
48
28
G0/GPIO2
RIN+
49
27
G1/GPIO3
RIN-
50
26
G2
CMF
51
25
G3
CMLOUTP
52
DS90UH926Q
24
VDDIO
23
G4
22
G5
G6
CMLOUTN
53
TOP VIEW
NC
54
DAP = GND
CAPR12
55
21
IDx
56
20
G7
11
12
13
B5
B4
VDDIO
15
10
B6
MODE_SEL
9
B7
14
8
HS
B3
7
BISTC/INTB_IN
VS
16
6
60
DE
MCLK
5
B2
PCLK
17
4
59
CAPL12
PDB
3
B1/I2S_DB/GPO_REG5
SCL
18
2
58
SDA
19
CAPI2S
1
57
B0/GPO_REG4
I2S_CLK/GPO_REG8
CAPP12
Figure 1. DS90UH926Q — Top View
2
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PIN DESCRIPTIONS
Pin Name
Pin #
I/O, Type
Description
LVCMOS Parallel Interface
R[7:0]
33, 34, 35, 36,
37, 39, 40, 41
O, LVCMOS
w/ pull down
RED Parallel Interface Data Output Pins
Leave open if unused
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1
G[7:0]
20, 21, 22, 23,
25, 26, 27, 28
O, LVCMOS
w/ pull down
GREEN Parallel Interface Data Output Pins
Leave open if unused
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
B[7:0]
9, 10, 11, 12,
14, 17, 18, 19
O, LVCMOS
w/ pull down
BLUE Parallel Interface Data Output Pins
Leave open if unused
B0 can optionally be used as GPO_REG4 and B1 can optionally be used as I2S_DB or
GPO_REG5.
HS
8
O, LVCMOS
w/ pull down
Horizontal Sync Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 9
VS
7
O, LVCMOS
w/ pull down
Vertical Sync Output Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
DE
6
O, LVCMOS
w/ pull down
Data Enable Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs. See Table 9
PCLK
5
O, LVCMOS
w/ pull down
Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 9
1, 30, 45
O, LVCMOS
w/ pull down
Digital Audio Interface Data Output Pins
Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
60
O, LVCMOS
w/ pull down
I2S Master Clock Output. x1, x2, or x4 of I2S_CLK Frequency.
18
O, LVCMOS
w/ pull down
Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by
MODE_SEL or configuration register
Leave open if unused
I2S_B can optionally be used as BI or GPO_REG5.
GPIO[3:0]
27, 28, 40, 41
I/O,
LVCMOS
w/ pull down
Standard General Purpose IOs.
Available only in 18-bit color mode, and set by MODE_SEL or configuration register.
See Table 9
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[8:
4]
1, 30, 45, 18,
19
O, LVCMOS
w/ pull down
General Purpose Outputs and set by configuration register. See Table 9
Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
16
Input,
LVCMOS w/
pull-down
Interrupt Input
Shared with BISTC
PDB
59
I, LVCMOS
w/ pull-down
Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = L, device is powered down.
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE,
the PLL is shutdown and IDD is minimized. .
OEN
31
Input,
LVCMOS w/
pull-down
Output Enable Pin.
See Table 3
OSS_SEL
46
Input,
LVCMOS w/
pull-down
Output Sleep State Select Pin.
See Table 3
MODE_SEL
15
I, Analog
I2S_CLK,
I2S_WC,
I2S_DA
MCLK
Optional Parallel Interface
I2S_DB
INTB_IN
Control
Device Configuration Select. See Table 4
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PIN DESCRIPTIONS (continued)
Pin Name
Pin #
I/O, Type
BISTEN
44
I, LVCMOS
w/ pull-down
Description
BIST Enable Pin.
0: BIST Mode is disabled.
1: BIST Mode is enabled.
BISTC
16
I, LVCMOS
w/ pull-down
BIST Clock Select.
Shared with INTB_IN
0: PCLK; 1: 33 MHz
IDx
56
I, Analog
SCL
3
I/O,
LVCMOS
Open Drain
I2C Clock Input / Output Interface
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SDA
2
I/O,
LVCMOS
Open Drain
I2C Data Input / Output Interface
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
LOCK
32
O, LVCMOS
w/ pull down
LOCK Status Output Pin
0: PLL is unlocked, RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states are controlled
by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
PASS
42
O, LVCMOS
w/ pull down
PASS Output Pin
0: One or more errors were detected in the received payload
1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
I2C
I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider.
See Figure 20
Status
FPD-Link III Serial Interface
RIN+
49
I, LVDS
True Input.
The interconnection should be AC Coupled to this pin with a 0.1 μF capacitor.
RIN-
50
I, LVDS
Inverting Input.
The interconnection should be AC Coupled to this pin with a 0.1 μF capacitor.
CMLOUTP
52
O, LVDS
True CML Output
Monitor point for equalized differential signal
CMLOUTN
53
O, LVDS
Inverting CML Output
Monitor point for equalized differential signal
CMF
51
Analog
Common Mode Filter. Connect 0.1 μF capacitor to GND
48, 29
Power
Power to on-chip regulator 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDD pin.
VDDIO
13, 24, 38
Power
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V – 3.6 V. Requires 4.7 uF to GND at each VDDIO
pin.
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
Power (1) and Ground
VDD33_A,
VDD33_B
Regulator Capacitor
CAPR12,
CAPP12,
CAPI2S
55, 57, 58
CAP
Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAP pin.
CAPL12
4
CAP
Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
Others
NC
RES[1:0]
(1)
4
54
NC
43.47
GND
No connect. This pin may be left open or tied to any level.
Reserved. Tie to Ground.
The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
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Block Diagram
REGULATOR
RINCMLOUTP
CMLOUTN
BISTEN
BISTC
PDB
SCL
SCA
IDx
MODE_SEL
Output Latch
RIN+
24
HDCP Cipher
Serial to Parallel
CMF
DC Balance Decoder
SSCG
Error
Detector
Timing and
Control
Clock and
Data
Recovery
RGB [7:0]
HS
VS
DE
4
I2S_CLK
I2S_WC
I2S_DA
MCLK
PASS
PCLK
LOCK
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
−0.3V to +4.0V
Supply Voltage – VDD33
−0.3V to +4.0V
Supply Voltage – VDDIO
−0.3V to (VDDIO + 0.3V)
LVCMOS I/O Voltage
−0.3V to +2.75V
Deserializer Input Voltage
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
60 WQFN Package
Maximum Power Dissipation Capacity at 25°C
Derate above 25°C
31 °C/W
θJC
2.4 °C/W
ESD Rating (IEC, powered-up only), RD = 330Ω,
CS = 150pF
Air Discharge (RIN+, RIN−)
ESD Rating (ISO10605), RD = 330Ω, CS = 150pF
Air Discharge (RIN+, RIN−)
Contact Discharge (RIN+, RIN−)
Contact Discharge(RIN+, RIN−)
ESD Rating (ISO10605), RD = 2kΩ, CS = 150 &
330pF
1/ θJA°C/W
θJA
Air Discharge (RIN+, RIN−)
Contact Discharge (RIN+, RIN−)
≥±15 kV
≥±8 kV
≥±15 kV
≥±8 kV
≥±15 kV
≥±8 kV
ESD Rating (HBM)
≥±8 kV
ESD Rating (CDM)
≥±1.25 kV
≥±250 V
ESD Rating (MM)
For soldering specifications:
see product folder at www.ti.com and
www.ti.com/lit/an/snoa549c/snoa549c.pdf
(1)
(2)
6
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
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Recommended Operating Conditions
Min
Nom
Max
Units
Supply Voltage (VDD33)
3.0
3.3
3.6
V
LVCMOS Supply Voltage (VDDIO)
3.0
3.3
3.6
V
OR
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
Operating Free Air Temperature (TA)
−40
+25
+105
°C
85
MHz
100
mVP-P
PCLK Frequency
Supply Noise
(1)
5
(1)
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDD33 and VDDIOsupplies
with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symb
ol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
2.0
VDDIO
V
GND
0.8
V
LVCMOS I/O DC SPECIFICATIONS
VIH
High Level Input Voltage
VDDIO = 3.0 to 3.6V
VIL
Low Level Input Voltage
VDDIO = 3.0 to 3.6V
IIN
Input Current
VIN = 0V or VDDIO = 3.0 to 3.6V
−10
+10
μA
VDDIO = 3.0 to 3.6V
2.0
VDDIO
V
0.65*
VDDIO
VDDIO
V
GND
0.8
V
GND
0.35*
VDDIO
V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
PDB
VDDIO = 1.71 to 1.89V
VDDIO = 3.0 to 3.6V
IIN
Input Current
VDDIO = 1.71 to 1.89V
VIN = 0V or VDDIO
VDDIO = 3.0
to 3.6V
VDDIO = 1.7
to 1.89V
VDDIO = 3.0 to 3.6V
VOH
High Level Output
Voltage
IOH = −4mA
VOL
Low Level Output
Voltage
IOL = +4mA
IOS
Output Short Circuit
Current
VOUT = 0V
IOZ
TRI-STATE® Output
Current
VOUT = 0V or VDDIO, PDB = L
(1)
(2)
(3)
OEN, OSS_SEL,
BISTEN, BISTC /
INTB_IN,
GPIO[3:0]
VDDIO = 1.7
to 1.89V
VDDIO = 3.0 to 3.6V
VDDIO = 1.7
to 1.89V
R[7:0], G[7:0],
B[7:0], HS, VS,
DE, PCLK, LOCK,
PASS, MCLK,
I2S_CLK,
I2S_WC, I2S_DA,
I2S_DB,
GPO_REG[8:4]
±1
−10
±1
+10
μA
−10
±1
+10
μA
2.4
VDDIO
V
VDDIO0.45
VDDIO
V
GND
0.4
V
GND
0.35
V
−60
−10
mA
+10
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symb
ol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
+50
mV
FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS
VTH
Differential Threshold
High Voltage
VTL
Differential Threshold
Low Voltage
VCM
Differential Commonmode Voltage
RT
Internal Termination
Resistor - Differential
VCM = 2.5V
(Internal VBIAS)
−50
mV
RIN+, RIN1.8
80
100
V
120
Ω
CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS
VODp-p
Differential Output
Voltage
CMLOUTP,
CMLOUTN
RL = 100Ω
360
mVp-p
SUPPLY CURRENT
IDD1
IDDIO1
IDD2
IDDIO2
Supply Current
(includes load current)
f = 85MHz
Supply Current
(includes load current)
f = 85MHz
CL = 12pF,
Checker Board Pattern
Figure 2
CL = 4pF
Checker Board Pattern,
Figure 2
IDDS
IDDIOS
8
VDDIO= 3.6V
VDDIO = 1.89V
VDD33 = 3.6V
VDDIO = 3.6V
VDDIO = 1.89V
VDD33 = 3.6V
Supply Current Sleep
Mode
Without Input Serial
Stream
VDDIO = 3.6V
VDDIO = 1.89V
IDDZ
IDDIOZ
VDD33= 3.6V
Supply Current Power
Down
PDB = L, All LVCMOS
inputs are floating or tied
to GND
VDD33 = 3.6V
VDDIO = 3.6V
VDDIO = 1.89V
VDD33
VDDIO
VDD33
VDDIO
VDD33
VDDIO
VDD33
VDDIO
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125
145
mA
110
118
mA
60
75
mA
125
145
mA
75
85
mA
50
65
mA
90
115
mA
3
5
mA
2
3
mA
2
10
mA
0.05
10
mA
0.05
10
mA
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
f = 5 – 85MHz,
GPIO[3:0]
0.25*f
Mbps
>50
>75
kbps
0.3
0.4
UI
200
300
mV
GPIO BIT RATE
Forward Channel Bit Rate
BR
Back Channel Bit Rate
See (4) (5)
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
EW
Differential Output Eye Opening
Width (6)
EH
Differential Output Eye Height
RL = 100Ω,
Jitter Freq >f / 40
Figure 3 (4) (5)
CMLOUTP,
CMLOUTN,
f = 85MHz
SWITCHING CHARACTERISTICS
tRCP
PCLK Output Period
tRDC
PCLK Output Duty Cycle
LVCMOS Low-to-High Transition
Time
Figure 4
tCLH
LVCMOS High-to-Low Transition
Time
Figure 4
tCHL
tROS
tROH
tDDLT
tDD
(1)
(2)
(3)
(4)
(5)
(6)
(7)
11.76
T
200
ns
45
50
55
%
VDDIO = 1.71 - 1.89V,
CL = 12pF
2
3
ns
VDDIO = 3.0 – 3.6V,
CL = 12pF
2
3
ns
2
3
ns
2
3
ns
VDDIO = 1.71 - 1.89V,
CL = 12pF
VDDIO = 3.0 – 3.6V,
CL = 12pF
Data Valid before PCLK – Setup
Time
SSCG = OFF
Figure 7
VDDIO = 1.71 - 1.89V,
CL = 12pF
Data Valid after PCLK – Hold
Time
SSCG = OFF
Figure 7
Active to OFF Delay
Figure 6 (4) (5)
tXZR
tRCP = tTCP
Lock Time
Figure 6 (4) (5) (7)
Delay – Latency
PCLK
R[7:0], G[7:0],
B[7:0], HS,
VS, DE,
PCLK, LOCK,
PASS, MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
2.2
ns
2.2
ns
VDDIO = 1.71 - 1.89V,
CL = 12pF
3.0
ns
VDDIO = 3.0 – 3.6V,
CL = 12pF
3.0
ns
VDDIO = 3.0 – 3.6V,
CL = 12pF
OEN = L, OSS_SEL = H
SSCG = OFF
(4) (5)
R[7:0], G[7:0],
B[7:0]
10
ns
HS, VS, DE,
PCLK, LOCK,
PASS
15
ns
MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
60
ns
f = 5 – 85MHz
5
f = 5 – 85MHz
147*T
40
ms
ns
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35*PCLK). The UI scales with PCLK frequency.
tDDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream.
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
tDCCJ
tONS
tONH
Parameter
Cycle-to-Cycle Jitter (8) (9)
Data Valid After OEN = H
SetupTime
Figure 8 (8) (9)
Data Tri-State After OEN = L
SetupTime
Figure 8 (8) (9)
Data Tri-State after OSS_ SEL =
H, Setup Time
Figure 8 (8) (9)
tSES
tSEH
Data to Low after OSS_SEL = L
Setup Time
Figure 8 (8) (9)
Conditions
Pin/Freq.
Min
Typ
Max
Units
f = 5 – <15
MHz
0.5
ns
f = 15 – 85
MHz
0.2
ns
I2S_CLK = 1 12.28MHz
+/-2
ns
VDDIO = 1.71 - 1.89V,
CL = 12pF
50
ns
VDDIO = 3.0 – 3.6V,
CL = 12pF
50
ns
50
ns
50
ns
5
ns
5
ns
VDDIO = 1.71 - 1.89V,
CL = 12pF
5
ns
VDDIO = 3.0 – 3.6V,
CL = 12pF
5
ns
800
ns
SSCG = OFF
VDDIO = 1.71 - 1.89V,
CL = 12pF
VDDIO = 3.0 – 3.6V,
CL = 12pF
VDDIO = 1.71 - 1.89V,
CL = 12pF
VDDIO = 3.0 – 3.6V,
CL = 12pF
R[7:0], G[7:0],
B[7:0], HS,
VS, DE,
PCLK, MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
BIST Mode
tPASS
BIST PASS Valid Time
BISTEN = H
Figure 9 (8) (9)
PASS
SSCG Mode
fDEV
Spread Spectrum Clocking
Deviation Frequency
fMOD
Spread Spectrum Clocking
Modulation Frequency
(8)
(9)
10
SeeFigure 13, Table 1 and
Table 2 (8) (9)
f = 85MHz,
SSCG = ON
±0.5
±2.5
%
8
100
kHz
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
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Recommended Timing for the Serial Control Bus
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
fSCL
Parameter
SCL Clock Frequency
tLOW
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
tr
tf
Conditions
Min
Typ
Max
Units
Standard Mode
0
100
kHz
Fast Mode
0
400
kHz
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Hold time for a start or a
repeated start condition
Figure 10
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Set Up time for a start or a
repeated start condition
Figure 10
Standard Mode
4.7
µs
Fast Mode
0.6
µs
Data Hold Time
Figure 10
Standard Mode
0
3.45
µs
Fast Mode
0
0.9
µs
Data Set Up Time
Figure 10
Standard Mode
250
Fast Mode
100
ns
Set Up Time for STOP
Condition, Figure 10
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Bus Free Time
Between STOP and START,
Figure 10
Standard Mode
4.7
µs
Fast Mode
1.3
µs
SCL & SDA Rise Time,
Figure 10
Standard Mode
1000
ns
Fast Mode
300
ns
SCL & SDA Fall Time,
Figure 10
Standard Mode
300
ns
Fast mode
300
ns
SCL Low Period
SCL High Period
ns
DC and AC Serial Control Bus Characteristics
Over 3.3V supply and temperature ranges unless otherwise specified. (1) (2) (3)
Symbol
Parameter
Conditions
VIH
Input High Level
SDA and SCL
VIL
Input Low Level Voltage
SDA and SCL
VHY
Input Hysteresis
Max
Units
0.7*
VDD33
Min
Typ
VDD33
V
GND
0.3*
VDD33
V
>50
VOL
SDA, IOL = 1.25mA
Iin
SDA or SCL, Vin = VDD33 or GND
mV
0
0.36
V
-10
+10
µA
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time — READ
SeeFigure 10
tHD;DAT
Hold Up Time — READ
SeeFigure 10
615
ns
tSP
Input Filter
50
ns
Cin
Input Capacitance
SDA or SCL
<5
pF
(1)
(2)
(3)
SDA, RPU = 10kΩ, Cb ≤ 400pF, Figure 10
430
ns
20
ns
560
ns
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
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AC TIMING DIAGRAMS AND TEST CIRCUITS
VDDIO
PCLK
GND
VDDIO
RGB[n] (odd),
VS, HS
GND
VDDIO
RGB[n] (even),
DE
GND
Figure 2. Checker Board Data Pattern
EW
VOD (+)
CMLOUT
(Diff.)
EH
0V
EH
VOD (-)
tBIT (1 UI)
Figure 3. CML Output Driver
VDDIO
80%
20%
GND
tCLH
tCHL
Figure 4. LVCMOS Transition Times
START
BIT
STOP
BIT
START
BIT
STOP
BIT
RIN
(Diff.)
0
1
2
SYMBOL N
33
0
1
2
33
SYMBOL N+1
tDD
PCLK
(RFB = L)
RGB[7:0],
I2S[2:0],
HS, VS, DE
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 5. Delay - Latency
12
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2.0V
PDB
0.8V
RIN
(Diff.)
}v[š
Œ
tDDLT
LOCK
TRI-STATE
or LOW
Z or L
tXZR
RGB[7:0],
HS, VS, DE,
I2S
TRI-STATE or LOW or Pulled Up
PCLK
(RFB = L)
Z or L or PU
TRI-STATE or LOW
OFF
Z or L
IN LOCK TIME
ACTIVE
OFF
Figure 6. PLL Lock Times and PDB TRI-STATE Delay
VDDIO
PCLK
w/RFB = H
1/2 VDDIO
GND
RGB[7:0],
VS, HS, DE,
I2S
VDDIO
VOHmin
VOLmax
tROS
GND
tROH
Figure 7. Output Data Valid (Setup and Hold) Times with SSCG = OFF
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PDB = H
VIH
OSS_SEL
VIL
VIH
OEN
VIL
RIN
(Diff.)
}v[š
Œ
tSEH
tSES
tONH
tONS
TRI-STATE
LOCK
(HIGH)
PASS
ACTIVE
HIGH
RGB[7:0],
HS, VS, DE,
I2S[2:0]
LOW
TRI-STATE
PCLK
(RFB = L)
LOW
TRI-STATE
HIGH
ACTIVE
ACTIVE
TRI-STATE
LOW
TRI-STATE
LOW
Figure 8. Output State (Setup and Hold) Times
BISTEN
1/2 VDDIO
tPASS
PASS
(w/errors)
1/2 VDDIO
Current BIST Test - Toggle on Error
Prior BIST Result
Result Held
Figure 9. BIST PASS Waveform
SDA
tf
tHD;STA
tLOW
tr
tf
tr
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 10. Serial Control Bus Timing Diagram
14
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Functional Description
The DS90UH926Q deserializer receives a 35-bits symbol over a single serial FPD-Link III pair operating upto
2.975 Gbps application payload. The serial stream contains an embedded clock, video control signals and the
DC-balanced video data and audio data which enhance signal quality to support AC coupling.
The DS90UH926Q deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. It also applies decryption through a High-Bandwidth Digital Content Protection (HDCP) Cipher to this
video and audio data stream following reception of the data from the FPD-Link III decoder. The decrypted parallel
LVCMOS video bus is provided to the display. The deserializer is intended for use with the DS90UH925Q
serializer, but is also backward compatible with DS90UR905Q or DS90UR907Q FPD-Link II serializer.
HIGH SPEED FORWARD CHANNEL DATA TRANSFER
The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing RGB data, sync signals,
HDCP, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 11 illustrates the serial stream per
PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,
balanced and scrambled.
C1
C0
Figure 11. FPD-Link III Serial Stream
The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps
maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.
LOW SPEED BACK CHANNEL DATA TRANSFER
The Low-Speed Backward Channel (LS_BC) of the DS90UH926Q provides bidirectional communication between
the display and host processor. The information is carried back from the Deserializer to the Serializer per serial
symbol. The back channel control data is transferred over the single serial link along with the high-speed forward
data, DC balance coding and embedded clock information. This architecture provides a backward path across
the serial link together with a high speed forward channel. The back channel contains the I2C, HDCP, CRC and
4 bits of standard GPIO information with 10 Mbps line rate.
BACKWARD COMPATIBLE MODE
The DS90UH926Q is also backward compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers with
15 - 65 MHz pixel clock frequencies supported. It receives 28-bits of data over a single serial FPD-Link II pair
operating at the line rate of 420 Mbps to 1.82 Gbps. This backward compatible mode is provided through the
MODE_SEL pin (Table 4) or the configuration register (Table 9). When backward compatible mode = ON, set
LFMODE = 0.
INPUT EQUALIZATION GAIN
FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces the
medium-induced deterministic jitter. It equalizes up to 10m STP cables with 3 connection breaks at maximum
serialized stream payload rate of 2.975 Gbps.
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COMMON MODE FILTER PIN (CMF)
The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1 μF capacitor has to be connected to this pin to Ground.
VIDEO CONTROL SIGNAL FILTER
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 12.
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 12. Video Control Signal Filter Waveform
EMI REDUCTION FEATURES
Spread Spectrum Clock Generation (SSCG)
The DS90UH926Q provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both
clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.5% (5%
total) at up to 100 kHz modulations are available. This feature may be controlled by register. See Table 1,
Table 2 and Table 9. Note: Do not enable the SSCG feature if the source PCLK into the SER has a clock with
spread spectrum already.
Frequency
fdev(max)
FPCLK+
FPCLK
FPCLK-
fdev(min)
Time
1/fmod
Figure 13. SSCG Waveform
16
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Table 1. SSCG Configuration
LFMODE = L (15 - 85 MHz)
SSCG Configuration (0x2C) LFMODE = L (15 - 85MHz)
Spread Spectrum Output
SSC[2]
SSC[1]
SSC[0]
Fdev (%)
Fmod (kHz)
L
L
L
±0.9
PCLK / 2168
L
L
H
±1.2
L
H
L
±1.9
L
H
H
±2.5
H
L
L
±0.7
H
L
H
±1.3
H
H
L
±2.0
H
H
H
±2.5
PCLK / 1300
Table 2. SSCG Configuration
LFMODE = H (5 - <15 MHz)
SSCG Configuration (0x2C) LFMODE = H (5 - <15 MHz)
SSC[2]
SSC[1]
L
L
L
L
H
H
Spread Spectrum Output
SSC[0]
Fdev (%)
Fmod (kHz)
L
L
±0.5
PCLK / 628
L
H
±1.3
H
L
±1.8
H
H
±2.5
L
L
±0.7
L
H
±1.2
H
H
L
±2.0
H
H
H
±2.5
PCLK / 388
Enhanced Progressive Turn-On (EPTO)
The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a
different time. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise.
In addition it spreads the noise spectrum out reducing overall EMI.
LVCMOS VDDIO Option
The deserializer parallel bus can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility.
The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
POWER DOWN (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the VDDIO, where VDDIO = 3.0V to 3.6V or VDD33. To save power disable the link when the display
is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and VDDIO
have reached final levels; no external components are required. In the case of driven by the VDDIO = 3.0V to 3.6V
or VDD33 directly, a 10 kΩ resistor to the VDDIO = 3.0V to 3.6V or VDD33 , and a >10µF capacitor to the ground are
required (See Figure 23 Typical Connection Diagram).
STOP STREAM SLEEP
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer will
then lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the Serial Control Bus
Registers values are retained.
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SERIAL LINK FAULT DETECT
The serial link fault detection is able to detect any of following seven (7) conditions
1. cable open
2. “+” to “-“ short
3. “+” short to GND
4. “-“ short to GND
5. “+” short to battery
6. “-“ short to battery
7. Cable is linked incorrectly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control
Bus Register bit 0 of address 0x1C Table 9. The link errors can be monitored though Link Error Count of the
Serial Control Bus Register bit [4:0] of address 0x41 Table 9.
OSCILLATOR OUTPUT
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by
register Address 0x02, bit 5 (OSC Clock Enable). See Table 9.
PIXEL CLOCK EDGE SELECT (RFB)
The RFB determines the edge that the data is strobed on. If RFB is High (‘1’), output data is strobed on the
Rising edge of the PCLK. If RFB is Low (‘0’), data is strobed on the Falling edge of the PCLK. This allows for
inter-operability with downstream devices. The deserializer output does not need to use the same edge as the
Ser input. This feature may be controlled by register. See Table 9.
CLOCK-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) AND OUTPUT STATE
SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the DS90UH926Q completes its lock sequence to the input
serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is
available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and OSS_SEL
setting (Table 3) or register bit (Table 9). See Figure 8.
Table 3. Output States
Inputs
Outputs
Serial
input
PDB
OEN
OSS_SEL
Lock
Pass
Data, GPIO, I2S
CLK
X
0
X
X
Z
Z
Z
Z
X
1
0
0
L or H
L
L
L
X
1
0
1
L or H
Z
Z
Z
Static
1
1
0
L
L
L
L/OSC (Register bit
enable)
Static
1
1
1
L
Previous Status
L
L
Active
1
1
0
H
L
L
L
Active
1
1
1
H
Valid
Valid
Valid
LOW FREQUENCY OPTIMIZATION (LFMODE)
The LFMODE is set via register (Table 9) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency of
the deserializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is
High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed,
a PDB reset is required.
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INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)
1. On DS90UH925, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UH926Q deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UH925Q serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt
condition.
4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .
5. A read to HDCP_ISR will clear the interrupt at the DS90UH925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN (pin 16) on the DS90UH926Q. The system is now ready to return to step (1) at next falling edge of
INTB_IN.
CONFIGURATION SELECT (MODE_SEL)
Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pullup resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL
input (VR4) and VDD33 to select one of the other 10 possible selected modes. See Figure 14 and Table 4.
VDD33
R3
MODE_SEL
VR4
R4
DES
Figure 14. MODE_SEL Connection Diagram
Table 4. Configuration Select (MODE_SEL)
#
Ideal Ratio
VR4/VDD33
Ideal VR4
(V)
Suggested
Resistor R3
kΩ (1% tol)
Suggested
Resistor R4
kΩ (1% tol)
LFMODE
Repeater
Backward
Compatible
I2S Channel B
(18–bit Mode)
1
0
0
Open
40.2 or Any
L
L
L
L
2
0.121
0.399
294
40.2
L
L
L
H
3
0.152
0.502
280
49.9
L
H
L
L
4
0.242
0.799
240
76.8
L
H
L
H
5
0.311
1.026
226
102
H
L
L
L
6
0.402
1.327
196
130
H
L
L
H
7
0.492
1.624
169
165
H
H
L
L
8
0.583
1.924
137
191
H
H
L
H
9
0.629
2.076
124
210
L
L
H
L
LFMODE:
L = frequency range is 15 – 85 MHz (Default)
H = frequency range is 5 – <15 MHz
Repeater:
L = Repeater mode is OFF (Default)
H = Repeater mode is ON
Backward Compatible:
L = Backward Compatible mode is OFF (Default)
H = Backward Compatible mode is ON; SER = DS90UR905Q or DS90UR907Q
– frequency range = 15 - 65MHz, set LFMODE = L
I2S Channel B:
L = I2S Channel B mode is OFF, Normal 24-bit RGB Mode (Default)
H = I2S Channel B mode is ON, 18-bit RGB Mode with I2S_DB Enabled. Note: use of GPIO(s) on unused inputs must be enabled by
register.
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I2S RECEIVING
In normal 24-bit RGB operation mode, the DS90UH926Q provides up to 3-bit of I2S. They are I2S_CLK, I2S_WC
and I2S_DA, as well as the Master I2S Clock (MCLK). The encrypted and packetized audio information is
received during the video blanking periods along with specific information about the clock frequency. Note: The
bit rates of any I2S input bits must maintain one fourth of the PCLK rate. The audio decryption is supported per
HDCP v1.3. A jitter cleaning feature reduces I2S_CLK output jitter to +/- 2ns.
I2S Jitter Cleaning
The DS90UH926Q features a standalone PLL to clean the I2S data jitter supporting high end car audio systems.
If I2S CLK frequency is less than 1MHz, this feature has to be disabled through the register bit I2S Control
(0x2B) in Table 9.
Secondary I2S Channel
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio
channel in additional to the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this
synchronization feature on this bit, set the MODE_SEL (Table 4) or program through the register bit (Table 9).
MCLK
The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S
PLL is disabled, the MCLK output is OFF. Table 5 below covers the range of I2S sample rates and MCLK
frequencies.
By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK frequencies can also
be enabled through the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 9. To select desired MCLK
frequency, write bit 7 (0x3A) = 1, then write to bit [6:4] accordingly.
Table 5. Audio Interface Frequencies
Sample Rate (kHz)
I2S Data Word Size
(bits)
I2S CLK
(MHz)
MCLK Output
(MHz)
Bit [6:4]
(Address 0x3A)
32
16
1.024
x1 of I2S CLK
000
x2 of I2S CLK
001
x4 of I2S CLK
010
x1 of I2S CLK
000
x2 of I2S CLK
001
x4 of I2S CLK
010
x1 of I2S CLK
000
x2 of I2S CLK
001
x4 of I2S CLK
010
x1 of I2S CLK
001
x2 of I2S CLK
010
x4 of I2S CLK
011
x1 of I2S CLK
010
x2 of I2S CLK
011
x4 of I2S CLK
100
x1 of I2S CLK
000
x2 of I2S CLK
001
x4 of I2S CLK
010
x1 of I2S CLK
001
x2 of I2S CLK
010
x4 of I2S CLK
011
x1 of I2S CLK
001
x2 of I2S CLK
010
x4 of I2S CLK
011
44.1
48
96
192
32
44.1
48
20
16
16
16
16
24
24
24
1.411
1.536
3.072
6.144
1.536
2.117
2.304
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Table 5. Audio Interface Frequencies (continued)
Sample Rate (kHz)
I2S Data Word Size
(bits)
I2S CLK
(MHz)
MCLK Output
(MHz)
Bit [6:4]
(Address 0x3A)
96
24
4.608
x1 of I2S CLK
010
x2 of I2S CLK
011
x4 of I2S CLK
100
x1 of I2S CLK
011
x2 of I2S CLK
100
x4 of I2S CLK
101
x1 of I2S CLK
001
x2 of I2S CLK
010
x4 of I2S CLK
011
x1 of I2S CLK
001
x2 of I2S CLK
010
x4 of I2S CLK
011
x1 of I2S CLK
001
x2 of I2S CLK
010
x4 of I2S CLK
011
x1 of I2S CLK
010
x2 of I2S CLK
011
x4 of I2S CLK
100
x1 of I2S CLK
011
x2 of I2S CLK
100
x4 of I2S CLK
110
192
24
32
9.216
32
44.1
2.048
32
48
2.822
32
96
3.072
32
192
6.144
32
12.288
GPIO[3:0] and GPO_REG[8:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UH926Q can be used as the general
purpose IOs GPIO[3:0] in either forward channel (Outputs) or back channel (Inputs) application.
GPIO[3:0] Enable Sequence
See Table 6 for the GPIO enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 9 on DS90UH925Q only.
DS90UH926Q is automatically configured as in the 18-bit mode.
Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UH925Q, then write 0x05 to
address 0x1F on DS90UH926Q.
Table 6. GPIO Enable Sequencing Table
#
Description
Device
Forward Channel
Back Channel
1
Enable 18-bit
mode
DS90UH925Q
0x12 = 0x04
0x12 = 0x04
DS90UH926Q
Auto Load from DS90UH925Q
Auto Load from DS90UH925Q
2
GPIO3
DS90UH925Q
0x0F = 0x03
0x0F = 0x05
DS90UH926Q
0x1F = 0x05
0x1F = 0x03
DS90UH925Q
0x0E = 0x30
0x0E = 0x50
DS90UH926Q
0x1E = 0x50
0x1E = 0x30
DS90UH925Q
0x0E = 0x03
0x0E = 0x05
DS90UH926Q
0x1E = 0x05
0x0E = 0x05
DS90UH925Q
0x0D = 0x93
0x0D = 0x95
DS90UH926Q
0x1D = 0x95
0x1D = 0x93
3
4
5
GPIO2
GPIO1
GPIO0
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GPO_REG[8:4] Enable Sequence
GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 7
for the GPO_REG enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 9 on DS90UH925Q only.
DS90UH926Q is automatically configured as in the 18-bit mode.
Step 2: To enable GPO_REG8 outputs an “1” , write 0x90 to address 0x21 on DS90UH926Q..
Table 7. GPO_REG Enable Sequencing Table
#
Description
Device
Local Access
1
Enable 18-bit mode
DS90UH926Q
0x12 = 0x04
(on DS90UH925Q)
2
GPO_REG8
DS90UH926Q
0x21 = 0x90
“1”
0x21 = 0x10
“0”
0x21 = 0x09
“1”
0x21 = 0x01
“0”
0x20 = 0x90
“1”
0x20 = 0x10
“0”
0x20 = 0x09
“1”
0x20 = 0x01
“0”
0x1F = 0x90
“1”
0x1F = 0x10
“0”
3
GPO_REG7
DS90UH926Q
4
GPO_REG6
DS90UH926Q
5
6
22
GPO_REG5
GPO_REG4
DS90UH926Q
DS90UH926Q
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HDCP
The Cipher function is implemented in the deserializer per HDCP v1.3 specification. It supports the HDCP key
exchange for the authentication over the back channel with the DS90UH925Q serializer. An on-chip Non-Volatile
Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the
manufacturing process and are not accessible external to the device.
The DS90UH926Q receives encrypted data and uses the Cipher engine to decrypt as per HDCP v1.3. Decrypted
data is available at the deserializer parallel output interface.
HDCP REPEATER
When DS90UH925Q and DS90UH926Q are configured as the HDCP Repeater application, it provides a
mechanism to extend HDCP transmission over multiple links to multiple display devices. This repeater
application provides a mechanism to authenticate all HDCP Receivers in the system and distribute protected
content to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification.
Repeater Configuration
In HDCP repeater application, In this document, the DS90UH925Q is referred to as the HDCP Transmitter or
transmit port (TX), and the DS90UH926Q is referred to as the HDCP Receiver (RX). Figure 15 shows the
maximum configuration supported for HDCP Repeater implementations using the DS90UH925Q (TX) and
DS90UH926Q (RX). Two levels of HDCP Repeaters are supported with a maximum of three HDCP Transmitters
per HDCP Receiver.
1:3 Repeater
1:3 Repeater
TX
Source
TX
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
TX
RX
Display
RX
RX
TX
TX
1:3 Repeater
RX
1:3 Repeater
RX
Figure 15. HDCP Maximum Repeater Application
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To support HDCP Repeater operation, the DS90UH926Q Deserializer includes the ability to control the
downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV
list to the upstream HDCP Transmitter. An I2C master within the DS90UH926Q communicates with the I2C slave
within the DS90UH925Q Serializer. The DS90UH925Q Serializer handles authenticating with a downstream
HDCP Receiver and makes status available through the I2C interface. The DS90UH926Q monitors the transmit
port status for each DS90UH925Q and reads downstream KSV and KSV list values from the DS90UH925Q.
In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementation
includes two other interfaces. A parallel LVCMOS interface provides the unencrypted video data in 24-bit RGB
format and includes the DE/VS/HS control signals. In addition to providing the RGB video data, the parallel
LVCMOS interface communicates control information and packetized audio data during video blanking intervals.
A separate I2S audio interface may optionally be used to send I2S audio data between the HDCP Receiver and
HDCP Transmitter in place of using the packetized audio over the parallel LVCMOS interface. All audio and
video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter.
Figure 16 provides more detailed block diagram of a 1:2 HDCP repeater configuration.
HDCP Transmitter
DS90UH925
I2C
Master
upstream
Transmitter
I2C
downstream
Receiver
or
Repeater
I2C
Slave
Parallel
LVCMOS
HDCP Receiver
DS90UH926
I2S Audio
HDCP Transmitter
DS90UH925
downstream
Receiver
or
Repeater
I2C
Slave
FPD-Link III interfaces
Figure 16. HDCP 1:2 Repeater Configuration
Repeater Connections
The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP
Transmitter Figure 17.
1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7 kΩ resistors
3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
4. IDx pin – Each HDCP Transmitter and Receiver must have an unique I2C address.
5. MODE_SEL pin – All HDCP Transmitter and Receiver must be set into the Repeater Mode.
6. Interrupt pin– Connect DS90UH926Q INTB_IN pin to DS90UH925Q INTB pin. The signal must be pulled up
to VDDIO.
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DS90UH926Q
VDD33
DS90UH925Q
R[7:0]
R[7:0]
G[7:0]
G[7:0]
B[7:0]
B[7:0]
DE
DE
VS
VS
HS
HS
I2S_CLK
I2S_CLK
I2S_WC
I2S_WC
I2S_DA
I2S_DA
Optional
MODE_SEL
VDD33
MODE_SEL
VDDIO
INTB_IN
INTB
VDD33
VDD33
ID[x]
VDD33
SDA
SDA
SCL
SCL
ID[x]
Figure 17. HDCP Repeater Connection Diagram
BUILT IN SELF TEST (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and the
low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for
system diagnostics.
BIST Configuration and Status
The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or
configuration register (Table 9) through the deserializer. When LFMODE = 0, the pin based configuration defaults
to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can
select the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, the
pin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.
When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the
Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to
35 bit errors.
The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset
(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to
the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the
connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the
deserializer is locked or unlocked, the lock status can be read in the register. See Table 9.
Sample BIST Sequence
See Figure 18 for the BIST mode flow diagram.
Step 1: For the DS90UH925Q and DS90UH926Q FPD-Link III chipset, BIST Mode is enabled via the BISTEN
pin of DS90UH926Q FPD-Link III deserializer. The desired clock source is selected through BISTC pin.
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Step 2: The DS90UH925Q serializer is woken up through the back channel if it is not already on. The all zero
pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the
deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and
BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low
for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to
determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there
was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST
is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 19 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
reducing signal condition enhancements ( Rx Equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 18. BIST Mode Flow Diagram
Forward Channel and Back Channel Error Checking
While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal test pattern.
The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to the
deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with allzeroes and records any errors in status registers and dynamically indicates the status on PASS pin.
The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as
indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The
register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the
functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in
BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.
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DES Outputs
BISTEN
(DES)
Case 1 - Pass
PCLK
(RFB = L)
RGB[7:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
SSO
Case 2 - Fail
X = bit error(s)
DATA
(internal)
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 19. BIST Waveforms
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Serial Control Bus
The DS90UH926Q is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple
deserializer devices may share the serial control bus since 16 device addresses are supported. Device address
is set via R1 and R2 values on IDx pin. See Figure 20 below.
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /
Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external
pull-up resistor to VDD33. For most applications a 4.7 k pull-up resistor to VDD33 may be used. The resistor value
may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven
Low.
VDD33
R1
VDD33
IDx
VR2
HOST
or
Salve
4.7k
4.7k
R2
SCL
SCL
SDA
SDA
SER
or
DES
To other
Devices
Figure 20. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pull-up resistor and a
pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to
select one of the other 16 possible addresses. See Table 8.
Table 8. Serial Control Bus Addresses for IDx
#
Ideal Ratio
VR2 / VDD33
Ideal VR2
(V)
Suggested Resistor Suggested Resistor
R1 kΩ (1% tol)
R2 kΩ (1% tol)
Address 7'b
Address 8'b
Appended
1
0
0
Open
40.2 or Any
0x2C
0x58
2
0.121
0.399
294
40.2
0x2D
0x5A
3
0.152
0.502
280
49.9
0x2E
0x5C
4
0.182
0.601
270
60.4
0x2F
0x5E
5
0.212
0.700
267
71.5
0x30
0x60
6
0.242
0.799
240
76.8
0x31
0x62
7
0.273
0.901
243
90.9
0x32
0x64
8
0.310
1.023
226
102
0x33
0x66
9
0.356
1.175
210
115
0x34
0x68
10
0.402
1.327
196
130
0x35
0x6A
11
0.447
1.475
182
147
0x36
0x6C
12
0.492
1.624
169
165
0x37
0x6E
13
0.538
1.775
154
180
0x38
0x70
14
0.583
1.924
137
191
0x39
0x72
15
0.629
2.076
124
210
0x3A
0x74
16
0.727
2.399
90.9
243
0x3B
0x76
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Table 9. Serial Control Bus Registers
ADD
(dec)
ADD
(hex)
Register
Name
0
0x00
I2C Device ID
1
0x01
Reset
Bit(s)
Register
Type
Default Function
(hex)
7:1
RW
Device ID
7–bit address of Deserializer
See Table 4
0
RW
ID Setting
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
7
RW
Remote
Auto Power
Down
Remote Auto Power Down
1: Power down when no forward channel link is detected
0: Do not power down when no forward channel link is
detected
0x04
6:3
2
0x02
Configuration
[0]
Descriptions
Reserved.
2
RW
BC Enable
Back channel enable
1: Enable
0: Disable
1
RW
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
0
RW
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
7
RW
Output
Enable
LVCMOS Output Enable.
1: Enable
0: Disable. Tri-state Outputs
6
RW
OEN and
OSS_SEL
Override
Overrides Output Enable Pin and Output State pin
1: Enable override
0: Disable - no override
5
RW
OSC Clock
Enable
OSC Clock Output Enable
If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
4
RW
Output
Sleep State
Select
(OSS_SEL)
OSS Select to Control Output State during Lock Low
Period
1: Enable
0: Disable
3
RW
Backward
Compatible
select by
pin or
register
control
Backward Compatible (BC) mode set by MODE_SEL pin
or register.
1: BC is set by register bit. Use register bit reg_0x02[2] to
set BC Mode
0: Use MODE_SEL pin.
2
RW
Backward
Compatible
Mode
Select
Backward compatible (BC) mode to DS90UR905Q or
DS90UR907Q, if reg_0x02[3] = 1
1: Backward compatible with DS90UR905Q or
DS90UR907Q
(Set LFMODE = 0)
0: Backward Compatible is OFF (default)
1
RW
LFMODE
select by
pin or
register
control
Frequency range is set by MODE_SEL pin or register
1: Frequency range is set by register. Use register
bitreg_0x02[0] to set LFMODE
0: Frequency range is set by MODE_SEL pin.
0
RW
LFMODE
Frequency range select
1: PCLK range = 5 - <15 MHz, if reg_0x02[1] = 1
0: PCLK range = 15 - 85 MHz (default)
0x00
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
3
0x03
Configuration
[1]
Bit(s)
Register
Type
7
6
Default Function
(hex)
0xF0
Reserved.
RW
CRC
Generator
Enable
4
RW
Filter
Enable
HS, VS, DE two clock filter When enabled, pulses less
than two full PCLK cycles on the DE, HS, and VS inputs
will be rejected
1: Filtering enable
0: Filtering disable
3
RW
I2C Passthrough
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
2
RW
Auto ACK
ACK Select
1: Auto ACK enable
0: Self ACK
0
RW
RRFB
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
7:1
RW
BCC
Watchdog
Timer
The watchdog timer allows termination of a control channel
transaction, if it fails to complete within a programmed
amount of time. This field sets the Bidirectional Control
Channel Watchdog Timeout value in units of 2
milliseconds.
This field should not be set to 0
0
RW
BCC
Watchdog
Timer
Disable
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation"
7
RW
I2C Pass
Through All
I2C Pass-Through All Transactions
1: Enabled
0: Disabled
6:4
RW
I2C SDA
Hold Time
Internal I2C SDA Hold Time
It configures the amount of internal hold time provided for
the SDA input relative to the SCL input. Units are 50 ns.
3:0
RW
I2C Filter
Depth
I2C Glitch Filter Depth
It configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5 ns.
5
5
30
0x04
0x05
BCC
Watchdog
Control
I2C Control [1]
CRC Generator Enable (Back Channel)
1: Enable
0: Disable
Reserved
1
4
Descriptions
Reserved
0xFE
0x2E
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
6
0x06
I2C Control [2]
Bit(s)
Register
Type
7
R
6
Default Function
(hex)
0x00
Forward
Channel
Sequence
Error
Control Channel Sequence Error Detected It indicates a
sequence error has been detected in forward control
channel. It this bit is set, an error may have occurred in the
control channel operation.
RW
Clear
Sequence
Error
It clears the Sequence Error Detect bit
This bit is not self-clearing.
4:3
RW
SDA Output SDA Output Delay
Delay
This field configures output delay on the SDA output.
Setting this value will increase output delay in units of 50
ns. Nominal output delay values for SCL to SDA are:
00 : 250ns
01: 300ns
10: 350ns
11: 400ns
2
RW
Local Write
Disable Remote Writes to Local Registers through
Serializer (Does not affect remote access to I2C slaves at
Deserializer)
1: Stop remote write to local device registers
0: remote write to local device registers
1
RW
I2C Bus
Timer
Speed
Speed up I2C Bus Watchdog Timer
1: Timer expires after approximately 50 ms
0: Timer expires after approximately 1s
0
RW
I2C Bus
Timer
Disable
Disable I2C Bus Timer When the I2C Timer may be used
to detect when the I2C bus is free or hung up following an
invalid termination of a transaction. If SDA is high and no
signalling occurs for approximately 1 s, the I2C bus is
assumed to be free. If SDA is low and no signaling occurs,
the device will attempt to clear the bus by driving 9 clocks
on SCL
7:1
RW
Remote ID
Remote ID
Configures the I2C Slave ID of the remote Serializer. A
value of 0 in this field disables I2C access to remote
Serializer. This field is automatically configured via the
Serializer Forward Channel. Software may overwrite this
value, but should also set the FREEZE DEVICE ID bit to
prevent overwriting by the Forward Channel.
0
RW
Freeze
Device ID
Freeze Serializer Device ID
1: Prevent auto-loading of the Serializer Device ID from the
Forward Channel. The ID will be frozen at the value
written.
0: Update
RW
0x00
Target
Slave
Device ID0
7-bit Remote Slave Device ID 0
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID0, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
RW
0x00
Target
Slave
Device ID1
5
7
0x07
Remote
Device ID
Descriptions
8
0x08
SlaveID[0]
7:1
9
0x09
SlaveID[1]
7:1
Reserved
0x18
0
Reserved
0
7-bit Remote Slave Device ID 1
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID1, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
Bit(s)
Register
Type
10
0x0A
11
Default Function
(hex)
SlaveID[2]
7:1
RW
0x00
Target
Slave
Device ID2
0x0B
SlaveID[3]
7:1
RW
0x00
Target
Slave
Device ID3
12
0x0C
SlaveID[4]
7:1
RW
0x00
Target
Slave
Device ID4
13
0x0D
SlaveID[5]
7:1
RW
0x00
Target
Slave
Device ID5
14
0x0E
SlaveID[6]
7:1
RW
0x00
Target
Slave
Device ID6
15
0x0F
SlaveID[7]
7:1
RW
0x00
Target
Slave
Device ID7
16
0x10
SlaveAlias[0]
7:1
RW
0x00
ID[0] Match
0
7-bit Remote Slave Device ID 3
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID3, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
7-bit Remote Slave Device ID 4
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID4, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
7-bit Remote Slave Device ID 5
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID5, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
7-bit Remote Slave Device ID 6
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID6, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
32
7-bit Remote Slave Device ID 2
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID2, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
0
0
Descriptions
7-bit Remote Slave Device ID 7
Configures the physical I2C address of the remote I2C
Slave device attached to the remote Serializer. If an I2C
transaction is addressed to the Slave Alias ID7, the
transaction will be remapped to this address before
passing the transaction across the Bidirectional Control
Channel to the Serializer.
Reserved
7-bit Remote Slave Device Alias ID 0
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID0 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
Bit(s)
Register
Type
17
0x11
18
Default Function
(hex)
SlaveAlias[1]
7:1
RW
0x00
ID[1] Match
0x12
SlaveAlias[2]
7:1
RW
0x00
ID[2] Match
19
0x13
SlaveAlias[3]
7:1
RW
0x10
ID[3] Match
20
0x14
SlaveAlias[4]
7:1
RW
0x00
ID[4] Match
21
0x15
SlaveAlias[5]
7:1
RW
0x00
ID[5] Match
22
0x16
SlaveAlias[6]
7:1
RW
0x00
ID[6] Match
0
RW
23
0x17
SlaveAlias[7]
7:1
RW
0x00
ID[7] Match
0
Descriptions
7-bit Remote Slave Device Alias ID 1
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID1 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
0
7-bit Remote Slave Device Alias ID 2
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID2 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
0
7-bit Remote Slave Device Alias ID 3
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID3 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
0
7-bit Remote Slave Device Alias ID 4
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID4 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
0
7-bit Remote Slave Device Alias ID 5
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID5 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
0
7-bit Remote Slave Device Alias ID 6
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID6 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
7-bit Remote Slave Device Alias ID 7
Configures the decoder for detecting transactions
designated for an I2C Slave device attached to the remote
Serializer. The transaction will be remapped to the address
specified in the Slave ID7 register.
A value of 0 in this field disables access to the remote I2C
Slave.
Reserved
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
28
0x1C
General Status
Bit(s)
Register
Type
Default Function
(hex)
7:4
RW
3
R
I2S Locked
1
R
Signal
Detect
Signal Detect
1: Serial input detected
0: Serial input not detected
0
R
Lock
Deserializer CDR, PLL's clock to recovered clock
frequency
1: Deserializer locked to recovered clock
0: Deserializer not locked
0x00
Reserved
2
29
30
34
0x1D
0x1E
GPIO0 Config
GPIO2 and
GPIO1 Config
Descriptions
I2S Lock Status
0: I2S PLL controller not locked
1: I2S PLL controller locked to input I2S clock
Reserved
7:4
R
Rev-ID
Revision ID: 1010: Production Device
3
RW
0xA0
GPIO0
Output
Value
Local GPIO Output Value
This value is output on the GPIO pin when the GPIO
function is enabled, the local GPIO direction is Output, and
remote GPIO control is disabled.
2
RW
GPIO0
Remote
Enable
Remote GPIO0 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer
1
RW
GPIO0
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO0
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
7
RW
GPIO2
Output
Value
Local GPIO Output Value
This value is output on the GPIO when the GPIO function
is enabled, the local GPIO direction is Output, and remote
GPIO control is disabled.
6
RW
GPIO2
Remote
Enable
Remote GPIO2 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
5
RW
GPIO2
Direction
Local GPIO Direction
1: Input
0: Output
4
RW
GPIO2
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
3
RW
GPIO1
Output
Value
Local GPIO Output Value
This value is output on the GPIO when the GPIO function
is enabled, the local GPIO direction is Output, and remote
GPIO control is disabled.
2
RW
GPIO1
Remote
Enable
Remote GPIO1 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
1
RW
GPIO1
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO1
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
0x00
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
31
0x1F
GPO_REG4
and GPO3
Config
Bit(s)
Register
Type
7
RW
Default Function
(hex)
0x00
GPO_REG4 Local GPO_REG4 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
6:5
32
0x20
GPO_REG6
and
GPO_REG5
Config
Reserved
4
RW
GPO_REG4 GPO_REG4 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPIO3
Output
Value
Local GPIO Output Value This value is output on the GPIO
when the GPIO function is enabled, the local GPIO
direction is Output, and remote GPIO control is disabled.
2
RW
GPIO3
Remote
Enable
Remote GPIO3 Control
1: Enable GPIO control from remote Serializer. The GPIO
pin will be an output, and the value is received from the
remote Deserializer.
0: Disable GPIO control from remote Serializer.
1
RW
GPIO3
Direction
Local GPIO Direction
1: Input
0: Output
0
RW
GPIO3
Enable
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
7
RW
0x00
6:5
0x21
GPO8 and
GPO7 Config
GPO_REG6 Local GPO_REG6 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
Reserved
4
RW
GPO_REG6 GPO_REG6 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPO_REG5 Local GPO_REG5 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
0
RW
GPO_REG5 GPO_REG5 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
7
RW
2:1
33
Descriptions
Reserved
6:5
0x00
GPO_REG8 Local GPO_REG8 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
Reserved
4
RW
GPO_REG8 GPO_REG8 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
3
RW
GPO_REG7 Local GPO_REG7 Output Value
Output
This value is output on the GPO when the GPO function is
Value
enabled, the local GPO direction is Output, and remote
GPO control is disabled.
RW
GPO_REG7 GPO_REG7 Function Enable
Enable
1: Enable GPO operation
0: Enable normal operation
2:1
0
Reserved
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
Bit(s)
Register
Type
34
0x22
Data Path
Control
7
RW
6
RW
Pass RGB
Setting this bit causes RGB data to be sent independent of
DE. This allows operation in systems which may not use
DE to frame video data or send other data when DE is
deasserted. Note that setting this bit prevents HDCP
operation and blocks packetized audio. This bit does not
need to be set in DS90UB925 or in Backward Compatible
mode.
1: Pass RGB independent of DE
0: Normal operation
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
5
RW
DE Polarity
This bit indicates the polarity of the DE (Data Enable)
signal.
1: DE is inverted (active low, idle high)
0: DE is positive (active high, idle low)
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
4
RW
I2S_Gen
This bit controls whether the HDCP Receiver outputs
packetized Auxiliary/Audio data on the RGB video output
pins.
1: Don't output packetized audio data on RGB video output
pins
0: Output packetized audio on RGB video output pins.
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
3
RW
I2S Channel 1: Set I2S Channel B Enable from reg_0x22[0]
B Enable
0: Set I2S Channel B Enable from MODE_SEL pin
Override
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
2
RW
18-bit Video 1: Select 18-bit video mode
Select
Note: use of GPIO(s) on unused inputs must be enabled
by register.
0: Select 24-bit video mode
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
1
RW
I2S
Transport
Select
0
RW
I2S Channel I2S Channel B Enable
B Enable
1: Enable I2S Channel B on B1 output
0: I2S Channel B disabled
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
7
RW
35
0x23
General
Purpose
Control
Default Function
(hex)
0x00
0x10
Override FC 1: Disable loading of this register from the forward channel,
Config
keeping locally written values intact
0: Allow forward channel loading of this register
Rx RGB
Checksum
6:5
Mode Status
36
Descriptions
1: Enable I2S Data Forward Channel Frame Transport
0: Enable I2S Data Island Transport
Note: this bit is automatically loaded from the remote
serializer unless bit 7 of this register is set.
RX RGB Checksum Enable Setting this bit enables the
Receiver to validate a one-byte checksum following each
video line. Checksum failures are reported in the
HDCP_STS register
Reserved
4
R
Mode_Sel
Mode Select is Done
3
R
LFMODE
Low Frequency Mode Status
2
R
Repeater
Repeater Mode Status
1
R
Backward
Backward Compatible Mode Status
0
R
I2S Channel I2S Channel B Status
B
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
36
0x24
BIST Control
Bit(s)
Register
Type
7:4
Default Function
(hex)
0x08
Descriptions
Reserved
3
RW
BIST Pin
Config
BIST Configured through Pin
1: BIST configured through pin
0: BIST configured through register bit
2:1
RW
BIST Clock
Source
BIST Clock Source
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
0
RW
BIST
Enable
BIST Control
1: Enabled
0: Disabled
37
0x25
BIST Error
7:0
R
0x00
BIST Error
Count
BIST Error Count
38
0x26
SCL High
Time
7:0
RW
0x83
SCL High
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL output
when the Deserializer is the Master on the local I2C bus.
Units are 50 ns for the nominal oscillator clock frequency.
The default value is set to provide a minimum 5us SCL
high time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
39
0x27
SCL Low Time
7:0
RW
0x84
SCL Low
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL output
when the De-Serializer is the Master on the local I2C bus.
This value is also used as the SDA setup time by the I2C
Slave for providing data prior to releasing SCL during
accesses over the Bidirectional Control Channel. Units are
50 ns for the nominal oscillator clock frequency. The
default value is set to provide a minimum 5us SCL low
time with the internal oscillator clock running at 26MHz
rather than the nominal 20MHz.
41
0x29
FRC Control
7
RW
0x00
Timing
Mode
Select
Select display timing mode
0: DE only Mode
1: Sync Mode (VS,HS)
6
RW
VS Polarity
0: Active High
1: Active Low
5
RW
HS Polarity
0: Active High
1: Active Low
4
RW
DE Polarity
0: Active High
1: Active Low
3
RW
FRC2
Enable
0: FRC2 Disable
1: FRC2 Enable
2
RW
FRC1
Enable
0: FRC1 Disable
1: FRC1 Enable
1
RW
Hi-FRC 2
Disable
0: Hi-FRC2 Enable
1: Hi-FRC2 Disable
0
RW
Hi-FRC 1
Disable
0: Hi-FRC1 Enable
1: Hi-FRC1 Disable
7:6
RW
Page
Setting
00:
01:
10:
11:
5
RW
White
Balance
Enable
0: White Balance Disable
1: White Balance Enable
4
RW
LUT Reload 0: Reload Disable
Enable
1: Reload Enable
42
0x2A
White Balance
Control
3:0
0x00
Configuration Registers
Red LUT
Green LUT
Blue LUT
Reserved
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
43
0x2B
I2S Control
Bit(s)
Register
Type
7
RW
Default Function
(hex)
0x00
I2S PLL
6:1
0
44
58
0x2C
0x3A
SSCG Control
I2S MCLK
Output
38
0x41
Link Error
Count
I2S PLL Control
0: I2S PLL is ON for I2S data jitter cleaning
1: I2S PLL is OFF. No jitter cleaning
Reserved
RW
7:4
I2S Clock
Edge
0x00
I2S Clock Edge Select
0: I2S Data is strobed on the Rising Clock Edge
1: I2S Data is strobed on the Falling Clock Edge
Reserved
3
RW
SSCG
Enable
Enable Spread Spectrum Clock Generator
0: Disable
1: Enable
2:0
RW
SSCG
Selection
SSCG Frequency Deviation:
When LFMODE = H
fdev fmod
000: +/- 0.7 CLK/628
001: +/- 1.3
010: +/- 1.8
011: +/- 2.5
100: +/- 0.7 CLK/388
101: +/- 1.2
110: +/- 2.0
111: +/- 2.5
When LFMODE = L
fdev fmod
000: +/- 0.9 CLK/2168
001: +/- 1.2
010: +/- 1.9
011: +/- 2.5
100: +/- 0.7 CLK/1300
101: +/- 1.3
110: +/- 2.0
111: +/- 2.5
7
RW
MCLK
Override
1: Override divider select for MCLK
0: No override for MCLK divider
6:4
RW
MCLK
Frequency
Slect
See Table 5
0x00
3:0
65
Descriptions
Reserved
7:5
0x03
Reserved
4
RW
Link Error
Count
Enable
Enable serial link data integrity error count
1: Enable error count
0: Disable
3:0
RW
Link Error
Count
Link error count threshold.
Counter is pixel clock based. clk0, clk1 and DCA are
monitored for link errors, if error count is enabled,
deserializer loose lock once error count reaches threshold.
If disabled deserilizer loose lock with one error.
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
68
0x44
Equalization
Bit(s)
Register
Type
7:5
RW
Default Function
(hex)
0x60
EQ Stage 1
Select
4
86
0x56
CML Output
Reserved
RW
EQ Stage 2
Select
EQ select value.
Used if adaptive EQ is bypassed.
000 Min EQ 2nd Stage
001
010
011
100
101
110
111 Max EQ 2nd Stage
0
RW
Adaptive
EQ
1: Disable adaptive EQ (to write EQ select values)
0: Enable adaptive EQ
7:4
0x08
RW
Reserved
CMLOUT+/- 1: Disabled (Default)
Enable
0: Enabled
2:0
0x64
Pattern
Generator
Control
EQ select value.
Used if adaptive EQ is bypassed.
000 Min EQ 1st Stage
001
010
011
100
101
110
111 Max EQ 1st Stage
3:1
3
100
Descriptions
7:4
Reserved
RW
0x10
Pattern
Generator
Select
3:1
0
Fixed Pattern Select
This field selects the pattern to output when in Fixed
Pattern Mode. Scaled patterns are evenly distributed
across the horizontal or vertical active regions. This field is
ignored when Auto-Scrolling Mode is enabled. The
following table shows the color selections in non-inverted
followed by inverted color mode
0000: Reserved 0001: White/Black
0010: Black/White
0011: Red/Cyan
0100: Green/Magenta
0101: Blue/Yellow
0110: Horizontally Scaled Black to White/White to Black
0111: Horizontally Scaled Black to Red/Cyan to White
1000: Horizontally Scaled Black to Green/Magenta to
White
1001: Horizontally Scaled Black to Blue/Yellow to White
1010: Vertically Scaled Black to White/White to Black
1011: Vertically Scaled Black to Red/Cyan to White
1100: Vertically Scaled Black to Green/Magenta to White
1101: Vertically Scaled Black to Blue/Yellow to White
1110: Custom color (or its inversion) configured in PGRS,
PGGS, PGBS registers
1111: Reserved
Reserved
RW
Pattern
Generator
Enable
Pattern Generator Enable
1: Enable Pattern Generator
0: Disable Pattern Generator
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
101
0x65
Pattern
Generator
Configuration
Bit(s)
Register
Type
7:5
Default Function
(hex)
0x00
Descriptions
Reserved
4
RW
Pattern
Generator
18 Bits
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled patterns
will have 64 levels of brightness and the R, G, and B
outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use
256 levels of brightness.
3
RW
Pattern
Generator
External
Clock
Select External Clock Source
1: Selects the external pixel clock when using internal
timing.
0: Selects the internal divided clock when using internal
timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
2
RW
Pattern
Generator
Timing
Select
Timing Select Control
1: The Pattern Generator creates its own video timing as
configured in the Pattern Generator Total Frame Size,
Active Frame Size. Horizontal Sync Width, Vertical Sync
Width, Horizontal Back Porch, Vertical Back Porch, and
Sync Configuration registers.
0: the Pattern Generator uses external video timing from
the pixel clock, Data Enable, Horizontal Sync, and Vertical
Sync signals.
1
RW
Pattern
Generator
Color Invert
Enable Inverted Color Patterns
1: Invert the color output.
0: Do not invert the color output.
0
RW
Pattern
Generator
Auto-Scroll
Enable
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the
next enabled pattern after the number of frames specified
in the Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
102
0x66
Pattern
Generator
Indirect
Address
7:0
RW
0x00
Indirect
Address
This 8-bit field sets the indirect address for accesses to
indirectly-mapped registers. It should be written prior to
reading or writing the Pattern Generator Indirect Data
register.
See AN-2198 (SNLA132)
103
0x67
Pattern
Generator
Indirect Data
7:0
RW
0x00
Indirect
Data
When writing to indirect registers, this register contains the
data to be written. When reading from indirect registers,
this register contains the read back value.
See AN-2198 (SNLA132
128
0x80
RX_BKSV0
7:0
R
0x00
RX BKSV0
BKSV0: Value of byte 0 of the Deserializer KSV
129
0x81
RX_BKSV1
7:0
R
0x00
RX BKSV1
BKSV1: Value of byte 1 of the Deserializer KSV
130
0x82
RX_BKSV2
7:0
R
0x00
RX BKSV2
BKSV2: Value of byte 2 of the Deserializer KSV
131
0x83
RX_BKSV3
7:0
R
0x00
RX BKSV3
BKSV3: Value of byte 3of the Deserializer KSV.
132
0x84
RX_BKSV4
7:0
R
0x00
RX BKSV4
BKSV4: Value of byte 4of the Deserializer KSV.
144
0x90
TX_KSV0
7:0
R
0x00
TX KSV0
KSV0: Value of byte 0 of the Serializer KSV.
145
0x91
TX_KSV1
7:0
R
0x00
TX KSV1
KSV1: Value of byte 1 of the Serializer KSV.
146
0x92
TX_KSV2
7:0
R
0x00
TX KSV2
KSV2: Value of byte 2 of the Serializer KSV.
147
0x93
TX_KSV3
7:0
R
0x00
TX KSV3
KSV3: Value of byte 3 of the Serializer KSV.
148
0x94
TX_KSV4
7:0
R
0x00
TX KSV4
KSV4: Value of byte 4 of the Serializer KSV.
40
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
192
0xC0
HDCP_DBG
193
0xC1
HDCP_DBG2
Bit(s)
Register
Type
7:4
Default Function
(hex)
0x00
Reserved
3
R
RGB_CHK
SUM_EN
Enable RBG video line checksum.
1: Enables sending of ones-complement checksum for
each 8-bit RBG data channel following end of each video
data line.
0: Checksum disabled
Set via the HDCP_DBG register in the HDCP Transmitter.
2
R
FC_TEST
MODE
Frame Counter Testmode:
1: Speeds up frame counter used for Pj and Ri verification.
When set to a 1, Pj is computed every 2 frames and Ri is
computed every 16 frames.
0: Pj is computed every 16 frames and Ri is computed
every 128 frames.
Set via the HDCP_DBG register in the HDCP Transmitter.
1
R
TMR_
SPEEDUP
Timer Speedup:
1: Speed up HDCP authentication timers.
0: Standard authentication timing
Set via the HDCP_DBG register in the HDCP Transmitter.
0
R
HDCP_I2C
_FAST
HDCP I2C Fast mode Enable:
1: Enable the HDCP I2C Master in the HDCP Receiver to
operation with Fast mode timing.
0:Tthe I2C Master will operate with Standard mode timing.
Set via the HDCP_DBG register in the HDCP Transmitter.
7:2
1
0x00
RW
Reserved
NO_
DECRYPT
0
196
224
225
226
0xC4
0xE0
0xE1
0xE2
HDCP Status
RPTR TX0
RPTR TX1
RPTR TX2
Descriptions
No Decrypt:
1: The HDCP Receiver outputs the encrypted data on the
RGB pins. All other functions will work normally. This
provides a simple way of showing that the link is
encrypted.
0: Normal Operation
Reserved
7:2
0x00
Reserved
1
R
RGB_CHK
SUM_ERR
RGB Checksum Error Detected:
If RGB Checksum in enabled through the HDCP
Transmitter HDCP_DBG register, this bit will indicate if a
checksum error is detected. This register may be cleared
by writing any value to this register.
0
R
HDCP
Status
HDCP Authenticated:
Indicates the HDCP authentication has completed
successfully. The controller may now send video data
requiring content protection. This bit will be cleared if
authentication is lost or if the controller restarts
authentication.
7:1
R
Serializer Port 0 I2C Address:
Indicates the I2C address for the Repeater Serializer Port.
0
R
HDCP
Serializer
Port 0
Address
7:1
R
Serializer Port 1 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
0
R
HDCP
Serializer
Port 1
Address
HDCP
Serializer
Port 2
Address
Serializer Port 2 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
7:1
0
0x0
0x00
0x00
R
Serializer Port 0 Valid:
Indicates that the HDCP Repeater has a Serializer port at
the I2C Address identified by upper 7 bits of this register.
Serializer Port 1 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register.
Serializer Port 2 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register.
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Table 9. Serial Control Bus Registers (continued)
ADD
(dec)
ADD
(hex)
Register
Name
227
0xE3
RPTR TX3
Register
Type
7:1
R
0
R
Default Function
(hex)
0x00
Descriptions
HDCP
Serializer
Port 3
Address
Serializer Port 3 I2C Address: Indicates the I2C address
for the Repeater Serializer Port.
Serializer Port 3 Valid: Indicates that the HDCP Repeater
has a Serializer port at the I2C Address identified by upper
7 bits of this register
240
0xF0
7:0
R
0x5F
ID0
First byte ID code: ‘_’
241
0xF1
7:0
R
0x55
ID1
Second byte of ID code: ‘U’
242
0xF2
7:0
R
0x48
ID2
Third byte of ID code, Value will be either ‘B’ or ‘H’. ‘H’
indicates an HDCP capable device.
243
0xF3
7:0
R
0x39
ID3
Fourth byte of ID code: ‘9’
244
0xF4
7:0
R
0x32
ID4
Fifth byte of ID code: '2'
245
0xF5
7:0
R
0x36
ID5
Sixth byte of ID code: '6'
42
HDCP RX ID
Bit(s)
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Image Enhancement Features
Several image enhancement features are provided. White balance LUTs allow the user to define and target the
color temperature of the display. Adaptive Hi-FRC dithering enables the presentation of “true-color” images on an
18–bit color display.
WHITE BALANCE
The White Balance feature enables similar display appearance when using LCD’s from different vendors. It
compensates for native color temperature of the display, and adjusts relative intensities of R, G, B to maintain
specified color temperature. Programmable control registers are used to define the contents of three LUTs (8-bit
color value for Red, Green and Blue) for the White Balance Feature. The LUTs map input RGB values to new
output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8-bits per
entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. Calibrated values are
loaded into registers through the I2C interface (deserializer is a slave device). This feature may also be applied
to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is enabled and configured
via serial control bus register.
LUT contents
The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth
being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3
tables. Unused bits - LSBs -shall be set to “0” by the user.
When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique
8-bit entries. The 8-bit white balanced data is then available at the output of the DS90UH926Q deserailizer, and
driven to the display.
When 18-bit (666) input data is being driven to an 18-bit display, the white balance feature may be used in one of
two ways. First, simply load each LUT with 256, 8-bit entries. Each 8-bit entry is a 6-bit value (6 MSBs) with the 2
LSBs set to “00”. Thus as total of 64 unique 6-bit white balance output values are available for each color (R, G
and B). The 6-bit white balanced data is available at the output of the DS90UH926Q deserializer, and driven
directly to the display.
Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode
of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white
point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are
available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the
deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the
user must configure the DS90UH926Q to enable the FRC2 function.
Examples of the three types of LUT configurations described are shown in Figure 21
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Enabling white balance
The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be
followed by the user.
To initialize white balance after power-on (Table 10):
1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third
BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance.
By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature via the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller via I2C. This provides the user with the
flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT values. The
host controller loads the updated LUT values via the serial bus interface. There is no need to disable the white
balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be
seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When
reloading, partial LUT updates may be made.
8-bit in / 8 bit out
Gray level
Entry
Data Out
(8-bits)
00000000b
N/A
N/A
N/A
00000100b
N/A
N/A
N/A
00001000b
N/A
N/A
N/A
248
249
250
251
252
253
254
255
11111000b
N/A
N/A
N/A
11111100b
N/A
N/A
N/A
0
1
2
3
4
5
6
7
8
9
10
11
00000001b
N/A
N/A
N/A
00000110b
N/A
N/A
N/A
00001011b
N/A
N/A
N/A
248
249
250
251
252
253
254
255
11111010b
N/A
N/A
N/A
11111111b
N/A
N/A
N/A
«
«
0
1
2
3
4
5
6
7
8
9
10
11
Data Out
(8-bits)
«
11111010b
11111010b
11111011b
11111011b
11111110b
11111101b
11111101b
11111111b
Data Out
(8-bits)
«
248
249
250
251
252
253
254
255
6-bit in / 8 bit out
Gray level
Entry
«
00000000b
00000001b
00000011b
00000011b
00000110b
00000110b
00000111b
00000111b
00001000b
00001010b
00001001b
00001011b
«
0
1
2
3
4
5
6
7
8
9
10
11
6-bit in / 6 bit out
Gray level
Entry
Figure 21. White Balance LUT Configurations
44
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Table 10. White Balance Register Table
PAGE
ADD
(dec)
ADD
(hex)
0
42
0x2A
Register Name
White Balance
Control
Bit(s)
Access Default
(hex)
7:6
RW
5
RW
4
RW
0x00
Function
Description
Page Setting
00:
01:
10:
11:
Configuration Registers
Red LUT
Green LUT
Blue LUT
White Balance
Enable
0: White Balance Disable
1: White Balance Enable
0: Reload Disable
1: Reload Enable
3:0
Reserved
1
0–
255
00 – FF White Balance
Red LUT
FF:0
RW
N/A
Red LUT
2
0–
255
00 – FF White Balance
Green LUT
FF:0
RW
N/A
Green LUT
3
0–
255
00 – FF White Balance
Blue LUT
FF:0
RW
N/A
Blue LUT
256 8–bit entries to be applied to the Red
subpixel data
256 8–bit entries to be applied to the Green
subpixel data
256 8–bit entries to be applied to the Blue
subpixel data
ADAPTIVE HI-FRC DITHERING
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per subpixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled via serial control bus register.
Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance
LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT
that is calibrated for an 18-bit data source. The second FRC block, FRC2, follows the white balance block and is
intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a
24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing
control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active
polarity of the timing control signals. All this information is entered to DS90UH926Q control registers via the
serial bus interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit
data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is
evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are
supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off subpixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level
transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 22. The “1” or “0” value shown in the table
describes whether the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated
LSBs are “001”.
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Frame = 0, Line = 0
F0L0
Pixel Index
PD1
Pixel Data one
Cell Value 010
R[7:2]+0, G[7:2]+1, B[7:2]+0
LSB=001
three lsb of 9 bit data (8 to 9 for Hi-Frc)
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
F0L0
010
000
000
000
000
000
010
000
F0L1
101
000
000
000
101
000
000
000
R = 4/32
F0L2
000
000
010
000
010
000
000
000
G = 4/32
F0L3
000
000
101
000
000
000
101
000
B = 4/32
F1L0
000
000
000
000
000
000
000
000
F1L1
000
111
000
000
000
111
000
000
R = 4/32
F1L2
000
000
000
000
000
000
000
000
G = 4/32
F1L3
000
000
000
111
000
000
000
111
B = 4/32
F2L0
000
000
010
000
010
000
000
000
F2L1
000
000
101
000
000
000
101
000
R = 4/32
F2L2
010
000
000
000
000
000
010
000
G = 4/32
F2L3
101
000
000
000
101
000
000
000
B = 4/32
F3L0
000
000
000
000
000
000
000
000
F3L1
000
000
000
111
000
000
000
111
R = 4/32
F3L2
000
000
000
000
000
000
000
000
G = 4/32
F3L3
000
111
000
000
000
111
000
000
B = 4/32
LSB=001
LSB = 001
Figure 22. Default FRC Algorithm
Table 11. Recommended FRC settings
Source
White Balance LUT
Display
FRC1
FRC2
24–bit
24–bit
24–bit
Disabled
Disabled
24–bit
24–bit
18–bit
Disabled
Enabled
24–bit
18–bit
18–bit
Enabled
Disabled
18–bit
24–bit
24–bit
Disabled
Disabled
18–bit
24–bit
18–bit
Disabled
Enabled
18–bit
18–bit
18–bit
Disabled
Disabled
Internal Pattern Generation
The DS90UH926Q serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual
verification of panel operation. As long as the device is not in power down mode, the test pattern will be
displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a
programmed oscillator frequency. For detailed information, refer to Application Note AN-2198 (SNLA132 .
46
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APPLICATIONS INFORMATION
DISPLAY APPLICATION
The DS90UH926Q, in conjunction with the DS90UH925Q, is intended for interface between a HDCP compliant
host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and high definition (720p)
digital video format. It allows to receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with
three control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.
The included HDCP 1.3 compliant cipher block allows the authentication of the DS90UH926Q, which decrypts
both video and audio contents. The keys are pre-loaded by TI into Non-Volatile Memory (NVM) for maximum
security.
The deserializer is expected to be located close to its target device. The interconnect between the deserializer
and the target device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is
expected to be in the 5 to 10 pF range. Care should be taken on the PCLK output trace as this signal is edge
sensitive and strobes the data. It is also assumed that the fanout of the deserializer is up to three in the repeater
mode. If additional loads need to be driven, a logic buffer or mux device is recommended.
TYPICAL APPLICATION CONNECTION
Figure 23 shows a typical application of the DS90UH926Q deserializer for an 85 MHz 24-bit Color Display
Application. inputs utilize 0.1 μF coupling capacitors to the line and the deserializer provides internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1 μF capacitors and two 4.7
μF capacitors should be used for local device bypassing. Ferrite beads are placed on the power lines for
effective noise suppression. Since the device in the Pin/STRAP mode, two 10 kΩ pull-up resistors are used on
the parallel output bus to select the desired device features.
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO pins are connected to the 3.3 V
rail. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
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DS90UH926Q
3.3V
3.3V/1.8V
VDDIO
VDD33_A
FB1
C6
FB2
C4
VDDIO
VDD33_B
C7
C5
VDDIO
C8
CAPP12
C9
CAPR12
C13
CAPI2S
PASS
C10
LOCK
R7
R6
R5
R4
R3
R2
R1
R0
CAPL12
C11
C12
C1
Serial
FPD-Link III
Interface
RIN+
RINC2
CMF
G7
G6
G5
G4
G3
G2
G1
G0
C3
CMLOUTP
100:
VDD33_B*
CMLOUTN
R5
OSS_SEL
OEN
BISTEN
Host Control
BISTC / INTB_IN
PDB
C14
4.7k
4.7k
VDD33_B
VDD33_B
FB1 ± FB2: Impedance = 1 k: @ 100 MHz,
Low DC resistance (<1:)
C1 ± C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)
C4 ± C13 = 4.7 PF
C14 =>10 PF
HS
VS
DE
SDA
SCL
PCLK
R1
ID[X]
R2
LVCMOS
Parallel
Video / Audio
Interface
B7
B6
B5
B4
B3
B2
B1
B0
VDD33_B
I2S_CLK
I2S_WC
I2S_DA
MCLK
R3
R1 and R2 (see IDx Resistor Values Table 8)
NC
RES
MODE_SEL
R3 and R4 (see MODE_SEL Resistor Values Table 4)
R4
R5 = 10 k:
* or VDDIO = 3.3V+0.3V
2
DAP (GND)
Figure 23. Typical Connection Diagram
POWER UP REQUIREMENTS AND PDB PIN
The VDDs (V33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operating
voltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or VDD33, it is recommended to use a 10 kΩ pull-up and
a >10 uF cap to GND to delay the PDB input signal.
All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.
48
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DS90UH926Q
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SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
TRANSMISSION MEDIA
The DS90UH925Q and DS90UH926Q chipset is intended to be used in a point-to-point configuration through a
shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize impedance
discontinuities. The interconnect (cable and connector) between the serializer and deserializer should have a
differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the quality of
the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (e.g.
power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application environment.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define
the acceptable data eye opening width and eye opening height. A differential probe should be used to measure
across the termination resistor at the CMLOUT+/- pin Figure 3 .
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50µF to 100µF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small body
size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML
lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100Ω are
typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will
appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).
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49
DS90UH926Q
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
www.ti.com
CML INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
Revision
•
•
50
March 7, 2012
– Deleted “DC Electrical Characteristics” PDB VDDIO = 1.71 to 1.89V
– Added under “SUPPLY CURRENT IDDZ, DDIOZ, IDDIOZMax = 10mA
– Added under “CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS” EW Min = 0.3 UI AND EH Min =
200 mV
– Added “INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)” under Functional
Description section
– Updated "POWER DOWN (PDB) description under Functional Description from VDDIO to VDDIO = 3.0 to
3.6V or VDD33
– Updated “Figure 23. Typical Connection Diagram”
Aug 6, 2012
– Corrected Table 4: Configuration Select (MODE_SEL) #6 I2S Channel B (18–bit Mode) from L to H
– Corrected typo in table “DC and AC Serial Control Bus Characteristics” from VDDIO to VDD33
– Added Recommended FRC settings table
– Added “When backward compatible mode = ON, set LFMODE = 0” under Functional Description.
Reformatted Table 4 and added clarification to notes. Added clarification to notes on Table 9 Serial
Control Bus Registers, address 0x02[3:0] (backwards compatible and LFMODE registers).
– Added “Note: Do not enable SSCG feature if PCLK source into the SER has an SSC clock already.” under
Functional Description, EMI REDUCTION FEATURES, Spread Spectrum Clock Generation (SSCG)
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DS90UH926Q
www.ti.com
SNLS337J – OCTOBER 2010 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision I (April 2013) to Revision J
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 50
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51
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DS90UH926QSQ/NOPB
ACTIVE
WQFN
NKB
60
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UH926QSQ
DS90UH926QSQE/NOPB
ACTIVE
WQFN
NKB
60
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UH926QSQ
DS90UH926QSQX/NOPB
ACTIVE
WQFN
NKB
60
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UH926QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS90UH926QSQ/NOPB
Package Package Pins
Type Drawing
WQFN
NKB
60
DS90UH926QSQE/NOPB WQFN
NKB
DS90UH926QSQX/NOPB WQFN
NKB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
60
250
178.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
60
2000
330.0
16.4
9.3
9.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UH926QSQ/NOPB
WQFN
NKB
60
1000
367.0
367.0
38.0
DS90UH926QSQE/NOPB
WQFN
NKB
60
250
213.0
191.0
55.0
DS90UH926QSQX/NOPB
WQFN
NKB
60
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
NKB0060B
SQA60B (Rev B)
www.ti.com
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