PanelBus SLDS149 − AUGUST 2004 D Supports UXGA Resolution (Output Pixel D D D D D D Reduced Power Consumption From 1.8-V Rates up to 165 MHz) Digital Visual Interface (DVI) and High-Bandwidth Digital Content Protection (HDCP) Specification Compliant1 True-Color, 24 Bits/Pixel, 48-Bit Dual Pixel Output Mode, 16.7M Colors at 1 or 2 Pixels Per Clock Laser-Trimmed (50-Ω) Input Stage for Optimum Fixed Impedance Matching Skew Tolerant up to One Pixel Clock Cycle (High Clock and Data Jitter Tolerance) 4x Over-Sampling for Reduced Bit-Error Rates and Better Performance Over Longer Cables D D D D Core Operation With 3.3-V I/Os and Supplies2 Reduced Ground Bounce Using Time-Staggered Pixel Outputs Lowest Noise and Best Power Dissipation Using TI 100-Terminal TQFP PowerPAD Packaging Advanced Technology Using TI’s 0.18-µm EPIC-5 CMOS Process Embedded Preprogrammed High-Bandwidth Digital Content Protection (HDCP) Keys description The TFP503 is a Texas Instruments PanelBus flat-panel display product, part of a comprehensive family of end-to-end DVI 1.0-compliant solutions. Targeted primarily at desktop LCD monitors, DLP and LCD projectors, and digital TVs, the TFP503 finds applications in any design requiring high-speed digital interface with the additional benefit of an extremely robust and innovative encryption scheme for digital content protection. The TFP503 supports display resolutions up to UXGA, including the standard HDTV formats, in 24-bit true color pixel format. The TFP503 offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time-staggered pixel outputs for reduced ground-bounce. PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultra-low ground inductance. The TFP503 combines PanelBus circuit innovation and unique implementation for HDCP key protection with TI’s advanced 0.18-µm EPIC-5 CMOS process technology to achieve a completely secure, reliable, low-powered, low-noise, high-speed, digital interface solution. The TFP503 comes with embedded preprogrammed HDCP keys, thus eliminating the need for an external storage device to store the HDCP keys or the need for the customer to purchase HDCP keys from the licensing authority. An encryption scheme ensures that the embedded HDCP keys are encrypted, thus providing highest level of key security. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Footnotes: 1. The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high−speed digital connection to digital displays. The high−bandwidth digital content protection system (HDCP) is an industry standard for protecting DVI outputs from being copied. HDCP was developed by Intel Corporation and is licensed by the Digital Content Protection, LLC. The TFP503 is compliant to the DVI Rev. 1.0 and HDCP Rev. 1.0 specifications. 2. The TFP503 has an internal voltage regulator that provides the 1.8 V core power supply from the externally supplied 3.3 V supplies. PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments. Copyright 2004, Texas Instruments Incorporated !"# $% $ ! ! & ' $$ ()% $ !* $ #) #$ * ## !% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PanelBus SLDS149 − AUGUST 2004 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 QO22 QO21 QO20 QO19 QO18 QO17 QO16 DGND CAP QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 OGND OVDD QO7 QO6 QO5 QO4 QO3 QO2 TQFP PACKAGE (TOP VIEW) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DFO PD ST PIXS DGND DVDD STAG SCDT PDO QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 OVDD OGND QE8 QE9 QE10 QE11 QE12 QE13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 OGND QO23 OVDD AGND Rx2+ Rx2− AVDD Rx1+ Rx1− AVDD Rx0+ Rx0− AVDD RxC+ RxC− AVDD DDC_SCL DDC_SDA DDC_SA RCL RDA PVDD1 PGND PVDD2 OCK_INV 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QO1 QO0 HSYNC VSYNC DE OGND ODCK OVDD RSVD CTL2 CTL1 DGND DVDD QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 OVDD OGND QE15 QE14 PanelBus SLDS149 − AUGUST 2004 functional block diagram 3.3 V 3.3 V 1.8 V Regulator Internal 50 Ω Termination + _ Latch Channel 1 Rx1+ Rx1- + _ Rx0+ Rx0- + _ Latch RxC+ RxC- + _ PLL RCL RDA DDC_SCL DDC_SDA Latch Channel 0 Data Recovery and Synchronization Rx2+ Rx2- Channel 2 RED[7:0] RED[7:0] CH2[9:0] CTL2 CTL2 QE[23:0] QO[23:0] CH1[9:0] GRN[7:0] GRN[7:0] ODCK DE SCDT T.M.D.S. Decoder CTL1 BLU[7:0] VSYNC HSYNC CH0[9:0] Encrypted Embedded HDCP Keys Key Decryption I2C Slave I/F for DDC I2C Control Registers HDCP Decryption CTL1 Panel Interface BLU[7:0] VSYNC HSYNC CTL2 CTL1 VSYNC HSYNC RAM Block DDC_SA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PanelBus SLDS149 − AUGUST 2004 Terminal Functions TERMINAL NAME NO. AGND 79 AVDD 82, 85, 88, 91 CAP I/O DESCRIPTION Analog ground. Ground reference and current return for analog circuitry. Analog VDD. Power supply for analog circuitry. Nominally 3.3 V. 67 O Bypass capacitor. 4.7-µF tantalum and 0.01-µF ceramic capacitors connected to ground. CTL[2:1] 41, 40 O General-purpose control signals. Used for user-defined control. In normal mode, CTL1 is not powered down via PDO. DDC_SA 94 I Display data channel_serial address. I2C slave address bit A0 for display data channel (DDC). Refer to I 2C interface section for more details. DDC_SCL 92 I/O Display data channel_serial clock. I2C clock for the DDC. This terminal is 3.3-V tolerant and typically sinks 3 mA. External pullup resistors are required. A level translator must be used to interface to 5-V DDC lines. DDC_SDA 93 I/O Display data channel_serial data. I2C data for the DDC. This terminal is 3.3-V tolerant and typically sinks 3 mA. External pullup resistors are required. A level translator must be used to interface to 5-V DDC lines. DE 46 O Output data enable. Indicates time of active video display versus nonactive display or blanking interval. During blanking, only HSYNC, VSYNC, and CTL[2:1] are transmitted. During times of active display, or nonblanking, only pixel data, QE[23:0] and QO[23:0], is transmitted. High: active display interval Low: blanking interval DFO 1 I Output clock data format. Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support, the ODCK clock runs continuously. For DSTN support, the ODCK only clocks when DE is high; otherwise, ODCK is held low when DE is low. High: DSTN support/ODCK held low when DE is low. Low: TFT support/ODCK runs continuously. DGND 5, 39, 68 DVDD 6, 38 Digital ground. Ground reference and current return for digital core. Digital VDD. Power supply for digital core. Nominally 3.3 V. HSYNC 48 O Horizontal sync output OCK_INV 100 I ODCK polarity. Selects the ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL[2:1]) are latched. Normal mode: High: latches output data on rising ODCK edge. Low: latches output data on falling ODCK edge. ODCK 44 OGND 19, 28, 45, 58, 76 Output driver ground. Ground reference and current return for digital output drivers. OVDD 18, 29, 43, 57, 78 Output driver VDD. Power supply for output drivers. Nominally 3.3 V. PD 2 O I Output data clock. Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with DE, HSYNC, VSYNC, and CTL[2:1] are synchronized to this clock. Power down. An active low signal that controls the TFP503 power-down state. During power down, all output buffers are switched to a high-impedance state and brought low through a weak pulldown resistor. All analog circuits are powered down and all inputs are disabled, except for PD. If PD is left unconnected, an internal pullup resistor defaults the TFP503 to normal operation. High: normal operation Low: power down PDO 9 I Output drive power down. An active low signal that controls the power-down state of the output drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. A weak pulldown resistor slowly pulls these outputs to a low level. When PDO is left unconnected, an internal pullup resistor defaults the TFP503 to normal operation. High: normal operation/output drivers on Low: output drive power down 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 Terminal Functions (Continued) TERMINAL NAME NO. PGND 98 PIXS 4 I/O DESCRIPTION PLL ground. Ground reference and current return for internal PLL. I Pixel select. Selects between 1- or 2-pixel/clock output mode. During 2-pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel.) High: 2-pixel/clock mode Low: 1-pixel/clock mode PVDD (1, 2) QE[0:7] 97, 99 10−17 PLL VDD. Power supply for internal PLL. Nominally 3.3 V. O Even blue pixel output. Output for even and odd blue pixels when in 1-pixel/clock mode. Output for only even blue pixels when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE0 (terminal 10) MSB: QE7 (terminal 17) QE[8:15] 20−27 O Even green pixel output. Output for even and odd green pixels when in 1-pixel/clock mode. Output for only even green pixels when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE8 (terminal 20) MSB: QE15 (terminal 27) QE[16:23] 30−37 O Even red pixel output. Output for even and odd red pixels when in 1-pixel/clock mode. Output for only even red pixels when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE16 (terminal 30) MSB: QE23 (terminal 37) QO[0:7] 49−56 O Odd blue pixel output. Output for only odd blue pixels when in 2-pixel/clock mode. Not used and held low when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO0 (terminal 49) MSB: QO7 (terminal 56) QO[8:15] 59−66 O Odd green pixel output. Output for only odd green pixels when in 2-pixel/clock mode. Not used and held low when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO8 (terminal 59) MSB: QO15 (terminal 66) QO[16:23] 69−75, 77 O Odd red pixel output. Output for only odd red pixels when in 2-pixel/clock mode. Not used and held low when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO16 (terminal 69) MSB: QO23 (terminal 77) RCL RDA 95 96 I/O These terminals are the I2C interface to the internal HDCP key EEPROM. Each terminal requires a 10-kΩ pullup resistor connected to VDD. RSVD 42 O Reserved. Must be tied high for normal operation. Rx2+ 80 I Channel-2 positive receiver input. Positive side of channel-2 T.M.D.S. low-voltage signal differential input pair. Channel-2 receives red pixel data in active display and CTL2 control signals during blanking. Rx2− 81 I Channel-2 negative receiver input. Negative side of channel-2 T.M.D.S. low-voltage signal differential input pair. Rx1+ 83 I Channel-1 positive receiver input. Positive side of channel-1 T.M.D.S. low-voltage signal differential input pair. Channel-1 receives green pixel data in active display and CTL1 control signals during blanking. Rx1− 84 I Channel-1 negative receiver input. Negative side of channel-1 T.M.D.S. low-voltage signal differential input pair. Rx0+ 86 I Channel-0 positive receiver input. Positive side of channel-0 T.M.D.S. low-voltage signal differential input pair. Channel-0 receives blue pixel data in active display and HSYNC and VSYNC control signals during blanking. Rx0− 87 I Channel-0 negative receiver input. Negative side of channel-0 T.M.D.S. low-voltage signal differential input pair. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PanelBus SLDS149 − AUGUST 2004 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION RxC+ 89 I Clock positive receiver input. Positive side of reference clock T.M.D.S. low-voltage signal differential input pair. RxC− 90 I Clock negative receiver input. Negative side of reference clock T.M.D.S. low-voltage signal differential input pair. SCDT 8 O Sync detect. Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP503 monitors the state DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive. High: active link Low: inactive link ST 3 I Output drive strength select. Selects output drive strength for high- or low-current drive (see dc specifications for IOH(D) and IOL(D) vs ST state). High: high drive strength Low: low drive strength STAG 7 I Staggered pixel select. An active low signal used in 2-pixel/clock pixel mode (PIXS = high). Time staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. High: normal simultaneous even/odd pixel output Low: time-staggered even/odd pixel output VSYNC 47 O Vertical sync output absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, DVDD, AVDD, OVDD, PVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Input voltage, logic/analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C ESD protection, all terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Human Body Model JEDEC latch-up (EIA/JESD78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage, VDD (DVDD, AVDD, OVDD, PVDD) Pixel time, t(pixel) (see Note 1) MIN NOM MAX 3 3.3 3.6 V 40 ns 6.06 Single-ended analog input-termination resistance, RT (see Note 2) Operating free-air temperature, TA UNIT 45 50 55 Ω 0 25 70 °C NOTES: 1. t(pixel) is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK, is equal to t(pixel) when in 1-pixel/clock mode and 2 t(pixel) when in 2-pixel/clock mode. 2. The TFP503 is internally optimized using a laser-trim process to precisely fix the single-ended termination impedance, RT, to 50 Ω ±10%. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) dc digital I/O specifications PARAMETER TEST CONDITIONS VIH High-level digital input voltage (CMOS inputs) (see Note 3) VIL Low-level digital input voltage (CMOS inputs) (see Note 3) VOH High-level digital output voltage (see Note 4) VOL Low-level digital output voltage (see Note 4) IOH(D) High-level output drive current (see Note 4) IOL(D) Low-level output drive current (see Note 4) IIH IIL High-level digital input current (see Note 3) Low-level digital input current (see Note 3) MIN TYP MAX 0.7 VDD V 0.3 VDD DVDD = 3 V, ST = High, IOH = − 5 mA DVDD = 3 V, ST = Low, IOH = − 3 mA DVDD = 3.6 V, ST = High, IOL = 10 mA UNIT V 2.4 V 2.4 0.4 DVDD = 3.6 V, ST = Low IOL = 5 mA ST = High, VOH = 2.4 V 0.4 −5 −12 −18 ST = Low, VOH = 2.4 V ST = High, VOL = 0.4 V −3 −7 −12 10 13 19 ST = Low, VOL = 0.4 V VIH = DVDD 5 7 11 V mA mA ±20 µA ±60 µA ±20 µA MAX UNIT 150 1200 mV AVDD−0.3 AVDD−0.01 AVDD−0.037 AVDD+0.01 VIL = 0.0 V PD = Low or PDO = Low IOZ Hi-Z output leakage current NOTES: 3. Digital inputs are labeled I in I/O column of the Terminal Functions Table. 4. Digital outputs are labeled O in I/O column of the Terminal Functions Table. dc specifications PARAMETER TEST CONDITIONS VID(1) VIC Analog input differential voltage (see Note 5) VI(OC) Open circuit analog input voltage IDD(2PIX) Normal 2-pixel/clock power supply current (see Note 7) ODCK = 82.5 MHz 2-pixel/clock I(PD) I(PDO) Power-down current (see Note 6) PD = Low Output drive power-down current (see Note 6) PDO = Low Analog input common mode voltage (see Note 5) MIN TYP 35 V V 460 mA 10 mA mA NOTES: 5. Specified as dc characteristic with no overshoot or undershoot. 6. Analog inputs are open circuit (transmitter is disconnected from TFP503.) 7. Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and Q0[23:0] CL = 10 pF. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PanelBus SLDS149 − AUGUST 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) ac specifications PARAMETER VID(2) VID(3) TEST CONDITIONS Differential input sensitivity (see Note 8) MIN TYP 150 Analog input intra-pair (+ to −) differential skew (see Note 12) tsk(CC) Analog input inter-pair or channel-to-channel skew (see Note 12) 1560 mVp−p 0.4 t(bit)† ns 1.0 t(pixel)‡ ns Worst case differential input clock jitter tolerance (see Notes 9 and 12) 112 MHz, 1 pixel/clock Rise time of data and control signals (see Notes 10 and 11) ST = Low, CL = 10 pF ST = High, CL = 10 pF 1.9 tr(1) Fall time of data and control signals (see Notes 10 and 11) ST = Low, CL = 10 pF ST = High, CL = 10 pF 1.9 tf(1) Rise time of ODCK clock (see Note 10) ST = Low, CL = 10 pF ST = High, CL = 10 pF 1.9 tr(2) Fall time of ODCK clock (see Note 10) ST = Low, CL = 10 pF ST = High, CL = 10 pF 1.9 tf(2) tsu(1) th(1) Setup time, data, and control signals to falling edge of ODCK (see Note 11) Hold time, data, and control signals to falling edge of ODCK (see Note 11) 200 ps 1.9 1.9 1.9 1.9 1 pixel/clock PIXS = Low ST = Low CL = 10 pF 1.2 OCK_INV = Low ST = High CL = 10 pF 1.2 2 pixel/clock PIXS = High ST = Low CL = 10 pF 2.7 STAG = High OCK_INV = Low ST = High CL = 10 pF 2.7 2 pixel & STAG PIXS = High ST = Low CL = 10 pF 1.7 STAG = Low OCK_INV = Low ST = High CL = 10 pF 1.7 1 pixel/clock PIXS = Low ST = Low CL = 10 pF 0.9 OCK_INV = Low ST = High CL = 10 pF 0.9 2 pixel and STAG PIXS = High ST = Low CL = 10 pF 2.9 STAG = Low OCK_INV = Low ST = High CL = 10 pF 2.9 UNIT mVp−p Maximum differential input tsk(D) MAX ns ns ns ns ns ns ns ns ns † t(bit) is 1/10 the pixel time, t(pixel) ‡ t(pixel) is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t(pixel) in 1-pixel/clock mode or 2 t(pixel) when in 2-pixel/clock mode. NOTES: 8. Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection. 9. Measured differentially at 50% crossing using ODCK output clock as trigger. 10. Rise and fall times measured as time between 20% and 80% of signal amplitude. 11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]. 12. By characterization 13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 ac specifications (continued) PARAMETER tsu(2) th(2) f(ODCK) TEST CONDITIONS Setup time, data, and control signals to rising edge of ODCK (see Note 11) Hold time, data, and control signals to rising edge of ODCK (see Note 11) ODCK frequency 1 pixel/clock PIXS = Low ST = Low CL = 10 pF 1.9 OCK_INV = High ST = High CL = 10 pF 1.9 2 pixel/clock PIXS = High ST = Low CL = 10 pF 2.9 STAG = High OCK_INV = High ST = High CL = 10 pF 2.9 2 pixel & STAG PIXS = High ST = Low CL = 10 pF 2.0 STAG = Low OCK_INV = High ST = High CL = 10 pF 2.0 1 pixel/clock PIXS = Low ST = Low CL = 10 pF 0.5 OCK_INV = High ST = High CL = 10 pF 0.5 2 pixel & STAG PIXS = High ST = Low CL = 10 pF 1.4 STAG = Low OCK_INV = High ST = High CL = 10 pF 1.4 TYP MAX UNIT ns ns ns ns ns PIXS = Low 25 165 PIXS = High 12.5 82.5 ODCK duty cycle td(PDL) td(PDOL) MIN 40% 50% MHz 60% Delay from PD low to Hi-Z outputs 18 ns Delay from PDO low to Hi-Z outputs 18 ns t(HSC) Time between DE transitions to SCDT low (see Note 13) tt(FSC) Time from DE low to SCDT high (see Note 13) td(st) ODCK latching edge to QE[23:0] data output 165 MHz STAG = Low PIXS = High 25 ms 8 trans(DE)† 0.5 t(pixel) ns † trans(DE) is one transition (low-to-high or high-to-low) of the DE signal. NOTES: 11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]. 13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PanelBus SLDS149 − AUGUST 2004 timing diagrams tr(2) tf(2) 80% ODCK 20% tr(1) 80% 80% QE[23:0], QO[23:0], DE, CTL[2:1], HSYNC, VSYNC 20% tf(1) 80% 20% 20% Figure 2. Rise and Fall Time of Data and Control Signals Figure 1. Rise and Fall Time of ODCK f(ODCK) ODCK Figure 3. ODCK Frequency tsu(1) tsu(2) th(1) VOH VOL ODCK QE[23:0], QO[23:0], DE, CTL[2:1], HSYNC, VSYNC th(2) VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL OCK_INV Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK VOH ODCK tsk(D) td(st) QE[23:0] Tx+ 50% 50% Tx- Figure 5. ODCK High to QE[23:0] Staggered Data Output PD PDO VIL td(PDL) QE[23:0], QO[23:0], ODCK, DE, CTL[2:1], HSYNC, VSYNC, SCDT Figure 7. Delay From PD Low to Hi-Z Outputs 10 Figure 6. Analog Input Intra-Pair Differential Skew POST OFFICE BOX 655303 VIL td(PDOL) QE[23:0], QO[23:0], ODCK, DE, CTL[2:1], HSYNC, VSYNC Figure 8. Delay From PDO Low to Hi-Z Outputs • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 timing diagrams (continued) VIH PD DFO, ST, PIXS, STAG, Rx[2:0]+, Rx[2:0]−, OCK_INV td(PDLM) td(PDLA) PD Figure 10. Minimum Time PD Low Figure 9. Delay From PD Low to High Before Inputs Are Active TX2 VIL 50% TX1 tsk(CC) TX0 50% Figure 11. Analog Input Channel-to-Channel Skew t(HSC) t(FSC) DE SCDT Figure 12. Time Between DE Transitions to SCDT Low and SCDT High POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PanelBus SLDS149 − AUGUST 2004 fundamental operation The TFP503 is a DVI-compliant digital receiver that is used in digital display systems to receive and decode transition-minimized differential-signaling (T.M.D.S.) encoded RGB pixel data streams. High-bandwidth digital content protection (HDCP) receiver functionality provides decryption of the DVI input data streams encrypted at the transmitter, such as TI’s HDCP TFP510 or TFP513 transmitter, to prevent unauthorized viewing or copying of digital content. In a digital display system, a host, usually a PC or consumer electronics device, contains a DVI-compatible transmitter that receives 24-bit pixel data along with the appropriate control signals. The HDCP TFP510 or TFP513 transmitter encrypts and encodes the signals into a high-speed, low-voltage, differential serial bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, requires a DVI- and HDCP-compatible receiver like the TI TFP503 to decode and decrypt the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to five meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions up to UXGA, a high-bandwidth receiver with good jitter and skew tolerance is required. The TFP503 incorporates high-bandwidth digital content protection (HDCP). This provides secure data transmission for high-definition video. The TFP503 comes with embedded preprogrammed HDCP keys, thus eliminating the need both for an external storage device to store the HDCP keys and for the customer to purchase HDCP keys from the licensing authority. An encryption scheme ensures that the embedded HDCP keys are encrypted, thus providing highest level of key security. T.M.D.S. pixel data and control signal encoding Only one of two possible T.M.D.S. characters for a given pixel is transmitted at a given time. The transmitter keeps a running count of the number of 1s and 0s previously sent, transmits the character that minimizes the number of transitions, and approximates a dc balance of the transmission line. Three T.M.D.S. channels receive RGB pixel data during active display time, DE = high. These same three channels also receive HSYNC, VSYNC, CTL3, and two user-definable control signals, CTL[2:1], during inactive display or blanking interval (DE = low). The following table maps the received input data to the appropriate T.M.D.S. input channel in a DVI-compliant system. RECEIVED PIXEL DATA ACTIVE DISPLAY DE = HIGH OUTPUT TERMINALS (VALID FOR DE = HIGH) T.M.D.S. INPUT CHANNEL Red[7:0] Channel-2 (Rx2 ±) QE[23:16] QO[23:16] Green[7:0] Channel-1 (Rx1 ±) QE[15:8] QO[15:8] Blue[7:0] Channel-0 (Rx0 ±) QE[7:0] QO[7:0] RECEIVED CONTROL DATA BLANKING DE = LOW OUTPUT TERMINALS (VALID FOR DE = LOW) T.M.D.S. INPUT CHANNEL CTL[3:2] (see Note 14) Channel-2 (Rx2 ±) CTL2 CTL[1:0] (see Note 14) Channel-1 (Rx1 ±) CTL1 HSYNC, VSYNC Channel-0 (Rx0 ±) HSYNC, VSYNC NOTE 14: Some DVI transmitters transmit a CTL0 signal. The TFP503 decodes and transfers CTL[2:1] and ignores CTL0 characters. CTL3 is used internally to enable HDCP decryption. CTL3 and CTL0 are not available as TFP503 outputs. The TFP503 discriminates between valid pixel T.M.D.S. characters and control T.M.D.S. characters to determine the state of active display vs blanking, i.e., state of DE. high-bandwidth digital content protection (HDCP) overview TI’s HDCP transmitters and receivers use up to three cipher engines to protect information that may be externally accessible to the user. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 high-bandwidth digital content protection (HDCP) overview (continued) The downstream encryption described in the specification High-bandwidth Digital Content Protection System Specification (Revision 1.0) protects video data passing from the HDCP transmitter to the HDCP receiver via a DVI link. The HDCP transmitter encrypts video data and the receiver decrypts the data as shown in Figure 13. The HDCP keys must also be protected from access. An encryption scheme protects the HDCP device key values passing from an embedded EEPROM to the HDCP receiver via a dedicated I2C interface. When the HDCP device keys are needed, the encrypted values are read from the EEPROM, decrypted, and then enable HDCP functionality. Although external pullup resistors are required for the I2C interface, the key data on the interface is encrypted. TI’s HDCP solution provides real advantages with respect to lower systems-level cost, ease of implementation, high performance, and exceptional security. S/W Application Program Encrypted Keys A Keys and KSV PROM I2C Input Stream T.M.D.S. Encode Clock Channel 0 Output Stream Key Decrypt Channel 2 Channel 1 Encrypted Keys B Keys and KSV I2C T.M.D.S. Decode HDCP Encrypt Pixel Data PROM HDCP Encrypted TMDS Link Key Decrypt DE CPU and North Bridge and Graphics Controller TFP503 DVI-HDCP RX (Display’s DVI Input) DE HDPC Decrypt TFP510 or TFP513 DVI-HDCP TX (PC’s DVI Output) Channel C Pixel Data Clock I2C Slave Interface I2C Slave Interface I2C I2C Control and Authentication and Key Exchange EDID PROM KSV = Key Selection Vector Figure 13. TI’s HDCP Implementation for PC and Display System TFP503 clocking and data synchronization The TFP503 receives a clock reference from the DVI transmitter, such as the TFP510 or TFP513, that has a period equal to the pixel time, t(pixel). The frequency of this clock is also referred to as the pixel rate. Since the T.M.D.S. encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the required pixel rate to support an UXGA resolution with 60-Hz refresh rate is 165 MHz. The T.M.D.S. serial bit rate is 10x the pixel rate or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream on three separate channels (or twisted-pair wires) of long distances (3 to 5 meters), phase synchronization between the data steams and the input reference clock is not assured. In addition, skew between the three data channels is common. The TFP503 uses a 4x oversampling scheme of the input data streams to achieve reliable synchronization with up to 1-T(pixel) channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of high-speed serial data transmission. The TFP503 is designed for high jitter tolerance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PanelBus SLDS149 − AUGUST 2004 TFP503 clocking and data synchronization (continued) The input clock to the TFP503 is conditioned by a PLL (phase-locked-loop) to remove high frequency jitter from the clock. The PLL provides four 10x clock outputs of different phases to locate and sync the T.M.D.S. data streams (4x oversampling). During the active display interval, the pixel data is encoded to be transition minimized; whereas, during the blanking interval, the control data is encoded to be transition maximized. A DVI-compliant transmitter is required to transmit during the blanking interval for a minimum period of time, 128-t(pixel), to ensure sufficient time for data synchronization when the receiver sees a transition-maximized code. Performing synchronization during the blanking interval, when the data is transition maximized, assures reliable data bit boundary detection. Phase synchronization to the data streams is unique for each of the three input channels and is maintained as long as the link remains active. TFP503 T.M.D.S. input levels and input impedance matching The T.M.D.S. inputs to the TFP503 receiver have a fixed single-ended input termination impedance to AVDD. The TFP503 is internally optimized using a laser-trim process to precisely fix the single-ended termination impedance at 50 Ω. This fixed impedance eliminates the need for external termination resistors while providing optimum impedance matching to standard DVI cables having a characteristic impedance of 100 Ω. Figure 14 shows a conceptual schematic of a TFP510 or TFP513 transmitter and TFP503 receiver connection. The TFP510 or TFP513 transmitter drives the twisted-pair cable via a current source, usually achieved with an open-drain output driver. The internal single-ended termination resistors, which are matched to the characteristic impedance of the DVI cable, provide a pullup to AVDD. Naturally, when the transmitter is disconnected and the TFP503 DVI inputs are left unconnected, the TFP503 receiver inputs are pulled up to AVDD. The single-ended differential signal and full differential signal are shown in Figure 15. The TFP503 is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with common mode voltages ranging from (AVDD−300 mV) to (AVDD−37 mV). TI TFP510 or TFP513 Transmitter TI TFP503 Receiver AVCC DVI-Compliant Cable Internal Termination at 50 Ω DATA DATA + _ Current Source Figure 14. T.M.D.S. Differential Input and Transmitter Connection VID AVCC 1/2 VID AVCC - 1/2 VID + 1/2 VID - 1/2 VID b) Differential Input Signal a ) Single-Ended Input Signal Figure 15. T.M.D.S. Inputs 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 TFP503 modes of operation The TFP503 provides system design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. The following table outlines the various panel modes that can be supported along with appropriate external control pin settings. PANEL PIXEL RATE ODCK LATCH EDGE ODCK DFO PIXS OCK_INV TFT or 16-bit DSTN 1 pixel/clock Falling Free run 0 0 0 TFT or 16-bit DSTN 1 pixel/clock Rising Free run 0 0 1 TFT 2 pixel/clock Falling Free run 0 1 0 TFT 2 pixel/clock Rising Free run 0 1 1 24-bit DSTN 1 pixel/clock Falling Gated low 1 0 0 None 1 pixel/clock Rising Gated low 1 0 1 24-bit DSTN 2 pixel/clock Falling Gated low 1 1 0 24-bit DSTN 2 pixel/clock Rising Gated low 1 1 1 TFP503 output driver configurations The TFP503 provides flexibility by offering various output driver features that can be used to optimize power consumption, ground bounce, and power-supply noise. The following sections outline the output driver features and their effects. Output driver power down (PDO = low.) Pulling PDO low places all the output drivers, except CTL1 and SCDT, into a high-impedance state. A weak pulldown (approximately 10 µA) gradually pulls these high-impedance outputs to a low level to prevent the outputs from floating. The SCDT output, which indicates a link-disabled or link-inactive state, can be tied directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. An internal pullup resistor on the PDO terminal defaults the TFP503 to the normal nonpower-down output drive mode if left unconnected. Drive strength (ST = high for high drive strength, ST = low for low drive strength.) The TFP503 allows for selectable output drive strength on the data, control, and ODCK outputs. See the dc specifications table for the values of IOH(D) and IOL(D) current drives for a given ST state. The high output strength offers approximately two times the drive as the low output drive strength does. Time-staggered pixel output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high.) Setting STAG = low will time-stagger the even and odd pixel outputs so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design, this can help reduce the amount of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even pixel is delayed from the latching edge of ODCK by 0.25 T(ODCK). (T(ODCK) is the period of ODCK. The ODCK period is 2 t(pixel) when in 2-pixel/clock mode.) Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP503 drive strength and staggered pixel options allow flexibility to reduce system power supply noise, ground bounce, and EMI. Power management. The TFP503 offers several system power-management features. The output driver power-down (PDO = low) mode is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 are driven to a high-impedance state while the rest of the device circuitry remains active. The TFP503 power down (PD = low) is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers are placed into a high-impedance state. All inputs are disabled except for the PD input. The TFP503 does not respond to any digital or analog inputs until PD is pulled high. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 PanelBus SLDS149 − AUGUST 2004 TFP503 output driver configurations (continued) Both PDO and PD have internal pullup resistors; so, if left unconnected, they default the TFP503 to normal operating modes. Sync detect. The TFP503 offers an output, SCDT, to indicate link activity. The TFP503 monitors activity on DE to determine if the link is active. When 1 million pixel clock periods pass without a transition on DE, the TFP503 considers the link inactive and SCDT is driven low. SCDT goes high immediately after the first eight transitions on DE. SCDT again goes low when no more transitions are seen after 218 oscillator clocks. SCDT can signal a system power-management circuit to initiate a system power down when the link is considered inactive. The SCDT can also be tied directly to the TFP503 PDO input to power down the output drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in complete power down, the analog inputs are ignored and the SCDT state does not change. An external system power management circuit to drive PD is preferred. HDCP register map The TFP503 is a standard I2C slave device. All the registers can be written and read through the I2C interface. The I2C base address of the TFP503 is dependent on terminal 94 (DDC_SA) as shown below. TERMINAL 94 WRITE ADDRESS (HEX) READ ADDRESS (HEX) 0 74 75 1 76 77 I2C register map BKSV Subaddress = 00 7 6 5 Read Only 4 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 BKSV[7:0] Subaddress = 01 7 6 5 Read Only 4 BKSV[15:8] Subaddress = 02 7 6 5 Read Only 4 BKSV[23:16] Subaddress = 03 7 6 5 Read Only 4 BKSV[31:24] Subaddress = 04 7 6 5 Read Only 4 BKSV[39:32] 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 I2C register map (continued) Video receiver KSV. This value may be used to determine that the video receiver is HDCP capable. Valid KSVs contain 20 ones and 20 zeros, a characteristic that is verified by video transmitter hardware before encryption is enabled. Ri’ Subaddress = 08 7 6 5 Read Only 4 3 2 1 0 3 2 1 0 Ri’ [7:0] Subaddress = 09 7 6 5 Read Only 4 Ri’ [15:8] Link verification response. Updated every 128th frame. It is recommended that graphics systems protect against errors in the I2C transmission by re-reading this value when unexpected values are received. This value is available at all times between updates. AKSV Subaddress = 10 7 6 5 Read/Write 4 Default = 00 3 2 1 0 1 0 1 0 1 0 1 0 AKSV[7:0] Subaddress = 11 7 6 5 Read/Write 4 Default = 00 3 2 AKSV[15:8] Subaddress = 12 7 6 5 Read/Write 4 Default = 00 3 2 AKSV[23:16] Subaddress = 13 7 6 5 Read/Write 4 Default = 00 3 2 AKSV[31:24] Subaddress = 14 7 6 5 Read/Write 4 Default = 00 3 2 AKSV[39:32] Video transmitter KSV. Writing to 0x14 triggers the authentication sequence in the device. An Subaddress = 18 7 6 5 Read/Write 4 Default = 00 3 2 1 0 1 0 1 0 An[7:0] Subaddress = 19 7 6 5 Read/Write 4 Default = 00 3 2 An[15:8] Subaddress = 1A 7 6 5 Read/Write 4 Default = 00 3 2 An[23:16] POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PanelBus SLDS149 − AUGUST 2004 I2C register map (continued) Subaddress = 1B 7 6 5 Read/Write Default = 00 4 3 2 1 0 1 0 1 0 1 0 1 0 An[31:24] Subaddress = 1C 7 6 5 Read/Write Default = 00 4 3 2 An[39:32] Subaddress = 1D 7 6 5 Read/Write Default = 00 4 3 2 An[47:40] Subaddress = 1E 7 6 5 Read/Write Default = 00 4 3 2 An[55:48] Subaddress = 1F 7 6 5 Read/Write Default = 00 4 3 2 An[63:56] Session random number. This multibyte value must be written by the graphics system before the KSV is written. Bcaps Subaddress = 40 Read Only Default = 10 7 6 5 4 3 2 1 0 Rsvd Repeater KSV-FIFO Fast Rsvd Rsvd Rsvd Rsvd Bit 6: REPEATER, Video repeater capability. This device is not a repeater. Read as 0. Bit 5: READY, KSV FIFO ready. This device does not support repeater capability. Read as 0. Bit 4: FAST. This device supports 400-kHz transfers. Read as 1. Bstatus 7 Subaddress = 41 6 5 Read Only 4 Default = 00 3 2 1 0 1 0 1 0 Bstatus[7:0] Subaddress = 42 7 6 5 Read Only 4 Default = 00 3 2 Bstatus[15:8] Bstatus. This device does not support repeater capability. All bytes read as 0x00. KSV_FIFO 7 Subaddress = 43 6 5 Read Only 4 Default = 00 3 2 KSV_FIFO Key selection vector FIFO. This device is not a repeater. All bytes read as 0x00. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 I2C register map (continued) VEN_ID Subaddress = C0 7 6 Read Only 5 4 Default = 4C 3 2 1 0 1 0 VEN_ID[7:0] Subaddress = C1 6 7 Read Only 5 4 Default = 01 3 2 VEN_ID[15:8] This read-only register contains the 16-bit Texas Instruments vendor ID for the TFP503. VEN_ID[15:0] is hardwired to 0x014C. DEV_ID Subaddress = C2 6 7 Read Only 5 4 Default = 01 3 2 1 0 1 0 DEV_ID[7:0] Subaddress = C3 6 7 Read Only 5 4 Default = 05 3 2 DEV_ID[15:8] This read-only register contains the 16-bit device ID for the TFP503. DEV_ID[15:0] is hardwired to 0x0501. REV_ID Subaddress = C4 7 6 Read Only 5 4 Default = 01 3 2 1 0 REV_ID[7:0] This read-only register contains the 8-bit revision ID for the TFP503. REV_ID[7:0] is hardwired to 0x01. I2C interface The I2C interface accesses the internal TFP503 registers. This two-terminal interface consists of one clock line, DDC_SCL, and one serial data line, DDC_SDA. The basic I2C access cycles are shown in Figures 16 and 17. DDC_SDA DDC_SCL Start Condition (S) Stop Condition (P) Figure 16. I2C Start and Stop Conditions The basic access cycle consists of the following: D D D D D A start condition A slave address cycle A subaddress cycle Any number of data cycles A stop condition POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 PanelBus SLDS149 − AUGUST 2004 I2C interface (continued) The start and stop conditions are shown in Figure 16. The high-to-low transition of DDC_SDA while DDC_SCL is high defines the start condition. The low-to-high transition of DDC_SDA while DDC_SCL is high defines the stop condition. Each cycle (data or address) consists of 8 bits of serial data followed by 1 acknowledge bit generated by the receiving device. Thus, each data/address cycle contains 9 bits as shown in Figure 17. 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 DDC_SCL DDC_SDA Stop MSB Slave Address Sub Address Data Figure 17. I2C Access Cycles Following a start condition, each I2C device decodes the slave address. The TFP503 responds with an acknowledge by pulling the DDC_SDA line low during the ninth clock cycle if it decodes the address as its address. During subsequent subaddress and data cycles, the TFP503 responds with an acknowledge as shown in Figure 18. The subaddress is autoincremented after each data cycle. The transmitting device must not drive the DDC_SDA signal during the acknowledge cycle so that the receiving device may drive the DDC_SDA signal low. The not acknowledge, A, condition is indicated by the master by keeping the DDC_SDA signal high just before it asserts the stop, P, condition. This sequence terminates a read cycle as shown in Figure 19. The slave address consists of 7 bits of address along with 1 bit of read/write information as shown below in Figures 18, 19, and 20. For the TFP503, the possible slave addresses (including the R/W bit) are 0x74, 0x76 for write cycles and 0x75 and 0x77 for read cycles. Refer to the register map section for additional base address information. In order to minimize the number of bits that must be transferred for the link integrity check, a second read format is supported. This format, shown in Figure 20, has an implicit subaddress equal to 0x08, the starting location of Ri’. S Slave Address W From Transmitter From Receiver A Sub Address A A S Acknowledge Start Condition P Stop Condition W Write Data Figure 18. I2C Write Cycle 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A Data A P PanelBus SLDS149 − AUGUST 2004 I2C interface (continued) S Slave Address W A From Transmitter From Receiver A Sub Address A A S Acknowledge Start Condition P Stop Condition Sr Slave Address W R R A Data A Data A P Write Read Sr Restart Condition Not Acknowledge (SDA High) Figure 19. I2C Read Cycle S Slave Address R A From Transmitter From Receiver A Data A Data A S Acknowledge Start Condition P Stop Condition R Read A P Not Acknowledge (SDA High) Figure 20. HDCP Port Link Integrity Message Read The DDC_SDA and DDC_SCL I2C interface is 3.3-V tolerant and both DDC_SDA and DDC_SCL require a level shifter for connection to the external system 5-V DDC lines. The I2C SDA driver must provide the 0.4-V maximum low level at 3 mA specified by the I2C specification under typical conditions. Stressed conditions can make the output level marginal. The level shifter design must minimize loading and losses to provide the best possible low level signal on the SDA line. PowerPAD 100-terminal TQFP package The TFP503 is packaged in TI’s thermally enhanced PowerPAD 100-terminal TQFP packaging. The PowerPAD package is a 14-mm × 14-mm × 1-mm TQFP outline with 0.5-mm lead-pitch. The PowerPAD package has a specially designed die-mount pad that offers improved thermal capability over typical TQFP packages of the same outline. The TI 100-terminal TQFP PowerPAD package offers a backside solder plane that connects directly to the die-mount pad for enhanced thermal conduction. If traces or vias are located under the back side pad, they must be protected by a suitable solder mask or other assembly technique to prevent inadvertent shorting to the exposed backside pad. Soldering the backside of the device to a thermal land connected to the PCB ground plane is recommended for thermal, electrical, and EMI considerations. The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques. The recommended pad size for the grounded thermal land is 5.8 mm minimum, centered in the device land pattern. When vias are required to ground the land, multiple vias are recommended for a low-impedance connection to the ground plane. Multiple vias are also recommended when thermal flow from the land to another plane is needed. Vias in the exposed pad must be small enough or filled to prevent wicking the solder away from the interface between the package body and the thermal land on the surface of the board during solder reflow. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 PanelBus SLDS149 − AUGUST 2004 Thermal Vias 5.8 mm SQ Minimum Figure 21. Recommended Thermal Land Size More information on this package and other requirements for using thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web pages beginning at URL: http://www.ti.com The following table outlines the thermal properties of the TI 100-terminal TQFP PowerPAD package. Table 1. TI 100-Terminal TQFP (14 × 14 × 1 mm)/0.5-mm Lead Pitch PARAMETER RθJA PowerPAD NOT CONNECTED TO PCB THERMAL PLANE PowerPAD CONNECTED TO PCB THERMAL PLANE (see Note 15) 73.7°C/W 22.5°C/W Junction-to-ambient thermal resistance (see Notes 15, 16, 17, and 18) PD Package power dissipation (see Notes 15, 16, 17, and 18) 1.08 W 3.55 W NOTES: 15. Specified with the PowerPAD bond pad on the backside of the package soldered to a 2 oz Cu plate PCB thermal plane. 16. Airflow is at 0 LFM (no airflow). 17. Specified at 150°C junction temperature and 70°C ambient temperature. 18. It is recommended that the power pad of the device must be connected to the PCB thermal plane for improved thermal performance. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PanelBus SLDS149 − AUGUST 2004 THERMAL PAD MECHANICAL DATA PowerPADt PLASTIC QUAD FLATPACK PZP (S−PQFP−G100) PowerPAD is a trademark of Texas Instruments. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 PanelBus SLDS149 − AUGUST 2004 MECHANICAL DATA PZP (S-PQFP-G100) PowerPAD PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 50 76 Thermal Pad (see Note D) 26 100 0,13 NOM 1 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,25 0,15 0,05 1,05 0,95 0°−ā 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4146929/A 04/99 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026 PowerPAD is a trademark of Texas Instruments. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TFP503PZP ACTIVE HTQFP PZP Pins Package Eco Plan (2) Qty 100 90 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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