SDZS008 − JANUARY 1990 − REVISED OCTOBER 1990 • • • • • • OR NT PACKAGE 100K Compatible (T0P VIEW) Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers ECL and TTL Output-Enable Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise Package Options Include “Small Outline” Packages and Standard Plastic 300-mil DIPs Y1 Y2 Y3 Y4 1 24 2 23 3 22 4 21 VCC GND GND GND Y5 Y6 Y7 Y8 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 A1 A2 A3 A4 OE2 (TTL) VEE GND OE1 (ECL) A5 A6 A7 A8 description This octal ECL-to-TTL translator is designed to provide efficient translation between a 100K signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters while eliminating the need for three-state overlap protection. Two pins OE1 and OE2 are provided for output-enable control. These control inputs are ANDed together with OE1 being ECL-compatible and OE2 being TTL-compatible. This offers the choice of controlling the outputs of the device from either a TTL or ECL signal environment. The SN100KT5539 is characterized for operation from 0°C to 85°C. FUNCTION TABLE OUTPUT DATA OUTPUT ENABLE INPUT (TTL) OE1 OE2 A Y H X X H X H X H L L L L L L H H Copyright 1990, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SDZS008 − JANUARY 1990 − REVISED OCTOBER 1990 logic symbol† OE1 OE2 17 logic diagram (positive logic) ECL/TTL & A1 24 ECL/TTL 1 ECL/TTL 2 ECL/TTL 3 ECL/TTL 4 EN 20 23 A2 A1 24 23 A2 22 A3 21 A4 16 A5 15 A6 14 A7 13 A8 ECL/TTL 1 Y1 2 Y2 3 Y3 4 Y4 9 Y5 10 Y6 11 Y7 12 Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. A3 A4 OE1 (ECL) OE2 (TTL) A5 22 21 17 16 15 A8 Y2 Y3 Y4 ECL/TTL 20 A6 A7 Y1 14 13 ECL/TTL 9 ECL/TTL 10 ECL/TTL 11 ECL/TTL 12 Y5 Y6 Y7 Y8 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V to 0 V Input voltage range: TTL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V ECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V Input current range: TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SDZS008 − JANUARY 1990 − REVISED OCTOBER 1990 recommended operating conditions MIN NOM MAX VCC VEE TTL supply voltage 4.5 5 5.5 V ECL supply voltage −4.2 −4.5 −4.8 V VIH VIL TTL high-level input voltage VIH VIL ECL high-level input voltage† ECL low-level input voltage† VOH IOL TTL high-level output voltage 5.5 V TTL low-level output current 48 mA 2 UNIT V TTL low-level input voltage 0.8 V −1150 −840 mV −1810 −1490 mV IIK TTL input clamp current −18 mA TA Operating free-air temperature range 0 85 °C † The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK IOH TEST CONDITIONS MIN TYP‡ MAX UNIT VCC = 4.5 V, VCC = 4.5 V, VEE = − 4.2 V, VEE = − 4.2 V, II = − 18 mA VOH = 5.5 V VCC = 4.5 V, VCC = 5.5 V, VEE = − 4.5 V ± 0.3 V, VEE = − 4.8 V, IOL = 48 mA VI = 7 V VCC = 5.5 V, VCC = 5.5 V, VEE = − 4.8 V, VEE = − 4.8 V, VI = 2.7 V VI = − 840 mV VCC = 5.5 V, VCC = 5.5 V, VEE = − 4.8 V, VEE = − 4.8 V, VI = 0.5 V VI = − 1810 mV VCC = 5.5 V, VCC = 5.5 V, VEE = − 4.8 V VEE = − 4.8 V 63 VCC = 5.5 V, VCC = 5 V, VEE = − 4.2 V VEE = − 4.5 V 6 pF Co VCC = 5 V, VEE = − 4.5 V ‡ All typical values are at VCC = 5 V, VEE = − 4.5 V, TA = 25°C. 5 pF VOL II OE2 only OE2 only OE2 only IIH A inputs and OE1 OE2 only IIL ICCH ICCL IEE Ci A inputs and OE1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.38 −1.2 V 250 µA 0.55 V 0.1 mA 20 µA 350 µA −0.5 mA 91 mA 79 114 mA −22 −32 mA µA 0.5 3 SDZS008 − JANUARY 1990 − REVISED OCTOBER 1990 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM TO (INPUT) (OUTPUT) CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω TYP† MAX UNIT MIN tPLH tPHL Any A Y tPLH tPHL OE1 (ECL) Y tPLH tPHL OE2 (TTL) Y All typical values are at VCC = 5 V, VEE = − 4.5 V, TA = 25°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6.2 9.3 12.4 2.6 4.9 7.3 7.1 10.3 13.5 3.2 5.8 8.4 6.5 9.5 12.4 2.7 5.3 8 ns ns ns SDZS008 − JANUARY 1990 − REVISED OCTOBER 1990 PARAMETER MEASUREMENT INFORMATION 7V R1 From Output Under Test Test Point R2 CL (See Note A) LOAD CIRCUIT tr 3V Input (See Note B) 1.5 V 1.5 V Input (See Note C) 0 tPHL tPLH VOH In-Phase Output 1.5 V 1.5 V 20% tf 80% 50% 80% 50% tPLH −950 mV 20% −1690 mV tPHL VOH In-Phase Output 1.5 V 1.5 V VOL VOL tPLH tPHL VOH Out-of-Phase Output 1.5 V 1.5 V tPLH tPHL VOH Out-of-Phase Output 1.5 V VOL VOL TTL-INPUT PROPAGATION DELAY TIMES 1.5 V ECL-INPUT PROPAGATION DELAY TIMES NOTES: A.CL includes probe and jig capacitance. B. For TTL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 0.7 ns, tf ≤ 0.7 ns. D. The outputs are measured one at a time with one transition per measurement. FIGURE 1. LOAD CIRCUIT AND VOLTAGE WAVEFORMS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN100KT5539DW OBSOLETE SOIC DW 24 TBD Call TI Call TI SN100KT5539NT OBSOLETE PDIP NT 24 TBD Call TI Call TI SN100KT5539NT OBSOLETE PDIP NT 24 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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