APL3205A/B Li+ Charger Protection IC Features General Description • Input Over-Voltage Protection • Programmable Input Over-Current Protection The APL3205A/B provide completed Li+ charger protections against over-voltage, over-current, and battery over- • Battery Over-Voltage Protection • • Over-Temperature Protection High Immunity of False Triggering • High Accuracy Protection Thresholds • Fault Status Indication • Enable Input • Available in TDFN2x2-8 Package • Lead Free and Green Devices Available voltage. The IC is designed to monitor input voltage, input current, and battery voltage. When any of the monitored parameters are over the threshold, the IC removes the power from the charging system by turning off an internal switch. All protections also have deglitch time against false triggering due to voltage spikes or current transients. The APL3205A/B also provide over-temperature protection, a FAULT output pin to indicate the fault conditions, and the EN pin to allow the system to disable the IC. (RoHS Compliant) Pin Configuration Applications • Smart Phones and PDAs • Digital Still Cameras • Portable Devices IN 1 8 OUT GND 2 7 ILIM PSW 3 6 BAT FAULT 4 5 EN TDFN2x2-8 (Top View) Simplified Application Circuit 5V Adapter or USB Charger Input IN OUT APL3205A/B EN FAULT PSW ILIM Charger Output and System BAT GND Li+ Battery ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 1 www.anpec.com.tw APL3205A/B Ordering and Marking Information APL3205A APL3205B Package Code QB : TDFN2x2-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code APL3205A QB: L05A X X - Date Code APL3205B QB: L05B X X - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol (Note 1) Rating Unit VIN IN Input Voltage (IN pin to GND) -0.3 to 30 V VOUT, VBAT OUT, BAT Pins to GND Voltage -0.3 to 7 V ILIM, FAULT, EN, PSW, Pins to GND Voltage -0.3 to 7 V VILIM, VFAULT , VEN , VPSW IOUT TJ Parameter OUT Output Current 2 Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature,10 Seconds A 150 o -65 to 150 o 260 o C C C Note 1 : Stresses beyond the absolute maximum rating may damage the device and exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Typical Value Unit θJA Junction to Ambient Thermal Resistance in Free Air TDFN2x2-8 80 °C/W Range Unit 4.5 to 5.5 V Recommended Operating Conditions Symbol Parameter VIN IN Input Voltage IOUT OUT Output Current 0 to 1.5 A TJ Junction Temperature -40 to 125 °C TA Ambient Temperature -40 to 85 °C Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 2 www.anpec.com.tw APL3205A/B Electrical Characteristics Refer to the typical application circuit. These specifications apply over VIN=5V, TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Test Conditions APL3205A/B Unit Min. Typ. Max. 2.5 - 2.8 V - 230 - mV POWER-ON-RESET (POR) AND SUPPLY CURRENT VPOR IN POR Threshold VIN rising IN POR Hysteresis ICC TB(IN) IN Supply Current Input Power-On Blanking Time EN = Low - 250 350 EN = High - 100 150 VIN rising to VOUT rising - 8 - ms µA INTERNAL POWER SWITCH AND OUT DISCHARGE RESISTANCE Power Switch On Resistance IOUT = 0.5A - 250 450 mΩ OUT Discharge Resistance VOUT = 3V - 500 - Ω APL3205A, VIN rising 5.67 5.85 6.00 APL3205B, VIN rising 6.60 6.80 7.00 Input OVP Recovery Hysteresis - 200 - Input OVP Propagation Delay - - 1 µs Input OVP Recovery Time - 8 - ms INPUT OVER-VOLTAGE PROTECTION (OVP) VOVP TON(OVP) Input OVP Threshold V mV OVER-CURRENT PROTECTION (OCP) IOCP OCP Threshold RILIM = 25kΩ 930 1000 1200 mA OCP Threshold Accuracy IOCP = 300mA to 1500mA -10 - +10 % TB(OCP) OCP Blanking Time - 176 - µs TON(OCP) OCP Recovery Time - 64 - ms 4.30 4.35 4.4 V - 270 - mV - - 20 nA - 176 - µs 1.4 - - V BATTERY OVER-VOLTAGE PROTECTION VBOVP Battery OVP Threshold VBAT rising Battery OVP Hysteresis IBAT TB(BOVP) BAT Pin Leakage Current VBAT = 4.4V Battery OVP Blanking Time EN LOGIC LEVELS EN Input Logic High EN Input Logic Low - - 0.4 V EN Internal Pull-Low Resistor - 500 - kΩ FAULT LOGIC LEVELS AND DELAY TIME FAULT Output Low Voltage Sink 5mA current - - 0.4 V FAULT Pin Leakage Current VFAULT = 5V - - 1 µA Over-Temperature Threshold - 140 - °C Over-Temperature Hysteresis - 20 - °C OVER-TEMPERATURE PROTECTION (OTP) TOTP PSW LOGIC LEVELS PSW Output Low Threshold VIN rising, VOUT - VBAT 50 100 150 mV PSW Output High Threshold VIN falling, VOUT - VBAT 20 50 80 mV Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 3 www.anpec.com.tw APL3205A/B Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over VIN=5V, TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Test Conditions APL3205A/B Min. Typ. Max. Unit PSW LOGIC LEVELS (CONT.) TD(PSW) PSW Source Current VPSW = 2.5V - 2.5 - mA PSW Sink Current VPSW = 2.5V - 5 - mA PSW Low Delay Time VIN rising, VOUT - VBAT - 1 - ms Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 4 www.anpec.com.tw APL3205A/B Typical Operating Characteristics Input OVP Threshold vs. Junction Temperature Input OVP Threshold vs. Junction Temperature 6.00 7.00 5.95 Input OVP Threshold , VOVP (V) Input OVP Threshold , VOVP (V) APL3205A 5.90 5.85 VIN Increasing 5.80 5.75 5.70 VIN Decreasing 5.65 5.60 5.55 APL3205B 6.95 6.90 6.85 VIN Increasing 6.80 6.75 6.70 6.65 VIN Decreasing 6.60 6.55 6.50 -50 -25 0 25 50 75 100 125 -50 -25 Junction Temperature (oC) Battery OVP Threshold vs. Junction Temperature 50 75 100 125 1200 1150 4.35 VBAT Increasing 4.30 OCP Threshold, IOCP (mA) Battery OVP Threshold, VBOVP (V) 25 OCP Threshold vs. Junction Temperature 4.40 4.25 4.20 4.15 4.10 VBAT Decreasing 4.05 1100 1050 1000 950 900 850 800 4.00 -50 -25 0 25 50 75 100 -50 125 -25 Junction Temperature (oC) 0 25 50 75 100 125 Junction Temperature (oC) IN Supply Current vs. Junction Temperature POR Threshold vs. Junction Temperature 2.80 POR Threshold, VPOR (V) 150 IN Supply Current, ICC (µΑ) 0 Junction Temperature (oC) 125 100 EN = high 75 2.70 VIN Increasing 2.60 2.50 2.40 VIN Decreasing 2.30 2.20 50 -50 -25 0 25 50 75 Junction Temperature Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 100 -50 125 -25 0 25 50 75 Junction Temperature (oC) 5 100 125 (oC) www.anpec.com.tw APL3205A/B Typical Operating Characteristics (Cont.) Power Switch On Resistance vs. Junction Temperature Power Switch On Resistance, RDS,ON (mΩ) Power Switch On Resistance, RDS,ON (Ω) Power Switch On Resistance vs. Input Voltage 0.35 0.30 0.25 0.20 0.15 0.10 3.0 3.5 4.0 4.5 5.0 5.5 6.0 350 300 250 200 150 -50 6.5 -25 0 25 50 75 100 125 o Junction Temperature ( C) Input Voltage, VIN (V) Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 400 6 www.anpec.com.tw APL3205A/B Operating Waveforms Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. OVP at Power On Normal Power On VIN = 0 to 12V VIN = 0 to 5V VIN VIN VOUT 1 1 VOUT 2 2 IOUT VFAULT 3 3 COUT =1µF, CIN =1µF, ROUT = 10Ω CH1: VIN, 10V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 2ms/Div COUT =1µF, CIN =1µF, ROUT = 10Ω CH1: VIN, 5V/Div, DC CH2: VOUT, 2V/Div, DC CH3: IOUT, 0.5A/Div, DC TIME: 2ms/Div Input Over-Voltage Protection Input Over-Voltage Protection APL3205A APL3205B V IN V IN 1 1 V OUT VOUT 3 2 3 V FAULT 2 COUT = 1µF, CIN=1µF, ROUT =50Ω CH1: VIN, 5V/Div, AC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME:20µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 V FAULT COUT = 1µF, CIN=1µF, ROUT =50Ω CH1: VIN, 5V/Div, AC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME:20µs/Div 7 www.anpec.com.tw APL3205A/B Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. Battery Over-Voltage Protection Recovery from Input OVP APL3204B APL3205B VBAT VIN 1 1 V OUT VOUT 2 2 VFAULT V FAULT 3 3 VIN = 12V to 5V COUT = 1µF, CIN=1µF, ROUT=50Ω CH1: VIN, 5V/Div, AC CH2: VOUT, 5V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 2ms/Div VBAT = 3.6V to 4.4V to 3.6V, ROUT=33.3Ω COUT =1µF, CIN =1µF CH1: VBAT, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 5ms/Div Recovery from Battery OVP Battery Over-Voltage Protection VBAT VB A T 1 V OUT 1 VOUT 2 2 VFAULT VFAULT 3 3 VBAT = 4.4V to 3.6V, ROUT=33.3Ω COUT =1µF, CIN =1µF CH1: VBAT, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 50µs/Div VBAT = 3.6V to 4.4V, ROUT=33.3Ω COUT =1µF, CIN =1µF CH1: VBAT, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 50µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 8 www.anpec.com.tw APL3205A/B Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. Over-Current Protection Over-Current Protection VIN IOUT 1 1 2 VOUT VOUT 2 IOUT 3 VFAULT 3 VFAULT 4 COUT=1µF, CIN =1µ F, ROUT = 2.5Ω CH1: VIN, 5V/Div, DC CH2: VOUT, 5V/Div, DC CH3: IOUT, 0.5A/Div, DC CH4: VFAULT, 5V/Div, DC TIME: 200ms/Div COUT =1µF, CIN =1µF, IOUT = 0.5A to 1.2A CH1: IOUT, 0.5A/Div, DC CH2: VOUT, 2V/Div, DC CH3: VFAULT, 5V/Div, DC TIME: 50µs/Div PSW Output Timing PSW Output Timing VIN = 5V to 0V VBAT = 3.8V VIN = 0V to 5V VBAT = 3.8V VOUT VOUT VBAT VBAT VPSW VPSW 1,2,3 1,2,3 COUT =1µF, CIN =1µF CH1: VBAT, 1V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPSW, 2V/Div, DC TIME: 200µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 COUT =1µF, CIN =1µF CH1: VBAT, 1V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPSW, 2V/Div, DC TIME: 5ms/Div 9 www.anpec.com.tw APL3205A/B Pin Description PIN FUNCTION NO. NAME 1 IN 2 GND Ground. 3 PSW PSW is an active high output that drives the external PMOS (see Application Circuit). 4 FAULT 5 EN Enable Input. Pull this pin to high to disable the device and pull this pin to low to enable device. 6 BAT Battery OVP Sense Pin. Connect to positive terminal of battery through a resistor. 7 ILIM Over-current Protection Setting Pin. Connect a resistor to the GND to set the over-current threshold. 8 OUT Output Voltage Pin. The output voltage follows the input voltage when no fault is detected. - EP Power Supply Input. Fault Indication Pin. This pin goes low when input OVP, OCP, or battery OVP is detected. Exposed Thermal Pad. Must be electrically connected to the GND pin. Block Diagram IN OUT POR ILIM Charge Pump 0.5V Gate Driver and Control Logic 1.2V 1V BAT FAULT OTP VOUT PSW VBAT +0.1V EN Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 GND 10 www.anpec.com.tw APL3205A/B Typical Application Circuit 5V Adapter/ USB 1 IN OUT 8 1µF GTDRV APL3205A/B 50K 5 GPIO CHRIN 1uF 50K EN PSW 4 MCU MTK PMU 3 FAULT APM2805QA 50K VIO 25K 7 200K ILIM GND BAT ISENS 0.2 6 VBAT Li+ Battery 2 Figure 1. The Typical Protection Circuit for Charger Systems. 5V Adapter/ USB 1 8 IN OUT CHRIN 1µF 1uF APL3205A/B 50K 5 GPIO 50K EN MTK PMU 3 PSW 4 MCU GTDRV FAULT VIO 50K 25K ISENS APM2103QA 7 200K ILIM GND 2 BAT 0.2 6 VBAT Li+ Battery Figure 2. Use the PSW pin to drive an external P-Channel MOSFET T for Charger Systems. Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 11 www.anpec.com.tw APL3205A/B Function Description Power-Up The APL3205A/B have a built-in power-on-reset circuit to keep the output shuting off until internal circuitry is oper- the internal power FET is turned off. When the BP voltage returns below the battery OVP threshold minus the ating properly. The POR circuit has hysteresis and a deglitch feature, therefore, it will typically ignore undershoot hysteresis, the FET is turned on again. The APL3205A/B have a built-in counter. When the total count of battery transients on the input. When input voltage exceeds the POR threshold and after 8ms blanking time, the output OVP fault reaches 16, the FET is turned off permanently, requiring either a VIN POR or EN re-enable again to restart. voltage starts a soft-start to reduce the inrush current. Over-Temperature Protection Input Over-Voltage Protection (OVP) When the junction temperature exceeds 140οC, the inter- The input voltage is monitored by the internal OVP circuit. When the input voltage rises above the input OVP nal thermal sense circuit turns off the power FET and allows the device to cool down. When the device’s junc- threshold, the internal FET will be turned off within 1µs to protect connected system on OUT pin. When the input tion temperature cools by 20οC, the internal thermal sense circuit will enable the device, resulting in a pulsed output voltage returns below the input OVP threshold minus the hysteresis, the FET is turned on again after 8ms recovery during continuous thermal protection. Thermal protection is designed to protect the IC in the event of over tem- time. The input OVP circuit has a 200mV hysteresis and a recovery time of TON(OVP) to provide noise immunity perature conditions. For normal operation, the junction temperature cannot exceed TJ=+125 οC. against transient conditions. FAULT Output Over-Current Protection (OCP) The output current is monitored by the internal OCP circuit. The APL3205A/B provide an open-drain output to indicate that a fault has occurred. When any of input OVP, When the output current reaches the OCP threshold, the device limits the output current at OCP threshold level. If OCP, battery OVP, is detected, the FAULT goes low to indicate that a fault has occurred. Since the FAULT pin is the OCP condition continues for a blanking time of TB(OCP), the internal power FET is turned off. After the recovery an open-drain output, connecting a resistor to a pull high voltage is necessary. time of TON(OCP), the FET will be turned on again and the output current is monitored again. The APL3205A/B have Enable/Shutdown a built-in counter. When the total count of OCP fault reaches 16, the FET is turned off permanently, requiring Pulling the EN pin voltage above 1.4V disables the device and pulling EN pin voltage below 0.4V enables the device. The EN pin has an internal pull-down resistor either a VIN POR or EN re-enable again to restart. The OCP threshold is programmed by a resistor RILIM con- and can be left floating. When the IC is latched off due to the total count of OCP or battery OVP reaches 16, disable nected from ILIM pin to the GND. The OCP threshold is calculated by the following equation: IOCP = and re-enable the device with the EN pin can clear the counter. KILIM RILIM PSW Output where The APL3205A/B provide an active high output to drive the KILIM=25000AΩ external P-channel MOSFET. When VOUT > VBAT + 100mV, the PSW pin is pulled low, and turns on the external P- Battery Over-Voltage-Protection The APL3205A/B monitor the BAT pin voltage for battery channel MOSFET for battery charge. When VOUT < VBAT + 50mV, the PSW pin is pulled high, and turns off the exter- over-voltage protection. The battery OVP threshold is internally set to 4.35V. When the BAT pin voltage exceeds nal P-channel MOSFET, which prevents the battery voltage from supplying to OUT pin and IN pin (see Applica- the battery OVP threshold for a blanking time of TB(BOVP), tion Circuit). Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 12 www.anpec.com.tw APL3205A/B Function Description (Cont.) VOVP VPOR VIN VOUT VFAULT TB(IN) TON(OVP) Figure3. OVP Timing Chart VOUT OCP Threshold Count 13 times IOUT VFAULT TB(OCP) TON(OCP) TB(OCP) TB(OCP) Total count 16 times IC is latched off Figure 4. OCP Timing Chart Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 13 www.anpec.com.tw APL3205A/B Function Description (Cont.) VBAT VBOVP VBOVP VBOVP Count 13 times VOUT VFAULT TB(BOVP) TB(BOVP) TB(BOVP) Total count 16 times IC is latched off Figure 5. Battery OVP Timing Chart Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 14 www.anpec.com.tw APL3205A/B Application Information RBAT Selection RUP FAULT Connect the BAT pin to the positive terminal of battery VIO through a resistor RBAT for battery OVP function. The RBAT limits the current flowing from BAT to battery in case of RFAULT GPIO BAT pin is shortened to VIN pin under a failure mode. The recommended value of RBAT is 100kΩ. In the worse case EN of an IC failure, the current flowing from the BAT pin to the battery is: BAT REN MCU GPIO RBAT (30V-3V)/ 100kΩ =270µA where the 30V is the maximum IN voltage and the 3V is the minimum battery voltage. The current is so small that Li+ Battery can be absorbed by the charger system. The disadvantage with the large RBAT is that the error of the battery OVP threshold will be increased. The addi- Figure 6. RUP, RFAULT, REN and RBAT tional error is the voltage drop across the RBAT because of the BAT bias current. When RBAT is 100kΩ, the worse- Capacitor Selection case additional error is 100kΩx20nA=2mV, which is acceptable in most applications. The input capacitor is for decoupling and prevents the REN Selection step-down transient, the input voltage has a transient spike due to the parasitic inductance of the input cable. A input voltage from overshooting to dangerous levels. In the AC adapter hot plug-in applications or load current For the same reason as the BAT pin case, the EN pin should be connected to the MCU GPIO pin through a 25V, X5R, dielectric ceramic capacitor with a value between 1µF and 4.7µF placed close to the IN pin is resistor. The value of the REN is dependent on the IO voltage of the MCU. Since the IO voltage is divided by REN and EN internal pull The output capacitor is for output voltage decoupling, and low resistor for EN voltage. It has to be ensured that the EN voltage is above the EN logic high voltage when the also can be as the input capacitor of the charging circuit. At least, a 1µF, 10V, X5R capacitor is recommended. recommended. GPIO output of the MCU is high. Layout Consideration FAULT Output In some failure modes, a high voltage may be applied to Since the FAULT pin is an open-drain output, connecting a resistor RUP to a pull high voltage is necessary. It is also the device. Make sure that the clearance constraint of the PCB layout must satisfy the design rule for high voltage. The exposed pad of the TDFN2x2-8 performs the func- recommended that connect the FAULT to the MCU GPIO through a resistor RFAULT. The RFAULT prevents damage to tion of channeling heat away. It is recommended that connect the exposed pad to a large copper ground plane the MCU under a failure mode. The recommended value of the resistors should be between 10kΩ and 100kΩ. on the backside of the circuit board through several thermal vias to improve heat dissipation. The input and output capacitors should be placed close to the IC. RILIM also should be placed close to the IC. The high current traces like input trace and output trace must be wide and short. Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 15 www.anpec.com.tw APL3205A/B Package Information TDFN2x2-8 A b E D D2 A1 E2 A3 L Pin 1 Corner e S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.18 0.30 0.007 0.012 D 1.90 2.10 0.075 0.083 D2 1.00 1.60 0.039 0.063 TDFN2x2-8 MILLIMETERS A3 b INCHES 0.20 REF 0.008 REF E 1.90 2.10 0.075 0.083 E2 0.60 1.00 0.024 0.039 0.45 0.012 e L 0.50 BSC 0.30 0.020 BSC 0.018 Note : 1. Follow from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 16 www.anpec.com.tw APL3205A/B Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN2x2-8 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.50±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.4 3.35 MIN 3.35 MIN 1.30±0.20 (mm) Devices Per Unit Package Type Unit Quantity TDFN2x2-8 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 17 www.anpec.com.tw APL3205A/B Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 18 www.anpec.com.tw APL3205A/B Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD 78 19 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV, VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL3205A/B Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - May., 2009 20 www.anpec.com.tw