ASIX AX88140AQ

ASIX
AX88140A
Fast Ethernet MAC Controller
ASIX AX88140A
100BASE-TX/FX PCI Bus
Fast Ethernet MAC Controller
Data Sheet(11/03/’97)
DOCUMENT NO. : AX140D2.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
AX88140A
PRELIMINARY
CONTENTS
1.0 INTRODUCTION ................................................................................................................................................ 6
1.1 GENERAL DESCRIPTION: ...................................................................................................................................... 6
1.2 FEATURES ............................................................................................................................................................ 7
1.3 BLOCK DIAGRAM: ............................................................................................................................................... 8
1.4 AX88140AQ PIN CONNECTION DIAGRAM FOR 160-PIN ...................................................................................... 9
1.5 AX88140AP PIN CONNECTION DIAGRAM FOR 144-PIN .................................................................................... 10
2.0 SIGNAL DESCRIPTION .................................................................................................................................. 11
2.1 SIGNAL DESCRIPTIONS FOR 160-PIN AND 144-PIN.............................................................................................. 11
2.2 PCI INTERFACE GROUP ...................................................................................................................................... 12
2.3 BOOT ROM , SERIAL ROM , GENERAL-PURPOSE SIGNALS GROUP .................................................................... 14
2.4 MII/SYM/SRL INTERFACE SIGNALS GROUP ...................................................................................................... 14
2.5 EXTENDED , NC, POWER PINS GROUP ................................................................................................................ 16
3.0 CONFIGURATION OPERATION .................................................................................................................. 17
3.1 CONFIGURATION SPACE MAPPING ..................................................................................................................... 17
3.2 CONFIGURATION SPACE ..................................................................................................................................... 18
3.2.1 Configuration ID Register (CSID)............................................................................................................ 18
3.2.2 Command and Status Configuration Register (CSCS)............................................................................... 18
3.2.3 Configuration Revision Register (CSRV).................................................................................................. 18
3.2.4 Configuration Latency Timer Register (CSLT)......................................................................................... 18
3.2.5 Configuration Base I/O Address Register (CBIO).................................................................................... 19
3.2.6 Configuration Base Memory Address Register (CBMA) .......................................................................... 19
3.2.7 Expansion ROM Base Address Register (CBER)...................................................................................... 19
3.2.8 Configuration Interrupt Register (CSIT) .................................................................................................. 19
4.0 REGISTERS OPERATION .............................................................................................................................. 20
4.1 REGISTERS MAPPING ......................................................................................................................................... 20
4.2 HOST REGS ....................................................................................................................................................... 21
4.2.1 Bus Mode Register (REG0)........................................................................................................................ 21
4.2.2 Transmit Poll Demand (REG1)................................................................................................................. 21
4.2.3 Receive Poll Demand (REG2)................................................................................................................... 22
4.2.4 Receive List Base Address (REG3) ........................................................................................................... 22
4.2.5 Transmit List Base Address (REG4) ......................................................................................................... 22
4.2.6 Status Register (REG5) ............................................................................................................................. 23
4.2.7 Operation Mode Register (REG6) ............................................................................................................ 24
4.2.8 Interrupt Enable Register (REG7) ............................................................................................................ 26
4.2.9 Missed Frame and Overflow Counter (REG8) ........................................................................................ 26
4.2.10 Serial ROM and MII Management Register (REG9).............................................................................. 27
4.2.11 General-Purpose Timer (REG11)........................................................................................................... 27
4.2.12 General-Purpose Port Register (REG12) ............................................................................................... 28
4.2.13 Filtering Index (REG13) ......................................................................................................................... 28
4.2.14 Filtering data (REG14)........................................................................................................................... 28
5.0 HOST COMMUNICATION.............................................................................................................................. 30
5.1 DESCRIPTOR LISTS AND DATA BUFFERS ............................................................................................................ 30
5.2 RECEIVE DESCRIPTORS ...................................................................................................................................... 31
5.2.1 Receive Descriptor 0 (RDES0) .................................................................................................................. 31
5.2.2 Receive Descriptor 1 (RDES1) .................................................................................................................. 32
5.2.3 Receive Descriptor 2 (RDES2) .................................................................................................................. 32
5.2.4 Receive Descriptor 3 (RDES3) .................................................................................................................. 32
5.3 TRANSMIT DESCRIPTORS ................................................................................................................................... 33
5.3.1 Transmit Descriptor 0 (TDES0)................................................................................................................. 33
5.3.2 Transmit Descriptor 1 (TDES1)................................................................................................................. 34
5.3.3 Transmit Descriptor 2 (TDES2)................................................................................................................. 34
5.3.4 Transmit Descriptor 3 (TDES3)................................................................................................................. 34
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
6.0 ELECTRICAL SPECIFICATION AND TIMINGS ...................................................................................... 35
6.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 35
6.2 GENERAL OPERATION CONDITIONS ................................................................................................................... 35
6.3 DC CHARACTERISTICS ...................................................................................................................................... 35
6.4 A.C. TIMING CHARACTERISTICS ........................................................................................................................ 36
6.4.1 PCI CLOCK .............................................................................................................................................. 36
6.4.2 PCI Timings ............................................................................................................................................... 36
6.4.3 Reset Timing .............................................................................................................................................. 36
6.4.4 MII/SYM Timing ........................................................................................................................................ 37
6.4.5 10Mbps serial timing ................................................................................................................................. 38
6.4.6 Boot ROM Read Cycles ............................................................................................................................. 39
7.0 PACKAGE INFORMATION............................................................................................................................ 40
APPENDIX A H/W NOTE .................................................................................................................................... 41
A.1 BOOT ROM READ CYCLE .................................................................................................................................. 41
A.2 POWER SUPPLY ................................................................................................................................................. 42
A.3 BOUNDARY SCAN TEST PINS ............................................................................................................................ 42
APPENDIX B FUNCTION APPLICATION ...................................................................................................... 43
B.1 APPLICATION FOR PCI INTERFACE .................................................................................................................... 43
B.2 APPLICATION FOR BOOT ROM INTERFACE ....................................................................................................... 44
B.3 APPLICATION FOR SERIAL ROM INTERFACE..................................................................................................... 44
B.4 APPLICATION FOR PHY INTERFACE .................................................................................................................. 45
B.4.1 AX88140A, QSI6611, & MTD213 Application ......................................................................................... 45
B.4.2 Application for MII Mode : LEVEL ONE LXT970.................................................................................... 45
B.4.3 Application for MII Mode : MYSON MTD972 + MTD971....................................................................... 46
B.4.4 Application for MII Mode : DAVICOM DM9101 ..................................................................................... 46
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
FIGURES
FIG - 1 AX88140A BLOCK DIAGRAM ........................................................................................................................... 8
FIG - 2 AX88140AQ PIN CONNECTION DIAGRAM FOR 160-PIN ..................................................................................... 9
FIG - 3 AX88140AP PIN CONNECTION DIAGRAM FOR 144-PIN .................................................................................... 10
FIG - 4 DESCRIPTOR STRUCTURE EXAMPLE ................................................................................................................. 30
FIG - 5 RECEIVE DESCRIPTOR FORMAT........................................................................................................................ 31
FIG - 6 TRANSMIT DESCRIPTOR FORMAT ..................................................................................................................... 33
FIG - 7 APPLICATION FOR PCS / SERIAL MODE ........................................................................................................... 45
FIG - 8 APPLICATION FOR MII MODE WITH LXT970................................................................................................... 45
FIG - 9 APPLICATION FOR MII MODE WITH MDT972 + MTD971............................................................................... 46
FIG - 10 APPLICATION FOR MII MODE WITH DM9101 ................................................................................................ 46
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
TABLES
TAB - 1 PCI INTERFACE GROUP ................................................................................................................................... 13
TAB - 2 BOOT ROM , SERIAL ROM , GENERAL-PURPOSE SIGNALS GROUP ................................................................. 14
TAB - 3 MII/SYM/SRL INTERFACE SIGNALS GROUP ................................................................................................... 15
TAB - 4 EXTENDED , NC, POWER PINS GROUP ............................................................................................................. 16
TAB - 5 CONFIGURATION SPACE MAPPING .................................................................................................................. 17
TAB - 6 CSID CONFIGURATION ID REGISTER DESCRIPTION ....................................................................................... 18
TAB - 7 CSCS COMMAND AND STATUS CONFIGURATION REGISTER ........................................................................... 18
TAB - 8 CSRV CONFIGURATION REVISION REGISTER DESCRIPTION ........................................................................... 18
TAB - 9 CSLT CONFIGURATION ID REGISTER DESCRIPTION ...................................................................................... 18
TAB - 10 CBIO CONFIGURATION BASE I/O ADDRESS REGISTER DESCRIPTION .......................................................... 19
TAB - 11 CBMA CONFIGURATION BASE MEMORY ADDRESS REGISTER DESCRIPTION ............................................... 19
TAB - 12 CBER EXPANSION ROM BASE ADDRESS REGISTER DESCRIPTION .............................................................. 19
TAB - 13 CSIT CONFIGURATION INTERRUPT REGISTER DESCRIPTION ........................................................................ 19
TAB - 14 COMMAND AND STATUS REGISTER MAPPING ............................................................................................... 20
TAB - 15 REG0 BUS MODE REGISTER DESCRIPTION................................................................................................... 21
TAB - 16 REG1 TRANSMIT POLL DEMAND REGISTER DESCRIPTION ........................................................................... 21
TAB - 17 REG2 RECEIVE POLL DEMAND REGISTER DESCRIPTION .............................................................................. 22
TAB - 18 REG3 RECEIVE LIST BASE ADDRESS REGISTER DESCRIPTION ..................................................................... 22
TAB - 19 REG4 TRANSMIT LIST BASE ADDRESS REGISTER DESCRIPTION .................................................................. 22
TAB - 20 REG5 STATUS REGISTER DESCRIPTION........................................................................................................ 24
TAB - 21 REG6 OPERATION MODE REGISTER DESCRIPTION ....................................................................................... 25
TAB - 22 PORT AND DATA RATE SELECTION ............................................................................................................... 25
TAB - 23 REG7 INTERRUPT ENABLE REGISTER DESCRIPTION..................................................................................... 26
TAB - 24 REG8 MISSED FRAME AND OVERFLOW COUNTER DESCRIPTION ................................................................. 26
TAB - 25 REG9 SERIAL ROM, AND MII MANAGEMENT REGISTER DESCRIPTION ..................................................... 27
TAB - 26 REG11 GENERAL-PURPOSE TIMER REGISTER DESCRIPTION ........................................................................ 28
TAB - 27 REG12 GENERAL-PURPOSE PORT REGISTER DESCRIPTION.......................................................................... 28
TAB - 28 REG13 FILTERING INDEX REGISTER DESCRIPTION ...................................................................................... 28
TAB - 29 REG14 FILTERING DATA REGISTER DESCRIPTION ....................................................................................... 28
TAB - 30 DESCRIPTION OF FILTERING BUFFER ............................................................................................................ 28
TAB - 31 LAYOUT OF FILTERING BUFFER .................................................................................................................... 29
TAB - 32 RECEIVE DESCRIPTOR 0 ................................................................................................................................ 32
TAB - 33 RECEIVE DESCRIPTOR 1 ................................................................................................................................ 32
TAB - 34 RECEIVE DESCRIPTOR 2 ................................................................................................................................ 32
TAB - 35 RECEIVE DESCRIPTOR 3 ................................................................................................................................ 32
TAB - 36 TRANSMIT DESCRIPTOR 0 ............................................................................................................................. 34
TAB - 37 TRANSMIT DESCRIPTOR 1 ............................................................................................................................. 34
TAB - 38 TRANSMIT DESCRIPTOR 2 ............................................................................................................................. 34
TAB - 39 TRANSMIT DESCRIPTOR 3 ............................................................................................................................. 34
5
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
1.0 Introduction
1.1 General Description:
l
The AX88140A Fast Ethernet Controller is a high performance and highly integrated PCI Bus Ethernet
Controller chip.
l
The AX88140A is cost effective, high performance solution for PCI add-in adapters, PC
motherboards, or bridge/hub applications.
l
It implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 LAN standard.
l
The AX88140A contains a high speed 32 bit PCI Bus master interface to host CPU. Two large
independent transmit and receive FIFO allow the AX88140A to buffer the Ethernet packet efficiently.
l
The 10/100Mbps ports can be programmed to support 10Mbps, 100Mbps media-independent interface
(MII), or 100BASE-TX physical coding sub-layer (PCS)mode, For 10Mbps operation AX88140A
provides a standard serial Interface to the external 10Mbps ENDEC chip.
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
1.2 Features
l
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Single chip PCI bus Fast Ethernet Controller.
Direct interface to PCI bus.
Support both 10Mbps and 100Mbps data rate.
Full or Half duplex operation supported for both10Mbps and 100Mbps operation.
Provides a MII port for both 10/100Mbps operation.
On chip PCS support for 100BASE-TX symbol mode operation.
On chip external 10Mbps ENDEC Interface.
Support 21MHz to 33MHz no wait state PCI Bus Interface.
Two large Independent FIFO for transmit and receive. no additional On board buffer memory required.
Interface to serial ROM for Ethernet ID address and jumper-less board design.
256KB boot ROM support.
On chip general purpose, programmable register and I/O pins.
Unlimited PCI burst.
external and internal loop-back capability.
Support early interrupts on transmit.
Powerful on chip buffer management DMA. And PCI Bus master operation reduce CPU utilization.
Big and little endian byte ordering supported.
IEEE 802.3u 100BASE-T, TX, and T4 Compatible.
160 pin or 144 pin PQFP package.
5V CMOS process.
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
1.3 Block Diagram:
SERIAL
ROOM
BOOT ROM
Interface
Serial
ROM I/F
BOOT
ROM I/F
Receive FIFO
PCI
BUS
PCI
BUS
MII
Interface
MII
PCS
Interface
SYM
MAC
Buffer
Management
DMA Engine
Controller
Interface
10 BT
Interface
Transmit FIFO
SRL
General Purpose REG
General purpose I/O pins
Fig - 1 AX88140A Block Diagram
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
1.4 AX88140AQ Pin Connection Diagram for 160-pin
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
nc
nc
nc
nc
nc
nc
srl_txen
srl_tclk
srl_txd
srl_rclk
srl_rxen
srl_rxd
srl_clsn
mii/srl
symtxd<4>
mtxd<3>/symtxd<3>
mtxd<2>/symtxd<2>
vdd
vss
mtxd<1>/symtxd<1>
mtxd<0>/symtxd<0>
mtxen/symtxen
nc
mtclk/symtclk
rcv_match
vdd
vss
symrxd<4>
mrxd<3>/symrxd<3>
mrxd<2>/symrxd<2>
mrxd<1>/symrxd<1>
mrxd<0>/symrxd<0>
mrclk/symrclk
mcrs
mcol
mrxdv
mrxerr
sd
nc
nc
The AX88140A is housed in the 160-pin plastic quad flat pack. Fig - 2 shows the AX88140A
pin connection diagram.
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
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96
95
94
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90
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88
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83
82
81
ASIX
88140AQ
nc
nc
vss
vdd
mdc
mdio
nc
br_a<1>
br_a<0>
brce#
br_ad<7>
br_ad<6>
vdd
vss
br_ad<5>
br_ad<4>
br_ad<3>
br_ad<2>
br_ad<1>
br_ad<0>
vss
genp<7>
genp<6>
genp<5>
genp<4>
vdd
vss
genp<3>
genp<2>
genp<1>
genp<0>
sr_cs
sr_ck
sr_di
sr_do
vdd
vss
vdd*
nc
nc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
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71
72
73
74
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76
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78
79
80
1
2
3
4
5
6
7
8
9
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11
12
13
14
15
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19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
nc
nc
vss
cbe#<2>
frame#
irdy#
trdy#
devsel#
stop#
vdd
perr#
serr#
par
cbe#<1>
vss
ad<15>
ad<14>
ad<13>
vss
ad<12>
ad<11>
vdd
ad<10>
ad<09>
vss
ad<08>
cbe#<0>
ad<07>
ad<06>
vss
ad<05>
ad<04>
vdd
ad<03>
ad<02>
vss
ad<01>
ad<00>
nc
nc
nc
nc
int#
rst#
vdd
vss
pci_clk
vdd
gnt#
req#
vss
ad<31>
ad<30>
vss
ad<29>
ad<28>
vss
ad<27>
ad<26>
vdd
ad<25>
ad<24>
c_be#<3>
idsel
vss
ad<23>
ad<22>
ad<21>
ad<20>
vdd
ad<19>
ad<18>
vdd
vss
vss
ad<17>
ad<16>
vss
nc
nc
Fig - 2 AX88140AQ Pin connection diagram for 160-pin
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
1.5 AX88140AP Pin Connection Diagram for 144-pin
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
nc
nc
nc
nc
srl_txen
srl_tclk
srl_txd
srl_rclk
srl_rxen
srl_rxd
srl_clsn
mii/srl
symtxd<4>
mtxd<3>/symtxd<3>
mtxd<2>/symtxd<2>
vdd
vss
mtxd<1>/symtxd<1>
mtxd<0>/symtxd<0>
mtxen/symtxen
nc
mtclk/symtclk
rcv_match
vdd
vss
symrxd<4>
mrxd<3>/symrxd<3>
mrxd<2>/symrxd<2>
mrxd<1>/symrxd<1>
mrxd<0>/symrxd<0>
mrclk/symrclk
mii_crs
mcol
mrxdv
mrxerr
sd
The AX88140A is housed in the 144-pin plastic quad flat pack. Fig - 3 shows the AX88140A
pin connection diagram.
108
107
106
105
104
103
102
101
100
99
98
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95
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ASIX
88140AP
vss
vdd
mdc
mdio
nc
br_a<1>
br_a<0>
brce#
br_ad<7>
br_ad<6>
vdd
vss
br_ad<5>
br_ad<4>
br_ad<3>
br_ad<2>
br_ad<1>
br_ad<0>
vss
genp<7>
genp<6>
genp<5>
genp<4>
genp<5>
vdd
vss
genp<3>
genp<2>
genp<1>
genp<0>
sr_cs
sr_ck
sr_di
sr_do
vdd
vss
vdd*
37
38
39
40
41
42
43
44
45
46
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50
51
52
53
54
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56
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66
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68
69
70
71
72
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2
3
4
5
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20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
vss
cbe#<2>
frame#
irdy#
trdy#
devsel#
stop#
vdd
perr#
serr#
par
cbe#<1>
vss
ad<15>
ad<14>
ad<13>
vss
ad<12>
ad<11>
vdd
ad<10>
ad<09>
vss
ad<08>
cbe#<0>
ad<07>
ad<06>
vss
ad<05>
ad<04>
vdd
ad<03>
ad<02>
vss
ad<01>
ad<00>
int#
rst#
vdd
vss
pci_clk
vdd
gnt#
req#
vss
ad<31>
ad<30>
vss
ad<29>
ad<28>
vss
ad<27>
ad<26>
vdd
ad<25>
ad<24>
cbe#<3>
idsel
vss
ad<23>
ad<22>
ad<21>
ad<20>
vdd
ad<19>
ad<18>
vdd
vss
vss
ad<17>
ad<16>
vss
Fig - 3 AX88140AP Pin connection diagram for 144-pin
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ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
2.0 Signal Description
2.1 Signal Descriptions for 160-pin and 144-pin
The following terms describe the AX88140A pin-out:
Address phase
Address and appropriate bus commands are driven during this cycle.
l Data phase
Data and the appropriate byte enable codes are driven during this cycle.
l #
All pin names with the # suffix are asserted low.
l
The following abbreviations are used in Tab - 1 PCI interface group Tab - 2 Boot ROM , Serial ROM , Generalpurpose signals group ,Tab - 3 MII/SYM/SRL interface signals group ,Tab - 4 Extended , NC, Power pins group..
I
O
I/O
O/D
Input
Output
Input /Output
Open Drain
11
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
2.2 PCI interface group
SIGNAL TYPE
PIN
PIN
NUMBER
NUMBER
FOR 160 PIN FOR 144 PIN
12,
13,
15,
16,
18,
19,
21,
22,
26,
27,
28,
29,
31,
32,
36,
37,
56,
57,
58,
60,
61,
63,
64,
66,
68,
69,
71,
72,
74,
75,
77,
78
23,
44,
54,
67
10,
11,
13,
14,
16,
17,
19,
20,
24,
25,
26,
27,
29,
30,
34,
35,
50,
51,
52,
54,
55,
57,
58,
60,
62,
63,
65,
66,
68,
69,
71,
72
21,
38,
48,
61
I/O
48
42
I/O
45
39
GNT#
I
9
7
IDSEL
I
24
22
INT#
O/D
3
1
IRDY#
I/O
46
40
AD<31>
AD<30>
AD<29>
AD<28>
AD<27>
AD<26>
AD<25>
AD<24>
AD<23>
AD<22>
AD<21>
AD<20>
AD<19>
AD<18>
AD<17>
AD<16>
AD<15>
AD<14>
AD<13>
AD<12>
AD<11>
AD<10>
AD<9>
AD<8>
AD<7>
AD<6>
AD<5>
AD<4>
AD<3>
AD<2>
AD<1>
AD<0>
CBE#<3>
CBE#<2>
CBE#<1>
CBE#<0>
I/O
DEVSEL#
FRAME#
I/O
DESCRIPTION
Address and data bits are multiplexed on the same pins. During the
address phase, the AD<31:0> contain a physical address (32 bits).
During, data phases, AD<31:0> contain 32 bits of data.
The AX88140A supports both read and write bursts (in master
operation only). Little and big endian byte ordering can be used.
BUS COMMAND and BYTE ENABLE Are multiplexed on the
same PCI pins. During the address phase of the transaction,
CBE#<3:0> Provide the BUS COMMAND. During the data phase,
CBE#<3:0> Provide the BYTE ENABLE. The BYTE ENABLE
determines which byte lines carry valid data., CBE#<0> Applies to
byte 0, and CBE#<3> Applies to byte 3.
Device select Is asserted by the target of the current bus access.
When the AX88140A is the master of the current bus access, the
target assert DEVSEL# confirming the access. It is driven by
AX88140A When AX88140A is selected as a slave.
The FRAME# Signal is driven by the AX88140A To indicate the
beginning and duration of an access. FRAME# Asserts to indicate
the beginning of a bus transaction. While FRAME# is asserted,
data transfers continue. When FRAME# deasserts the next data
phase is the final data phase transaction.
BUS GRANT Indicates to the AX88140A That access to the bus is
granted.
Initialization devise select asserts To indicate that the host is
issuing a configuration cycle to the AX88140A.
Interrupt request asserts When one of the appropriate bits of reg5
sets and causes an interrupt, provided that the corresponding mask
bit in reg7 is not asserted. interrupt request deasserts by writing a 1
into the appropriate crs5 bit.
This pin must be pulled up by an external resistor.
Initiator ready Indicates the bus master ability to complete the
current data phase of the transaction.
A data phase is completed on any rising edge of the clock When
both IRDY# and target ready TRDY# are asserted. Wait cycles are
inserted until both IRDY# and TRDY# are asserted together.
When the AX88140A is the bus master, IRDY# is asserted during
write operations to indicate that valid data is present on the
AD<31:0>. During read operations, the AX88140A asserts
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ASIX ELECTRONICS CORPORATION
AX88140A
PAR
PRELIMINARY
I/O
53
47
I
7
5
PERR#
I/O
51
45
REQ#
O
10
8
RST#
I
4
2
SERR#
I/O
52
46
STOP#
I/O
49
43
TRDY#
I/O
47
41
PCI_CLK
IRDY# to indicate that it is ready to accept data.
Parity is an even parity bit for the AD<31:0> AD and CBE#<3:0>.
During address and data phases, parity is calculated on all the
AD<31:0> AND CBE#<3:0>lines whether or not any of these
lines carry meaningful information.
The clock provides the timing for the AX88140A related PCI bus
transactions. All the bus signals are sampled on the rising edge of
PCI_CLK. The clock frequency range is between 21MHZ and
33MHZ.
Parity error asserts when a data parity error is detected. When the
AX88140A is the bus master it monitor PERR# to see if the target
report a data parity error., when the AX88140A is the bus target
and a parity error is detected, the AX88140A asserts PERR#. This
pin must be pulled up by an external resistor.
Bus request is asserted by the AX88140A to indicate to the bus
arbiter that it wants to use the bus.
Resets the AX88140A to its initial state. This signal must be
asserted for at least 10 active PCI clock cycles. When is the reset
state, all PCI output pins are put into tri-state and all PCI o/d
signals are floated.
System Error is used by AX88140A to report address parity Error.
This pin must be pulled up by an external resistor.
Stop indicator indicates that the current target is requesting the bus
master to stop the current transaction. The AX88140A responds to
the assertion of STOP# when it is the bus master, and stop the
current transaction.
Target ready indicates the target ability to complete the current data
phase of the transaction.
A data phase is completed on any clock when both TRDY# and
IRDY# are asserted. Wait cycles are inserted until both IRDY#
and TRDY# are asserted together. When the AX88140A is the bus
master, target ready is asserted by the bus slave on the read
operation, indicating that valid data is present on the ad lines.
During a write cycle, it indicates that the target is prepared to
accept data.
Tab - 1 PCI interface group
13
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
2.3 Boot ROM , Serial ROM , General-purpose signals group
SIGNAL
BR_A<0>
BR_A<1>
BR_AD<7>
BR_AD<6>
BR_AD<5>
BR_AD<4>
BR_AD<3>
BR_AD<2>
BR_AD<1>
BR_AD<0>
BR_CE#
SR_CK
SR_CS
SR_DI
SR_DO
GENP<7>
GENP<6>
GENP<5>
GENP<4>
GENP<3>
GENP<2>
GENP<1>
GENP<0>
TYPE
PIN
PIN
NUMBER
NUMBER
FOR 160 PIN FOR 144 PIN
0
0
112
113
102
103
I/O
110,
109,
106,
105,
104,
103,
102,
101
111
88
89
87
86
99,
98,
97,
96,
93,
92,
91,
90
100,
99,
96,
95,
94,
93,
92,
91
101
78
79
77
76
89,
88,
87,
86,
83,
82,
81,
80
O
O
O
O
I
I/O
DESCRIPTION
Boot ROM address line bit 0.
Boot ROM address line bit 1. This pin also latches the boot ROM
address and control lines by the two external latches.
Boot ROM address and data multiplexed lines bits 7 through 0. In
the first of two consecutive address cycles, these lines contain the
boot ROM address bits 9 through 2; followed by boot ROM
address bits 17 through 10 in the second cycle. During the data
cycle, bits 7 through 0 contain data.
Boot ROM chip enable.
Serial ROM clock signal.
Serial ROM chip-select signal.
Serial ROM data-in signal.
Serial ROM data-out signal.
General-purpose pins can be used by software as either status pins
or control pins. These pins can be configured by software to
perform either input or output functions.
Tab - 2 Boot ROM , Serial ROM , General-purpose signals group
2.4 MII/SYM/SRL interface signals group
SIGNAL
TYPE PIN
PIN
NUMBER
NUMBER
FOR 160 PIN FOR 144 PIN
MCOL
I
126
112
MCRS
I
127
113
MRXDV
I
125
111
MRXERR
I
124
110
MDC
O
116
106
MDIO
I/O
115
105
O
147
133
MII/SRL
DESCRIPTION
Collision detected is asserted when detected by an
external physical layer protocol(PHY) device.
Carrier sense is asserted by the PHY when the media
is active.
Data valid is asserted by an external PHY when
receive data is present on the MRXD/SYRXD lines
and is deasserted at the end of the packet. This signal
should be synchronized with the
MRCLK/SYMRCLK signal.
Receive error asserts when a data decoding error is
detected by an external PHY device. This signal is
synchronized to MRCLK/SYMRCLK and can be
asserted for a minimum of one receive clock. When
asserted during a packet reception, it sets the cyclic
redundancy check(CRC) error bit in the receive
descriptor (RDESO).
MII management data clock is sourced by the
AX88140A to the PHY devices as a timing reference
for the transfer of information on the MII_MDIO
signal.
MII management data input/output transfers control
information and status between the PHY and the
AX88140A.
Indicates the selected port: SRL or MII/SYM. When
asserted, the MII/SYM port is active. When
deasserted, the SRL port is active.
14
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
MRCLK/SYMRCLK
I
128
114
MRXD<3>/SYMRXD<3>
MRXD<2>/SYMRXD<2>
MRXD<1>/SYMRXD<1>
MRXD<0>/SYMRXD<0>
MTCLK/SYMTCLK
I
132,
131,
130,
129
137
118,
117,
116,
115
123
I
MTXD<3>/SYMTXD<3>
MTXD<2>/SYMTXD<2>
MTXD<1>/SYMTXD<1>
MTXD<0>/SYMTXD<0>
O
145,
144,
141,
140
131,
130,
127,
126
MTXEN/SYMTXEN
O
139
125
RCV_MATCH
O
136
122
SD
I
123
109
SRL_CLSN
I
148
134
SRL_RCLK
I
151
137
SRL_RXD
I
149
135
SRL_RXEN
I
150
136
SRL_TCLK
I
153
139
SRL_TXD
O
152
138
SRL_TXEN
O
154
140
SYMRXD <4>
I
133
119
SYMTXD<4>
O
146
132
Supports either the 25-MHZ or 2.5-MHZ receive
clock. This clock is recovered by the PHY.
Four parallel receive data lines When MII mode is
selected. This data is driven by an external PHY that
attached the media and should be synchronized with
the MRCLK/SYMRCLK signal.
Supports the 25-MHZ or 2.5-MHZ transmit clock
supplied by the external physical layer medium
dependent (PMD) device. This clock should always
be active.
Four parallel transmit data lines. This data is
synchronized to the assertion of the
MTCLK/SYMTCLK signal and is latched by the
external PHY on the rising edge of the
MTCLK/SYMTCLK signal.
Transmit enable signals that the transmit is active to
an external PHY device. In PCS mode (REG6<23>),
This signal reflects the transmit activity of the MAC
sub-layer.
Receive match indication is asserted when a received
packet has passed address recognition.
Receive match indication is asserted when a received
packet has passed address recognition.
Signal detect indication supplied by an external
physical layer medium dependent (PMD) device.
Collision detect signals a collision occurrence on the
Ethernet cable to the AX88140A. It may be asserted
and deasserted asynchronously by the external
ENDEC to the receive clock.
Receive clock carries the recovered receive clock
supplied by an external ENDEC. during idle periods,
SRL_RCLK may be inactive.
Receive data carries the input receive data from the
external ENDEC. The incoming data should be
synchronous with the SRL_RCLK signal.
Receive enable signals activity on the Ethernet cable
to the AX88140A. It is asserted when receive data is
present on the Ethernet cable and is deasserted at the
end of a frame. It may be asserted and deasserted
asynchronously to the receive clock (SRL_RCLK) by
the external ENDEC.
Transmit clock carries the transmit clock supplied by
an external ENDEC. This clock must always be
active (even during reset).
Transmit data carries the serial output data from the
AX88140A. This data is synchronized to the
SRL_TCLK signal.
Transmit enable signals an external ENDEC That the
AX88140A transmit is in progress.
Receive data, together with the four receive lines
MII/SYM_RXD<3:0>, Provide five parallel lines of
data in symbol from for use in PCS mode
(100BASE-T, REG6<23). This data is synchronized
on the rising edge of the MTCLK/SYMTCLK signal.
Transmit data, together with the our transmit lines
MII/SYM_TXD<3:0>,provide five parallel lines of
data in symbol form for use in PCS mode
(100BASE-T, REG6<23>). This data is synchronized
on the rising edge of the MII/SYM_TCLK signal.
Tab - 3 MII/SYM/SRL interface signals group
15
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
2.5 Extended , NC, Power pins group
SIGNAL
TYPE
EC<15:0>
O
NC
O
VDD
P
VDD*
VSS
P
P
PIN
PIN
NUMBER
NUMBER
FOR 160 PIN FOR 144 PIN
160,159,122,
121,120,119,
82,81,80,79,42,41
,40,39,2,1
114,138,155,156,
157,158
5,8,20,30,33,
50,62,73,85,
95,108,117,
135,143
83
6,11,14,17,25,
34,35,38,43,
55,59,65,70,
76,84,94,100,
107,118,134,
142
DESCRIPTION
NONE
Expended pins. do not connect.
104,124,141,142,
143,144
3,6,18,28,31,
44,56,67,75,
85,98,107,
121,129
73
4,9,12,15,23,
32,33,36,37,
49,53,59,64,
70,74,84,90,97,10
8,120,128
No connection.
5-V supply input voltage.
5.0-V reference for 5.0-V signaling environments
Ground pins.
Tab - 4 Extended , NC, Power pins group
16
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
3.0 Configuration Operation
1.
Software reset (REG0<0>) has no effect on the configuration registers.
2.
Hardware reset puts the configuration registers in default values.
3.
The configuration registers could be accessed in byte, word , and long-word.
3.1 Configuration Space Mapping
CONFIGURATION REGISTER
DEVICE/VENDOR ID
COMMAND AND STATUS
REVISION
LATENCY TIMER
BASE I/O ADDRESS
BASE MEMORY ADDRESS
RESERVED
SUBSYSTEM ID
EXPANSION ROM BASE ADDRESS
RESERVED
INTERRUPT
Special Use
IDENTIFIER
I/O ADDRESS OFFSET
CSID
CSCS
CSRV
CSLT
CBIO
CBMA
CBER
CSIT
SUD
00H
04H
08H
0CH
10H
14H
18H-28H
2CH
30H
34H - 38H
3CH
40H
Tab - 5 Configuration Space Mapping
17
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
3.2 Configuration Space
3.2.1 Configuration ID Register (CSID)
FIELD
R/W
31:16
R
15:0
R
DESCRIPTION
Device ID :
Provides the unique AX88140A ID number (1400H)
Vender ID :
Provides the manufacturer of the AX88140A (125BH)
Tab - 6 CSID Configuration ID Register Description
3.2.2 Command and Status Configuration Register (CSCS)
FIELD
R/W
TYPE
31
30
29
28
26:25
24
23
22:9
8
6
2
1
0
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
RESERVED
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
DESCRIPTION
Detected Parity Error : active high
Signal System Error : active high
Received Master Abort : active high
Received Target Abort : active high
Device Select Timing : fixed at 01 which indicates a medium assertion of DEVSEL#
Data Parity Report : active high
Fast Back-to-Back : always set
System Error Enable : active high
Parity Error Response : active high
Master Operation : active high
Memory Space Access : active high
I/O Space Access : Active high
Tab - 7 CSCS Command and Status Configuration Register
3.2.3 Configuration Revision Register (CSRV)
FIELD
R/W
31:24
23:16
7:4
3:0
R
R
R
R
DESCRIPTION
Base Class : Always equal to 2H that indicates the network controller
Subclass : Always equal to 0H that indicates the fast Ethernet controller
Revision Number : Indicates the AX88140A revision number and is equal to 0H
Step Number : Indicates the AX88140A step number and is referred to current silicon step.
Tab - 8 CSRV Configuration Revision Register Description
3.2.4 Configuration Latency Timer Register (CSLT)
FIELD
R/W
31:16
15:8
7:0
R/W
R/W
R/W
DESCRIPTION
Reserved
Configuration Latency Timer. The value after hardware reset equal to 0h.
Reserved
Tab - 9 CSLT Configuration ID Register Description
18
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
3.2.5 Configuration Base I/O Address Register (CBIO)
FIELD
R/W
31:7
6:1
0
R/W
R
R
DESCRIPTION
Configuration Base I/O Address : Defines the address assignment mapping of AX88140A‘s regs.
This field value is 0 when read
I/O Space Indicator : Determines that the register maps into the I/O space. The value in this field is 1.
Tab - 10 CBIO Configuration Base I/O Address Register Description
3.2.6 Configuration Base Memory Address Register (CBMA)
FIELD
31:7
6:1
0
R/W
R/W
R
R
DESCRIPTION
Configuration Base Memory Address : Defines the address assignment mapping of AX88140A‘s regs.
This field value is 0 when read
Memory Space Indicator : Determines that the register maps into the memory space. The value in this
field is 0.
Tab - 11 CBMA Configuration Base Memory Address Register Description
3.2.7 Expansion ROM Base Address Register (CBER)
FIELD
R/W
31:10
9:1
0
R/W
R
R/W
DESCRIPTION
Expansion ROM Base Address
This field value is 0 when read
Expansion ROM Enable Bit : Active high
Tab - 12 CBER Expansion ROM Base Address Register Description
3.2.8 Configuration Interrupt Register (CSIT)
FIELD
31:24
23:16
15:8
7:0
R/W
R
R
R
R/W
DESCRIPTION
MAX_LAT : time unit is equal to 0.25 microsecond.(28H)
MIN_GNT : Time unit is equal to 0.25 microsecond.(14H)
Interrupt Pin : The AX88140A uses INTA# and the read value is (01H).
Interrupt Line : The BIOS writes the routing information into this field.
Tab - 13 CSIT Configuration Interrupt Register Description
19
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
4.0 Registers Operation
1.
The REGs are quad-word aligned, 32-bits long, and must be accessed using long-word
instruction with quad-word aligned addresses only.
2.
Reserved bits should be written with 0.; Reserved bits are UNPREDICTABLE on read
access.
3.
Retries on second data transactions occur in response to burst accesses.
4.1 Registers Mapping
REGISTER
REG0
REG1
REG2
REG3
REG4
REG5
REG6
REG7
REG8
REG9
REG10
REG11
REG12
REG13
REG14
MEANING
OFFSET FROM REG BASE ADDRESS
(CBIO,CBMA)
BUS MODE
TRANSMIT POLL DEMAND
RECEIVE POLL DEMAND
RECEIVE LIST BASE ADDRESS
TRANSMIT LIST BASE ADDRESS
STATUS
OPERATION MODE
INTERRUPT ENABLE
MISSED FRAME AND OVERFLOW COUNTER
SERIAL ROM, AND MII MANAGEMENT
GENERAL-PURPOSE TIMER
GENERAL-PURPOSE PORT
FILTERING BUFFER INDEX
FILTERING BUFFER DATA
00H
08H
10H
18H
20H
28H
30H
38H
40H
48H
50H
58H
60H
68H
70H
Tab - 14 Command and Status Register Mapping
20
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
4.2 Host REGs
4.2.1 Bus Mode Register (REG0)
FIELD
R/W/C
DESCRIPTION
31:22
21
R/W
20
R/W
19:14
13:8
R/W
7
R/W
6:2
1
R/W
0
R/W
RESERVED
RML - Read Multiple
When set, the AX88140A supports the memory-read-multiple command on the PCI bus. This bus
command is used in memory read bursts with more than one longword. When reset, the AX88140A
uses memory-read command in all its memory read accesses on the PCI bus.
DBO - Descriptor Byte Ordering Mode
When set, the AX88140A operates in big edian ordering mode for descriptors only.
When reset, the AX88140A operates in little endian mode.
Reserved.--Written as “0” for future compatibility concern.
PBL - Programmable Burst Length
Indicates the maximum number of longwords to be transfered in one DMA transaction. If reset, the
ax88140a burst is limited only by the amount of data stored in the receive FIFO (at least 16 longword),
or by the amount of free space in the transmit FIFO (at least 16 longword) before issuing a bus request.
The PBL can be programmed with permissible values 0,1,2,4,8,16, or 32. After reset, the PBL default
value is 0.
BLE - Big/Little Endian
When set, the AX88140A operates in big endian byte ordering mode. When reset, the AX88140A
operates in little endian byte ordering mode. Big endian is applicable only for data buffer
RESERVED
BAR - Bus Arbitration
Selects the internal bus arbitration between the receive and transmit processes.
When set, a round robin arbitration scheme is applied resulting in equal sharing between processes.
When reset, the receive process has priority over the transmit process, unless the ax88140a is currently
transmitting.
SWR - Software Reset
When set, the AX88140A resets all internal hardware with the exception of the configuration area and
also, it does not change the port select setting (REG6<18>).
Software reset does not affect the configuration area.
Tab - 15 REG0 Bus Mode Register Description
4.2.2 Transmit Poll Demand (REG1)
FIELD
R/W
DESCRIPTION
31:0
W
TPD - Transmit Poll Demand
When written with any value, the AX88140A checks for frames to be transmitted. If no descriptor is
available, the transmit process returns to the suspended states and REG5<2> is asserted. If the descriptor
is available the transmit process resumes.
Tab - 16 REG1 Transmit Poll Demand Register Description
21
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
4.2.3 Receive Poll Demand (REG2)
FIELD
R/W/C
31:0
W
DESCRIPTION
RPD - Receive Poll Demand
When written with any value, the AX88140A checks for receive descriptors to be required. If no
descriptor is available, the receive process returns to the suspended states and REG5<7> is not
asserted. If the descriptor is available the receive process resumes.
Tab - 17 REG2 Receive Poll Demand Register Description
4.2.4 Receive List Base Address (REG3)
1.
The register is used to point the AX88140A to the start of receive descriptors list.
2.
The descriptor list resides in physical memory space and must be longword aligned. The
AX88140A behaves UNPREDICTABLY when the list are not longword aligned.
3.
Writing to REG3 is permitted only when receive process is in the stopped state. That is, the
REG3 must be written before the receive START command is given .
REG3 Receive List Base Address Register Description
FIELD
R/W/C
31:2
1:0
R/W
R/W
DESCRIPTION
Start of receive list
Must be 00 for longword alignment
Tab - 18 REG3 Receive List Base Address Register Description
4.2.5 Transmit List Base Address (REG4)
1.
The register is used to point the AX88140A to the start of transmit descriptors list.
2.
The descriptor list resides in physical memory space and must be long-word aligned. The
AX88140A behaves UNPREDICTABLY when the list are not long-word aligned.
3.
Writing to REG4 is permitted only when transmit process is in the stopped state. That is, the
REG4 must be written before the transmit START command is given .
FIELD
R/W/C
31:2
1:0
R/W
R/W
DESCRIPTION
Start of transmit list
Must be 00 for long-word alignment
Tab - 19 REG4 Transmit List Base Address Register Description
22
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
4.2.6 Status Register (REG5)
1.
2.
3.
4.
The status register contains all the status bits that the AX88140A reports to the host.
Most of the fields in this register cause the host to be interrupted.
REG5 bits are not cleared when read.
Writing 1 to these bits clears them; writing 0 has no effect. Each field can be masked.
Field
R/W/C
31:26
25:23
R
22:20
19:17
16
15
R
R
13
R
11
R/W/C
10
R/W/C
9
R/W/C
8
R/W/C
7
R/W/C
6
R/W/C
5
R/W/C
4
-
Description
Reserved
EB - Error Bits
(Not generate interrupt)
Indicates the type of error that
caused system error.
Valid only when fatal bus error
REG5<13> is set.
25
24
23
Description
0
0
0
Parity error
0
0
0
1
1
0
Master abort
Target abort
0
1
1
Reserved
1
x
x
Reserved
Reserved.--Written as “0” for future compatibility concern.
Reserved.--Written as “0” for future compatibility concern.
NIS - Normal Interrupt Summary
Only the unmasked bits affect normal interrupt summary REG5<16> bit Normal interrupt
summary bit. Its value is the logical OR of :
CSR5<0>
transmit interrupt
CSR5<2>
transmit buffer unavailable
CSR5<6>
receive interrupt
CSR5<10>
Early transmit interrupt
CSR5<11>
General-purpose timer expired
AIS - Abnormal Interrupt Summary
Only unmasked bits affect only the abnormal interrupt summary REG5<15> bit.
Abnormal interrupt summary bits. Its value is the logical OR of :
CSR5<1>
transmit process stopped
CSR5<3>
transmit jabber time out
CSR5<5>
transmit under-flow
CSR5<7>
receive buffer unavailable
CSR5<8>
receive process stopped
CSR5<9>
receive watchdog time out
CSR5<13>
fatal bus error
FBE - Fatal Bus Error
Indicates that a system error occurred. If a system error occurs, all bus accesses are disabled
GTE - General Purpose Timer Expired
Indicates that the general-purpose timer (REG11) counter has expired. This timer is mainly used
by the software driver.
ETI - Early Transmit Interrupt
Indicates that the packet to be transmitted was fully transferred into the chip‘s internal transmit
FIFOs. Transmit interrupt (REG5<0>) automatically clears this bit.
RWT - Receive watchdog Time out
Indicates that the receive watchdog timer expired and another node is still active on the network.
In case of overflow, the long packets may not be received.
RPS - Receive Process Stopped
Asserts when the receive process enters stopped state.
RU - Receive Buffer Unavailable
Indicates the next descriptor in the receive list is owned by the host and cannot be acquired by
the AX88140A.The reception process is suspended.
RI - Receive Interrupt
Indicates the completion of a frame reception. Specific frame status information has been posted
in the descriptor. The reception process remains in the running state.
UNF - Transmit Under-flow
Indicates that the transmit FIFO had an under-flow condition during the packet transmission.
The transmit process is placed in the suspended state and under-flow error TDES0<1> is set.
Reserved.--Written as “0” for future compatibility concern.
23
ASIX ELECTRONICS CORPORATION
AX88140A
3
R/W/C
2
R/W/C
1
R/W/C
0
R/W/C
PRELIMINARY
TJT - Transmit Jabber Time-out
Indicates that the transmit jabber timer expired, meaning that the AX88140A transmitter had
been excessively active. The transmission process is aborted and placed in the stopped state.
This event causes the transmit jabber time-out TDES0<14> is set.
TU - Transmit Buffer Unavailable
Indicates that the next descriptor on the transmit list is owned by the host and cannot be acquired
by the AX88140A.The transmission process is suspended. To resume processing transmit
descriptors, the host should change the ownership bit of the descriptor and then issue a transmit
poll demand command.
TPS - Transmit Process Stopped
Asserts when the transmit process enters the stopped state.
TI - Transmit Interrupt
Indicates that a frame transmission was completed, while TDES1<31> is asserted in the first
descriptor of the frame.
Tab - 20 REG5 Status Register Description
4.2.7 Operation Mode Register (REG6)
1.
2.
REG6 establishes the receive and transmit operating modes and commands.
REG6 should be the last REG to be written as part of initialization.
Field
R/W/C
31
30
R/W
29:25
24
R/W
23
R/W
22
R/W
21
R/W
20
19
R/W
18
R/W
Description
Reserved
RA - Receive All
1 All incoming packets will be received
0 Filtering mode
Reserved.--Written as “0” for future compatibility concern.
SCR - Scrambler Mode
1 Enable Scrambler
0 Disable Scrambler
PCS - PCS Mode
1 PCS functions are active
TTM - Transmit Threshold Mode
0
MII/SYM port is not selected
1
Threshold is 10Mb/s
0
Threshold is 100Mb/s
SF - Store and Forward
1 Enable Store and Forward
0 Disable Store and Forward
Reserved.--Written as “0” for future compatibility concern.
HBD - Heartbeat Disable
1 Heartbeat Disable
0 Heartbeat Enable
PS - Port Select
1 MII/SYM port is selected.
0
17:16
15:14
R/W
SRL port is selected
Reserved.--Written as “0” for future compatibility concern.
TR - Threshold Control Bits
The threshold value has a direct impact on the AX88140A bus arbitration scheme . Transmission starts when
the frame size within the transmit FIFO is larger than the threshold. In addition, full frames with a length
less than the threshold are also transmitted. The transmit process must be in the stopped state to change these
bits.
Controls the selected threshold level for the AX88140A transmit FIFO. Four threshold levels are allowed.
REG6<18>=0
REG6<18>=1
REG6<18>=1
REG6<21>
0
REG6<15:14>
00
0
01
96
96
256
0
10
128
128
512
0
11
160
160
1024
1
XX
Store & Forward
Store & Forward
Store & Forward
13
R/W
ST - Start/Stop Transmission
12
R/W
FC - Force Collision Mode
11:10
R/W
OM - Operating Mode
9
R/W
FD - Full-Duplex Mode
REG6<22>=X
72
1
0
1
0
00
01
10
1
24
REG6<22>=1
72
REG6<22>=0
128
Start Transmission
Stop Transmission
Enable force collision
Disable force collision
Normal
Internal Loop-back
External Loop-back
Full-Duplex
ASIX ELECTRONICS CORPORATION
AX88140A
8
R/W
7
R/W
6
R/W
5:4
3
R/W
2
1
R/W
0
R
PRELIMINARY
0
1
0
1
0
1
Half-Duplex
RB - Receive broadcast packet
Accept broadcast packet
Reject broadcast packet
PM - Pass All Multicast
Enable Pass All Multicast
Disable Pass All Multicast
PR - Promiscuous Mode
Indicates that any incoming valid frame is received,
regardless of its destination address.
0 Disable Promiscuous Mode.
Reserved.--Written as “0” for future compatibility concern.
PB - Pass Bad Frames
1 All incoming frames that passed the address
filtering are received, including runt frames,
collided fragments, or truncated frames caused by
FIFO over-flow. If any received bad frames are
required, promiscuous mode (REG6<6>) should be
set to 1.
0 Disable pass bad frame.
Reserved.--Written as “0” for future compatibility concern.
SR - Start/Stop Receive
1 Start Receive
0 Stop Receive
PLS - PCS_SYM Link Status : Active high.
Tab - 21 REG6 Operation Mode Register Description
Port and Data Rate Selection
REG6
<18>
REG6
<22>
REG6
<23>
REG6
<24>
ACTIVE
PORT
DATA
RATE
0
1
0
1
X
0
X
0
SRL
MII/SYM
10MB/S
10MB/S
1
0
0
0
MII/SYM
1
1
0
0
1
1
0
1
MII/SYM
MII/SYM
FUNCTION
Conventional 10MB/S ENDEC interface
MII with transmit FIFO thresholds appropriate
for 10MB/S
100MB/S MII with transmit FIFO thresholds appropriate
for 100MB/S
100MB/S PCS function for 100BASE-FX
100Mb/s PCS and scrambler functions for 100BASE-T
Tab - 22 Port and Data Rate Selection
25
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PRELIMINARY
4.2.8 Interrupt Enable Register (REG7)
1.
2.
The interrupt enable register (REG7) enables the interrupts reported by REG5.
Setting bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Field
R/W/C
31:17
16
R/W
15
R/W
13
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
NI - Normal Interrupt Summary Enable
When set, normal interrupt is enabled.
When reset, no normal interrupt is enabled. This bit (REG7<16>) enables the following bits :
CSR5<0>
Transmit interrupt
CSR5<2>
Transmit buffer unavailable
CSR5<6>
Receive interrupt
CSR5<10>
Early transmit interrupt
CSR5<11>
General-purpose timer expired
AI - Abnormal Interrupt Summary Enable
When set, abnormal interrupt is enabled.
When reset, no abnormal interrupt is enabled. This bit (REG7<15>) enables the following bits :
CSR5<1>
transmit process stopped
CSR5<3>
transmit jabber time-out
CSR5<5>
transmit under-flow
CSR5<7>
receive buffer unavailable
CSR5<8>
receive process stopped
CSR5<9>
receive watchdog time-out
CSR5<11>
fatal bus error
FBE - Fatal Bus Error interrupt enable. Active high.
GPT - General purpose Timer interrupt Enable. Active high.
ETE - Early Transmit Interrupt Enable. Active high.
RW - Receive Watchdog Time out interrupt Enable. Active high
RS - Receive Stopped interrupt Enable. Active high.
RU - Receive Buffer Unavailable interrupt Enable. Active high.
RI - Receive Interrupt Enable. Active high.
UN - under-flow interrupt Enable. Active high.
Reserved.--Written as “0” for future compatibility concern.
TJ - Transmit Jabber Time out interrupt Enable. Active high.
TU - Transmit Buffer Unavailable interrupt Enable. Active high.
TS - Transmission Stopped interrupt Enable. Active high.
TI - Transmit Interrupt Enable. Active high.
Tab - 23 REG7 Interrupt Enable Register Description
4.2.9 Missed Frame and Overflow Counter (REG8)
Field
R/W
31:29
28
R/C
27:17
R/C
16
R/C
15:0
R/C
Description
Reserved
Overflow counter overflow
Sets When the overflow counter overflows, Resets When REG8 is read.
Overflow counter
Indicates the number of frames discarded because of overflow. The counter clears when read.
Missed frame overflow
Sets When the missed frame counter overflows; Resets When reg8 is read.
Missed Frame Counter
Indicates the number of frames discarded because no host receive descriptors were available. The counter
clears when read.
Tab - 24 REG8 Missed Frame and Overflow Counter Description
26
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4.2.10 Serial ROM and MII Management Register (REG9)
1.
2.
The register provides an interface to the Microwire serial ROM and to the physical layer
protocol (PHY). It selects the device and contains both the commands and data to be read from
and stored in the serial ROM.
The MII management selects and operation mode for reading and writing the MII.
FIELD
R/W/C
DESCRIPTION
31:20
19
R
18
R/W
17
R/W
16
R/W
14
R/W
13:12
11
R/W
10:4
3
R/W
2
R
Reserved.--Written as “0” for future compatibility concern.
MDI - MII management data_in
Used by the AX88140A to read data from the PHY
MII - MII management operation mode
Defines the operation mode (read or write) of the PHY.
MDO - MII Management write data
Specifies the value of the data that AX88140A writes to the PHY
MDC - MII Management clock
MII management data clock (MII_MDC) is an output signal to the PHY. it is used as a timing
reference.
RD - Read operation
Read control bit. When set together with REG9<12>, The AX88140A performs read cycles from the
BOOT ROM, and the serial ROM.
Reserved.--Written as “0” for future compatibility concern.
SR - SERIAL ROM select
When set together with either SERIAL ROM read operation (REG9<14>) or SERIAL ROM Write
operation (REG9<13>), The AX88140A selects the SERIAL ROM.
Reserved.--Written as “0” for future compatibility concern.
SDO - SERIAL ROM data_out
SERIAL ROM data output(SR_DO) From the SERIAL ROM device to the AX88140A.
SDI - SERIAL ROM data_in
SERIAL ROM Data input(SR_DI) To the SERIAL ROM device from the AX88140A.
1
R/W
SCLK - SERIAL ROM serial clock
Serial clock (SR_CK) Output to the SERIAL ROM.
0
R/W
SCS - Serial ROM Chip Select
Chip select (sr_cs) output to the serial ROM.
Tab - 25 REG9 Serial ROM, and MII Management Register Description
4.2.11 General -Purpose Timer (REG11)
1.
2.
This register contains a 16 bit general-purpose timer. It is used mainly by the software driver
for timing functions not supplied by the operating system. After the timer is loaded, it starts
counting down . The expiration of the timer causes an interrupt in REG5<11>.
If the timer expires with the CON bit on, the counter will load itself automatically with the last
value. The timer is not active in snooze mode.
Field
31:17
16
R/W/C
R/W
Description
Reserved.--Written as “0” for future compatibility concern.
CON - Continuous Mode
1
Continuous operating mode.
0
15:0
R/W
One-shot operating mode.
Timer value
Contains the general-purpose timer value within a N microsecond cycle.
SRL_10M : 204.8us
MII_10M
: 819.2us
MII_100M : 81.92us
27
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
Tab - 26 REG11 General -Purpose Timer Register Description
4.2.12 General -Purpose Port Register (REG12)
Field
R/W/C
31:9
-
8
R/W
Description
Reserved.--Written as “0” for future compatibility concern.
GPC - General Purpose Control .
When a hardware reset is initiated, all gep pins
become input pins.
1
Indicate next write REG12<7:0> is use
for define General purpose port in/out
direction.
Indicate next write REG12<7:0> is use
for read/write general purpose port data.
0
7:0
R/W
MD - General Purpose Mode and Data
Tab - 27 REG12 General -Purpose Port Register Description
4.2.13 Filtering Index (REG13)
FIELD
R/W/C
DESCRIPTION
31:6
5:0
R/W
Reserved.--Written as “0” for future compatibility concern.
FI - Filtering Index
When writing data to filtering buffer, uses filtering index register REG13 to point the position (buffer
number) in filtering buffer. The valid value is between 0 and 3.
Tab - 28 REG13 Filtering Index Register Description
4.2.14 Filtering data (REG14)
FIELD
R/W/C
DESCRIPTION
31:0
R/W
FD - Filtering Data
By indexed by filtering index register REG13, write the filtering data register REG14 to put filtering
address/hash table into filtering buffer..
Tab - 29 REG14 Filtering Data Register Description
Filtering Buffer
The AX88140A stores one Ethernet address for local physical address and filters the packets
with multicast addresses by 64 bits array. For any incoming frame with a multicast destination
address, the AX88140A applies the standard Ethernet cyclic redundancy check function to the
destination address, then uses the most significant 6 bits of the result as a bit index into the table. If
the indexed bit is set, the frame is accepted. If the bit is reset, the frame is rejected.
Description of Filtering Buffer
BUFFER
NUMBER
0
1
2
3
DESCRIPTION
BYTE 0 - 3 OF LOCAL PHYSICAL ADDRESS
BYTE 4 - 5 OF LOCAL PHYSICAL ADDRESS IN THE LEAST SIGNIFICANT WORD
BIT 0 - 31 OF MULTICAST ADDRESS FILTERING TABLE
Bit 32 - 63 of multicast address filtering table
Tab - 30 Description of Filtering Buffer
Layout of Filtering Buffer
BUFFER
NUMBER
BYTE 3
0
PHYSICAL
ADDRESS BYTE 3
BYTE 2
BYTE 1
PHYSICAL ADDRESS PHYSICAL ADDRESS
BYTE 2
BYTE 1
28
BYTE 0
PHYSICAL ADDRESS
BYTE 0
ASIX ELECTRONICS CORPORATION
AX88140A
1
2
3
PRELIMINARY
RESERVED
RESERVED
PHYSICAL ADDRESS PHYSICAL ADDRESS
BYTE 5
BYTE 4
MULTICAST ADDRESS
MULTICAST
ADDRESS FILTERING FILTERING TABLE BIT
0-7
TABLE BIT 8 - 15
MULTICAST
MULTICAST
ADDRESS
ADDRESS
FILTERING TABLE FILTERING TABLE
BIT 16 - 23
BIT 24 - 31
multicast address
multicast address filtering multicast address filtering
multicast address
table bit 40 - 47
table bit 32 - 39
filtering table bit 56 - filtering table bit 48 - 55
63
Tab - 31 Layout of Filtering Buffer
29
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AX88140A
PRELIMINARY
5.0 Host Communication
Descriptor lists and data buffers, collectively called the host communication, reside in the host
memory and manage the actions and status related to buffer management.
5.1 Descriptor Lists and Data Buffers
The AX88140A transfers data frames to the receive buffers and from the transmit buffers in host
memory. Descriptors that reside in the host memory act as pointers to these buffers.
There are two descriptor lists, one for receive and one for transmit. The base address of each list is
written into REG3 and REG4, respectively. A descriptor list is forward-linked (explicitly). The
last descriptor may point back to the first entry to create a ring structure. Explicit chaining of
descriptors is accomplished by setting the address pointer chained in both the receive and transmit
descriptors (RDES3 and TDES3). The descriptor lists reside in the host physical memory address
space.
A data buffer consists of either an entire frame or part of a frame, but it cannot exceed a single
frame. Buffers contain only data; buffer status is maintained in the descriptor. Data chaining refers
to frames that span multiple data buffers.
Descriptor Structure Example
Buffer 1
Descriptor 0
Buffer 2
Descriptor 1
Next Descriptor
Fig - 4 Descriptor Structure Example
30
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PRELIMINARY
5.2 Receive Descriptors
The receive descriptor provides one buffer, one byte-count buffer, and one address pointer in
each descriptor. Descriptors and receive buffers addresses must be long-word aligned.
Receive Descriptor Format
RDES0
RDES1
31
O
W
N
0
Status
Control bits
Byte Count Buffer 2
RDES2
Buffer Address 1
RDES3
Buffer Address 2
Byte Count Buffer 1
Fig - 5 Receive Descriptor Format
5.2.1 Receive Descriptor 0 (RDES0)
RDES0 contains the received frame status, the frame length, and the descriptor ownership
information.
Field
31
30
29:16
15
14
13:12
11
Description
OWN - Own Bit
The AX88140A clears this bit either when it completes
the frame reception or
when the buffers that are associated with this descriptor
are full.
FF - Filtering Fail
This bit can be set only when receive all (REG6<30>) is
set.
1
0
1
0
Indicates that the descriptor is owned by the
AX88140A
Indicates that the descriptor is owned by the host
Indicates that the frame failed the address
recognition filtering
Indicates that the frame passed the address
recognition filtering
FL - Frame Length
Indicates the length in bytes of the received frame including the cyclic redundancy check (CRC).
This field is valid only when last descriptor (RDES0<8>) is set and descriptor error ( RDES0<14>) is reset.
ES - Error Summary
Indicates the logical OR of the following RDES0 bits :
This field is valid only when last descriptor (RDES0<8>) is set.
RDES0<1>
CRC error
RDES0<6>
collision seen
RDES0<7>
frame too long
RDES0<11>
runt frame
RDES0<14>
descriptor error
DE - Descriptor Error. The frame is truncated. Active high.
This field is valid only when last descriptor (RDES0<8>) is set.
Reserved.--Written as “0” for future compatibility concern.
RF - Runt Frame. Indicates that this frame is a runt frame. Active high.
This field is valid only when last descriptor (RDES0<8>) is set .
31
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AX88140A
PRELIMINARY
10
MF - Multicast Frame Indicates that this frame is a multicast address.
This field is valid only when last descriptor (RDES0<8>) is set.
9
FS - First Descriptor
8
LS - Last Descriptor
1
Indicates that this descriptor contains the first buffer of a
frame.
0
Indicates that this descriptor is the middle or last buffer of
a frame.
Indicates that the buffers pointed to by this descriptor, are
the last buffers
Indicates that this descriptor is the middle or first buffer of
a frame.
1
0
7
TL - Frame Too Long. Frame length grater then 1518 bytes. Active high.
This field is valid only when last descriptor (RDES0<8>) is set.
6
CS - Collision Seen. This is a late collision.
This field is valid only when last descriptor (RDES0<8>) is set.
5
4
Reserved.--Written as “0” for future compatibility concern.
RW - Receive Watchdog time expire. Active high.
This field is valid only when last descriptor (RDES0<8>) is set.
3
2
RE - Report on MII Error. Active high.
DB - Dribbling Bit Active high.
If set, and CRC error (RDES0<1>) is reset, then the packet is valid.
CE - CRC Error. Active high.
This field is valid only when last descriptor (RDES0<8>) is set.
FIFO Overrun. Active high.
1
0
Tab - 32 Receive Descriptor 0
5.2.2 Receive Descriptor 1 (RDES1)
FIELD
31:11
10:0
DESCRIPTION
Reserved.--Written as “0” for future compatibility concern.
RBS - Receive Data Buffer Size
Indicates the size in bytes of the data buffer. If this field is 0, the AX88140A ignores this buffer.
The buffer size must be a multiple of 4.
Tab - 33 Receive Descriptor 1
5.2.3 Receive Descriptor 2 (RDES2)
FIELD
31:0
DESCRIPTION
Data Buffer Pointer
Indicates the physical address of data buffer. The buffer must be long-word-aligned (RDES2<1:0>=00).
Tab - 34 Receive Descriptor 2
5.2.4 Receive Descriptor 3 (RDES3)
FIELD
31:0
DESCRIPTION
Address Pointer
Indicates the physical address of next descriptor. The address must be long-word aligned (RDES3<1:0>=00).
Tab - 35 Receive Descriptor 3
32
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5.3 Transmit Descriptors
Providing one buffer, one byte-count buffer, and two address pointers in each descriptor .
Transmit Descriptor Format
31
O
TDES0
W
N
TDES1
0
Status
Control bits
Byte Count Buffer 2
TDES2
Buffer Address 1
TDES3
Buffer Address 2
Byte Count Buffer 1
Fig - 6 Transmit Descriptor Format
5.3.1 Transmit Descriptor 0 (TDES0)
TDES0 contains transmitted frame status and descriptor ownership information.
Field
31
30:16
15
14
13:12
11
10
9
8
7
6:3
2
Description
OWN - Own Bit
1
Indicates that the descriptor is owned by the AX88140A.
0
Indicates that the descriptor is owned by the host.
Reserved.--Written as “0” for future compatibility concern.
ES - Error Summary
Indicates the logical OR of the following bits :
TDES0<1>
under-flow error
TDES0<8>
successive collisions
TDES0<9>
late collision
TDES0<10>
no carrier
TDES0<11>
loss of carrier
TDES0<14>
transmit jabber time-out
TO - Transmit Jabber Time-out : Active high.
The transmission process is aborted and placed in the STOPPED state.
When TDES0<14> is set any heartbeat fail indication (TDES0<7>) is not valid.
Reserved.--Written as “0” for future compatibility concern.
LO - Loss of Carrier during transmission. Active high. (The status is no meaning except 10BASE SRL mode)
Not valid in internal loop-back mode (REG6<11:10>=01).
NC - No Carrier. Indicates that the carrier signal from the transceiver was not present during transmission.
Active high.
Not valid in internal loop-back mode (REG6<11:10>=01).
LC - Late Collision. When set, indicates that the frame transmission was aborted due to collision occurring after
the collision window of 64 bytes. Not valid if under-flow error (TDES0<1>) is set.
EC - Excessive Collision When set, indicates that the transmission was aborted after 16 successive collisions
while attempting to transmit the current frame.
HF - Heartbeat Fail
This bit is effective only in 10Mb/s operation mode. When set, indicates a heartbeat collision check failure
This bit is not valid if under-flow error (TDES0<1>) is set.
On the second transmission attempt, after the first transmission was aborted due to collision, the AX88140A
does not check heartbeat fail and (TDES0<7>) is reset.
CC - Collision Count
This 4-bit counter indicates the number of collisions that occurred before the frame was transmitted.
Not valid when the excessive collisions bit (TDES0<8>) is also set.
Reserved.--Written as “0” for future compatibility concern.
33
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AX88140A
1
0
PRELIMINARY
UF - Under-flow Error
When set, indicates that the transmitter aborted the message because data arrived late from memory. Underflow error indicates that the AX88140A encountered an empty transmit FIFO while transmitting a frame. The
transmission process enters the suspended state and sets both transmit under-flow (REG5<0>) and transmit
interrupt (REG5<0>).
DE - Deferred
When set, indicates that the AX88140A had to defer while ready to transmit a frame because the carrier was
asserted.
Tab - 36 Transmit Descriptor 0
5.3.2 Transmit Descriptor 1 (TDES1)
Field
Description
31
IC - Interrupt on Completion
When set, the AX88140A sets transmit interrupt (REG5<0>) after the present frames has been transmitted. It is
valid only when first segment (TDES1<30>) is set.
LS - Last Segment
1 Indicates that the buffer contains the last segment of a
frame.
30
29
28:27
26
25:24
23
FS - First Segment
0
Indicates that the buffer contains the first or middle
segment of a frame.
1
Indicates that the buffer contains the first segment of a
frame.
0
Indicates that the buffer contains the middle or last segment
of a frame.
Reserved.--Written as “0” for future compatibility concern.
AC - Add CRC Disable
When set, the AX88140A does not append the CRC to the end of the transmitted frame. This field is valid only
when first segment (TDES1<29>) is set.
Reserved.--Written as “0” for future compatibility concern.
DPD - Disabled Padding
1 the AX88140A does not automatically add a padding field,
The CRC field is added despite the state of
so a packet shorter than 64 bytes.
the add CRC disable (TDES1<26>) flag.
0
22:11
10:0
The AX88140A automatically adds a padding field and also
a CRC field to a packet shorter than 64 bytes.
Reserved.--Written as “0” for future compatibility concern.
Data Buffer Size
Indicates the size, in bytes, of the data buffer. If this field is 0, the AX88140A ignores this buffer.
Tab - 37 Transmit Descriptor 1
5.3.3 Transmit Descriptor 2 (TDES2)
Field
31:0
Description
Data Buffer Pointer
Physical address of data buffer. There are no limitations on the buffer address alignment.
Tab - 38 Transmit Descriptor 2
5.3.4 Transmit Descriptor 3 (TDES3)
Field
31:0
Description
Address Pointer
Physical address of next descriptor address. There are no limitation on the buffer address alignment.
Tab - 39 Transmit Descriptor 3
34
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Operating Temperature
Ta
0
+70
°C
Storage Temperature
Ts
-55
+150
°C
Supply Voltage
Vcc
-0.5
+7
V
Input Voltage
Vin
Vss-0.5
Vdd+0.5
V
Output Voltage
Vout
Vss-0.5
Vdd+0.5
V
Lead Temperature (soldering 10 seconds maximum)
Tl
-55
+250
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability
6.2 General Operation Conditions
Description
Operating Temperature
Supply Voltage
SYM
Min
0
+4.75
Max
+70
+5.25
Units
°C
V
SYM
Min
Vss-0.5
2
2.4
-
Max
0.8
Vdd+0.5
0.4
10
500
10
Units
V
V
V
V
uA
uA
uA
Ta
Vdd
6.3 DC Characteristics
(Vdd=4.75V to 5.25V, Vss=0V, Ta=0°C to 70°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current 1 (Note 1)
Input Leakage Current 2 (Note 2)
Output Leakage Current
Vil
Vih
Vol
Voh
Iil1
Iil1
Iol
Note :
1.
All the input pins without pull low or pull high.
2.
Those pins had been pull low or pull high.
35
ASIX ELECTRONICS CORPORATION
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6.4 A.C. Timing Characteristics
6.4.1 PCI CLOCK
Symbol
Tcyc
Thigh
Tlow
Tr/Tf
Description
CYCLE TIME
PCI_CLK HIGH TIME
PCI_CLK LOW TIME
PCI_CLK SLEW RATE
Min
30
11
11
1
Typ.
-
Max
45
4
Units
ns
ns
ns
ns
Min
2
2
7
0
Typ.
-
Max
11
28
-
Units
ns
ns
ns
ns
ns
Min
10
Typ.
-
Max
-
Units
PCI Clk
6.4.2 PCI Timings
PCI_CLK
Tval
(max)
Tval
(min)
OUTPUT
Ton
Toff
INPUT
Tsu
Symbol
Tval
Ton
Toff
Tsu
Th
Th
Description
CLK TO SIGNAL VALID DELAY
FLOAT TO ACTIVE DELAY
ACTIVE TO FLOAT DELAY
INPUT SETUP TIME TO CLK
INPUT HOLD TIME FROM CLK
6.4.3 Reset Timing
PCI_CLK
RST#
Symbol
Trst
Description
Reset pulse width
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ASIX ELECTRONICS CORPORATION
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6.4.4 MII/SYM Timing
Ttclk
Ttch
Ttcl
MTCLK/SYMTCLK
Ttv
Tth
MTXD<3:0>/SYMTXD<3:0>
MTXEN/SYMTXEN
Trclk
Trch
Trcl
MRCLK/SYMRCLK
Trs
Trh
MRXD<3:0>/SYMRXD<3:0>
MTXEN/SYMTXEN
Trs1
MRXERR,SD
Symbol
Ttclk
Ttclk
Ttch
Ttch
Trch
Trch
Ttv
Tth
Trclk
Trclk
Trch
Trch
Trcl
Trcl
Trs
Trh
Trs1
Description
Min
14
140
14
140
5
14
140
14
140
6
10
10
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
Clock to data valid
Data output hold time
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
data setup time
data hold time
SD, MRXERR data setup time
37
Typ.
40
400
40
400
-
Max
26
260
26
260
20
26
260
26
260
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
6.4.5 10Mbps serial timing
Tstc
Tstcl
SRL_TCLK
Tsto
Tstch
Tsth
SRL_TXD
SRL_TXEN
Tsto1
Tsrc
SRL_RCLK
Tsrs
Tsrch
Tsrcl
Tsrh
SRL_RXD
SRL_RXEN
Symbol
Tstc
Tstch
Tstcl
Tsto
Tsto1
Tsth
Tsrc
Tsrch
Tsrcl
Tsrs
Tsrh
Description
SRL_TCLK Cycle time
Clock high time
Clock low time
Data output delay
SRL_TXEN data output delay
Data output hold time
SRL_RCLK Cycle time
Clock high time
Clock low time
Data input Setup time
Data input hold time
Min
85
45
45
5
85
45
45
10
5
38
Typ.
-
Max
118
55
55
26
26
118
55
55
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
6.4.6 Boot ROM Read Cycles
Boot ROM Byte Read Cycle
br_ad<7:0>
address 9-2
address 17-10
data
br_a1
address 1
br_a0
address 0
brce#
Boot ROM Dword Read Cycle
br_ad<7:0>
address 9-2
address 17-10
data3
data2
data1
data0
br_a1
br_a0
brce#
39
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
7.0 Package Information
A2
A1
L
L1
D
Hd
He
E
pin 1
e
b
θ
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AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
SYMBOL
MILIMETER
MIN.
NOM
MAX
A1
0.05
0.25
0.5
A2
3.17
3.32
3.47
b
0.20
0.30
0.40
D
27.90
28.00
28.10
E
27.90
28.00
28.10
e
0.65
Hd
30.95
31.20
31.45
He
30.95
31.20
31.45
L
0.65
0.80
0.95
L1
θ
1.60
0
10
40
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
APPENDIX
A H/W NOTE
A.1 Boot ROM read cycle
ASIX 88140 Boot ROM Byte Read Cycle
br_ad<7:0>
address 9-2
address 17-10
data
br_a1
address 1
br_a0
address 0
brce#
27512
74LS374
BRAD0
BRAD1
BRAD2
BRAD3
BRAD4
BRAD5
BRAD6
BRAD7
GND
BRA1
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
74LS374
A10
A11
A12
A13
A14
A15
A16
A17
D0
D1
D2
D3
D4
D5
D6
D7
GND
OC
CLK
BRA0
BRA1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A2
A3
A4
A5
A6
A7
A8
A9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OC
CLK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BR_CE
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
BRAD0
BRAD1
BRAD2
BRAD3
BRAD4
BRAD5
BRAD6
BRAD7
/CE
/OE
DEC 21140 Boot ROM Byte Read Cycle:
br_ad<7:0>
address 7-2
address 15-8
data
br_a1
address 1
br_a0
address 17
address16
address 0
brce#
27512
74LS374
BRAD0
BRAD1
BRAD2
BRAD3
BRAD4
BRAD5
BRAD6
BRAD7
GND
BRA1
D0
D1
D2
D3
D4
D5
D6
D7
OC
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
BRA0
BRA1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
74LS374
A8
A9
A10
A11
A12
A13
A14
A15
GND
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
/WE
/OE
A2
A3
A4
A5
A6
A7
OC
CLK
BR_CE
/OE
41
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
BRAD0
BRAD1
BRAD2
BRAD3
BRAD4
BRAD5
BRAD6
BRAD7
/CE
/OE
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
A.2 Power Supply
AX88140A power supply is +5V DC
DEC 21140 power supply is +3.3V DC
A.3 Boundary Scan Test Pins
AX88140A do not support boundary scan test pins
DEC 21140 supports boundary scan test pins
42
ASIX ELECTRONICS CORPORATION
AX88140A
APPENDIX
PRELIMINARY
B Function Application
B.1 Application for PCI Interface
Features :
l Direct interface to PCI Bus.
l Support 33 MHz no wait state PCI Bus Interface.
l Powerful on chip buffer management DMA. And PCI Bus master operation reduce CPU
utilization.
l 5 Volt CMOS process.
PCI Interface Schematic:
PCI BUS CONNECTOR
AX88140A PCI I/O PINS
AD[31:0]
C/BE[3:0]
PAR
PCI SLOT
MAC
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#
CLK
RST#
The pull high resisters are required for pin REQ#, GNT#, PERR#, and SERR# on MAC for more detail please to
check the schematic.
43
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
B.2 Application for Boot ROM Interface
AX88140A
Boot ROM Byte Read Cycle
BR_AD<7:0>
address 9-2
address 17-10
data
BR_A1
address 1
BR_A0
address 0
BRCE#
27512
74LS374
BRAD0
BRAD1
BRAD2
BRAD3
BRAD4
BRAD5
BRAD6
BRAD7
GND
BRA1
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OC
CLK
BRA0
BRA1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
74LS374
A10
A11
A12
A13
A14
A15
A16
A17
GND
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A2
A3
A4
A5
A6
A7
A8
A9
OC
CLK
BR_CE
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
BRAD0
BRAD1
BRAD2
BRAD3
BRAD4
BRAD5
BRAD6
BRAD7
/CE
/OE
B.3 Application for Serial ROM Interface
AX88140A
Serial ROM Interface
Serial ROM Chip Select
Serial ROM Clock
Serial ROM Data In
Serial ROM Data Out
44
Serial ROM
93C46
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
B.4 Application for PHY Interface
B.4.1 AX88140A, QSI6611, & MTD213 Application
SNI
RJ-45
ST 6114
X‘former
QSI 6611
Transceiver
for 100BASE TX
Scrambler /
Descrambler
5/4 bit converter
AX88140A
MAC Controller
MTD213
10 BASE T
Transceiver
Fig - 7 Application for PCS / Serial Mode
B.4.2 Application for MII Mode : LEVEL ONE LXT970
MII
STA
A.N.
LXT970
PHY
4B/5B
RJ-45
MII
ST 6114
X‘former
AX88140A
MAC Controller
10BASE-T
Transceiver
Scrambler /
Descrambler
Fig - 8 Application for MII Mode with LXT970
45
ASIX ELECTRONICS CORPORATION
AX88140A
PRELIMINARY
B.4.3 Application for MII Mode : MYSON MTD972 + MTD971
MII
STA
A.N.
MTD972 PHY +
MTD971 T/R
RJ-45
MII
ST 6166
X‘former
AX88140A
MAC Controller
10BASE-T
Transceiver
Scrambler /
Descrambler
4B/5B
Fig - 9 Application for MII Mode with MTD972 +MTD971
B.4.4 Application for MII Mode : DAVICOM DM9101
MII
STA
A.N.
DM9101
PHY
Scrambler /
Descrambler
4B/5B
RJ-45
MII
YCL 20PMT04
X‘former
AX88140A
MAC Controller
10BASE-T
Transceiver
Fig - 10 Application for MII Mode with DM9101
46
ASIX ELECTRONICS CORPORATION