AUSTIN AS4LC4M4883C

AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
DRAM
4 MEG x 4 DRAM
3.3V, EDO PAGE MODE
AVAILABLE IN MILITARY
SPECIFICATIONS
PIN ASSIGNMENT (Top View)
• MIL-STD-883
• SMD Planned
24/28-Pin
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• Low power, 1mW standby; 150mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR)
HIDDEN
• 2,048-cycle (11 row-, 11 column-addresses)
• Extended Data-Out (EDO) PAGE access cycle
• 5V-tolerant I/Os (5.5V maximum VIH level)
OPTIONS
MARKING
• Timing
60ns access (Contact Factory)
70ns acess
80ns access
ECJ
EC
ECG
No. 505
No. 212
No. 603
KEY TIMING PARAMETERS
SPEED
-6
-7
-8
tRC
110ns
130ns
150ns
tRAC
60ns
70ns
80ns
tPC
30ns
35ns
40ns
tAA
30ns
35ns
40ns
tCAC
15ns
18ns
20ns
tCAS
12ns
15ns
20ns
GENERAL DESCRIPTION
The AS4LC4M4 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 configuration. The AS4LC4M4 ?R?A/S is used to latch the first 11
bits and ?C?A/S the latter 11 bits. READ and WRITE cycles are
selected with the ? W / E input. A logic HIGH on
?W/E dictates READ mode while a logic LOW on ?W/E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of ?W/E or ?C?A/S, whichever occurs last. If
?W/E goes LOW prior to ?C?A/S going LOW, the output pins
remain open (High- Z) until the next ?C?A/S cycle, regardless
of ?O/E.
AS4LC4M4
Rev. 11/97
DS000022
11
22
33
44
55
66
28
26
27
25
26
24
25
23
24
22
23
21
VSS
DQ4
DQ3
/C/A/S
/O/E
A9
A10
A0
A1
A2
A3
VCC
98
10
9
11
10
12
11
13
12
14
13
20
19
19
18
18
17
17
16
16
15
15
14
A8
A7
A6
A5
A4
Vss
A logic HIGH on ?W/E dictates READ mode while a logic
LOW on ?W/E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of ?W/E or /C/A/S,
whichever occurs last. An EARLY WRITE occurs when
?W/E is taken LOW prior to /C/A/S falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when ?W/E falls after /C/A/S
was taken LOW. During EARLY WRITE cycles, the dataoutputs (Q) will remain High-Z regardless of the state of
O
? E
/ . During LATE WRITE or READ-MODIFY-WRITE cycles,
?O/E must be taken HIGH to disable the data-outputs prior to
applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping ?O/E LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by ?W/E and ?O/E.
-6
-7
-8
• Packages
Ceramic SOJ
Ceramic LCC
Ceramic Gull Wing
VCC
DQ1
DQ2
/W/E
/R/A/S
NC
FAST PAGE MODE
FAST PAGE operations allow faster data operations
(READ, WRITE or READ-MODIFY-WRITE) within a rowaddress-defined page boundary. The FAST PAGE cycle is
always initiated with a row-address strobed-in by ?R?A/S
followed by a column-address strobed-in by C
? ?A/S. ?C?A/S may
be toggled-in by holding ?R?A/S LOW and strobing-in different column-addresses, thus executing faster memory cycles.
Returning R?A/S HIGH terminates the FAST PAGE MODE
of operation.
2-73
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO PAGE MODE
?R?A/S and ?C?A/S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If ?O/E is toggled or
pulsed after ?C?A/S goes HIGH while ?R?A/S remains LOW,
data will transition to and remain High-Z (refer to Figure 1).
?W/E can also perform the function of disabling the output
devices under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR’d,
?O/E must be used to disable idle banks of DRAMs. Alternatively, pulsing ?W/E to the idle banks during ?C?A/S high time
will also High-Z the outputs. Independent of ?O/E control,
the outputs will disable after tOFF, which is referenced
from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
The AS4LC4M4E8 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
?C?A/S returns HIGH. EDO allows ?C?A/S precharge time (tCP)
to occur without the output data going invalid. This elimination of ?C?A/S output control allows pipeline READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
?C?A/S. EDO-PAGE-MODE DRAMs operate similarly to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after ?C?A/S goes HIGH during READs,
provided ?R?A/S and ?O/E are held LOW. If ?O/E is pulsed while
RAS
V IH
V IL
,, ,,, ,,,,,, ,,,,, ,,,,,, ,,,,
,
, , ,
CAS
ADDR
V IH
V IL
V IH
V IL
DQ V IOH
V IOL
ROW
COLUMN (A)
OPEN
COLUMN (B)
,,
VALID DATA (A)
VALID DATA (A)
t OD
OE
V IH
V IL
COLUMN (C)
,,, ,,
VALID DATA (C)
VALID DATA (B)
t OD
t OES
t OE
COLUMN (D)
,
VALID DATA (D)
t OD
t OEHC
t OEP
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS cycle
if tOEHC is met.
The DQs remain High-Z
until the next CAS cycle
if tOEP is met.
Figure 1
OUTPUT ENABLE AND DISABLE
AS4LC4M4
Rev. 11/97
DS000022
2-74
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
REFRESH
Preserve correct memory cell data by maintaining power and executing a ?R?A/S cycle (READ, WRITE) or ?R?A/S refresh cycle
(?R?A/S ONLY, CBR, or HIDDEN) so that all 2,048 combinations of R
? ?AS
/ addresses are executed at least every 32ms, regardless
of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic ?R?A/S addressing.
,, ,,, ,,,,,,, ,,,,, ,,,,,
,,,
,,,
,,
RAS
V IH
V IL
CAS
V IH
V IL
ADDR
V IH
V IL
DQ V IOH
V IOL
WE
V IH
V IL
OE
V IH
V IL
ROW
COLUMN (A)
OPEN
COLUMN (B)
,,
COLUMN (C)
,
VALID DATA (A)
t WHZ
t WPZ
The DQs go to High-Z if WE falls, and if tWPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
VALID DATA (B)
COLUMN (D)
,,
INPUT DATA (C)
t WHZ
,,
,,
,,,
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 2
?W/E CONTROL OF DQs
AS4LC4M4
Rev. 11/97
DS000022
2-75
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
FUNCTIONAL BLOCK DIAGRAM
WE
CAS
4
DATA-IN
BUFFER
DATA-OUT
BUFFER
NO. 2 CLOCK
GENERATOR
DQ1
DQ2
DQ3
DQ4
4
4
OE
11
COLUMNADDRESS
BUFFER(11)
10
COLUMN
DECODER
1
1024
REFRESH
CONTROLLER
4
SENSE AMPLIFIERS
I/O GATING
RAS
11
2048
2048
2048
2048
2048
ROW SELECT
(2 of 4096)
11
COMPLEMENT
SELECT
11
ROWADDRESS
BUFFERS (11)
4096 x 1024 x 4
MEMORY
ARRAY
NO. 1 CLOCK
GENERATOR
ROW TRANSFER
ROW
TRANSFER
(1 OF
2)
(1 OF 2)
1024
REFRESH
COUNTER
ROW
DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VDD
Vss
TRUTH TABLE
ADDRESSES
DATA-IN/OUT
FUNCTION
?R?A/S
?C?A/S
?W/E
?O/E
tR
Standby
H
H>X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
tC
DQ1-DQ4
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H>L
L>H
ROW
COL
Data-Out, Data-In
EDO-PAGE-MODE
1st Cycle
L
H>L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H>L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H>L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H>L
L
X
n/a
COL
Data-In
Any Cycle
L
L>H
H
L
n/a
n/a
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H>L
H>L
L>H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H>L
H>L
L>H
n/a
COL
Data-Out, Data-In
HIDDEN
READ
L>H>L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L>H>L
L
L
X
ROW
COL
Data-In
L
H
X
X
ROW
n/a
High-Z
H>L
L
H
X
X
X
High-Z
?R?A/S-ONLY REFRESH
CBR REFRESH
AS4LC4M4
Rev. 11/97
DS000022
2-76
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC pin Relative to VSS ................. -1V to +4.6V
Voltage on NC, Inputs or I/O pins
Relative to VSS .................................................... -1V to +5.5V
Operating Temperature, TA (ambient) .. TA(MIN) = -55°C
................................................................... TC (MAX) = 125°C
Storage Temperature ................................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (VCC = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
VCC
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs (including NC pins)
VIH
2.0
VCC+1
V
Input Low (Logic 0) Voltage, all inputs (including NC pins)
VIL
-1.0
0.8
V
II
-2
2
µA
OUTPUT LEAKAGE CURRENT (Q is disabled; 0V ≤ VOUT ≤ 5.5V) Vcc=3.6V
IOZ
-10
10
µA
OUTPUT LEVELS
Output High Voltage (IOUT = -2mA)
Output Low Voltage (IOUT = 2mA)
VOH
2.4
INPUT LEAKAGE CURRENT
Vcc = 3.6V
Any input 0V ≤ VIN ≤ 5.5V
(All other pins not under test = 0V) (NC pins not tested)
VOL
NOTES
V
0.4
V
MAX
PARAMETER/CONDITION
SYM
-6
-7
-8
UNITS
STANDBY CURRENT: (TTL)
(?R?A/S = ?C?A/S = VIH)
ICC1
2
2
2
mA
STANDBY CURRENT: (CMOS)
(?R?A/S = ?C?A/S = other inputs = VCC -0.2V
ICC2
1
1
1
mA
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(?R?A/S, ?C?A/S, address cycling: tRC = tRC [MIN])
ICC3
120
110
100
mA
3, 4, 12
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(?R?A/S = VIL, ?C?A/S, address cycling: tPC = tPC [MIN])
ICC4
110
100
90
mA
3, 4, 12
REFRESH CURRENT: ?R?A/S ONLY
Average power supply current
(?R?A/S cycling, ?C?A/S = VIH: tRC = tRC [MIN])
ICC5
120
110
100
mA
3, 12
REFRESH CURRENT: CBR
Average power supply current
(?R?A/S, ?C?A/S, address cycling: tRC = tRC [MIN])
ICC6
120
110
100
mA
3, 5
AS4LC4M4
Rev. 11/97
DS000022
2-77
NOTES
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: Address pins
CI 1
7
pF
2
Input Capacitance: ?R?A/S, ?C?A/S, ?W/E, ?O/E
CI 2
7
pF
2
Input/Output Capacitance: DQ
CIO
8
pF
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address set-up to ?C?A/S precharge during write
Column-address hold time (referenced to ?R?A/S)
Column-address setup time
Row-address setup time
Column-address to ?W/E delay time
Access time from ?C?A/S
Column-address hold time
?C?A/S pulse width
?C?A/S hold time (CBR REFRESH)
?C?A/S to output in Low-Z
Data output hold after next ?C?A/S LOW
?C?A/S precharge time
Access time from ?C?A/S precharge
?C?A/S to ?R?A/S precharge time
?C?A/S hold time
?C?A/S setup time (CBR REFRESH)
?C?A/S to ?W/E delay time
Write command to ?C?A/S lead time
Data-in hold time
Data-in hold time (referenced to ?R?A/S)
Data-in setup time
Output disable
Output Enable
O
? E
/ hold time from W
? E
/ during READ-MODIFY-WRITE cycle
?O/E HIGH hold from ?C?A/S HIGH
?O/E HIGH pulse width
?O/E LOW to ?C?A/S HIGH setup time
AS4LC4M4
Rev. 11/97
DS000022
SYM
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHR
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDHR
tDS
tOD
tOE
tOEH
tOEHC
tOEP
tOES
-6
MIN
MAX
30
15
45
0
0
55
15
10
12 10,000
10
0
5
10
35
5
50
5
35
15
10
40
0
0
15
15
10
10
10
5
2-78
-7
MIN
-8
MAX
35
15
55
0
0
65
MIN
20
60
0
0
65
20
15
15
15
0
5
10
10,000
20
15
20
15
0
5
10
40
5
55
5
40
15
12
56
0
0
12
10
10
5
MAX
40
10,000
40
5
60
10
45
20
15
55
0
15
20
20
20
15
10
10
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
20
14
5
15
5
20
21
21
22
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
SYM
tOFF
Output buffer turn-off delay
O
? E
/ setup prior to R
? A
? S
/ during HIDDEN REFRESH cycle tORD
tPC
EDO-PAGE-MODE READ or WRITE cycle time
t
EDO-PAGE-MODE READ-WRITE cycle time
PRWC
tRAC
Access time from ?R?A/S
tRAD
?R?A/S to column-address delay time
tRAH
Row-address hold time
tRAL
Column-address to ?R?A/S lead time
tRAS
?R?A/S pulse width
tRASP
?R?A/S pulse width (EDO PAGE MODE)
tRC
Random READ or WRITE cycle time
t
?R?A/S to ?C?A/S delay time
RCD
tRCH
Read command hold time (referenced to ?C?A/S)
tRCS
Read command setup time
tREF
Refresh period (2,048 cycles)
tRP
?R?A/S precharge time
tRPC
?R?A/S to ?C?A/S precharge time
tRRH
Read command hold time (referenced to ?R?A/S)
tRSH
?R?A/S hold time
t
READ WRITE cycle time
RWC
tRWD
?R?A/S to ?W/E delay time
tRWL
Write command to ?R?A/S lead time
tT
Transition time (rise or fall)
t
Write command hold time
WCH
tWCR
Write command hold time (referenced to ?R?A/S)
tWCS
?W/E command setup time
tWHZ
Output disable delay from ?W/E
tWP
Write command pulse width
tWPZ
?W/E pulse to disable at ?C?A/S HIGH
tWRH
?W/E hold time (CBR REFRESH)
tWRP
?W/E setup time (CBR REFRESH)
AS4LC4M4
Rev. 11/97
DS000022
-6
MIN
0
0
30
75
15
10
30
60
60
110
16
0
0
-7
MAX
15
60
30
10,000
100,000
45
MIN
0
0
35
85
15
10
35
70
70
130
16
0
0
32
40
5
0
13
150
80
15
2
10
40
0
0
10
10
10
10
2-79
30
14
-8
MAX
15
70
35
10,000
100,000
50
MIN
0
0
40
90
15
10
40
80
80
150
20
0
0
32
50
5
0
15
180
90
15
2
12
56
0
0
12
12
10
10
30
16
MAX
20
80
40
10,000
100,00
60
32
60
5
0
15
200
105
20
2
15
60
0
0
15
15
10
10
30
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
19
13
17
16
18
18
20
20
24
24
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
NOTES
18. Either tRCH or tRRH must be satisfied for a READ
cycle.
19. tOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL. It is referenced from the
rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
20. tWCS, tRWD, tAWD and tCWD are not restrictive
operating parameters. tWCS applies to EARLY
WRITE cycles. tRWD, tAWD and tCWD apply to
READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If tWCS < tWCS (MIN) and tRWD ≥
tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥
tCWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. ?O/E held HIGH
and ?W/E taken LOW after ?C?A/S goes LOW results in a
LATE WRITE (?O/E-controlled) cycle. tWCS, tRWD,
tCWD and tAWD are not applicable in a LATE
WRITE cycle.
21. These parameters are referenced to ?C?A/S leading edge
in EARLY WRITE cycles and ?W/E leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
22. If ?O/E is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, ?W/E
must be pulsed during ?C?A/S HIGH time in order to
place I/O buffers in High-Z.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, ?W/E = LOW and
?O/E = HIGH.
24. tWTS and tWTH are setup and hold specifications for
the /W/E pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of tWRP and tWRH in the
CBR REFRESH cycle.
1.
2.
3.
4.
All voltages referenced to VSS.
This parameter is sampled. VCC = +3.3V; f = 1 MHz.
ICC is dependent on cycle rates.
ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the ful
temperature range is assured.
7. An initail pause of 100µs is required after power-up
followed by eight /R/A/S refresh cycles (/R/A/S ONLY or
CBR with /W/E HIGH) before proper device operation
is assured. The eight /R/A/S cycle wake-ups should be
repeated any thime the tREF refresh requirement is
exceeded.
8. AC characteristics assume tT = 2.5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. Column address changed once each cycle.
12. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
13. Assumes that tRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
14. Assumes that tRCD≥ tRCD (MAX).
15. If ?C?A/S is LOW at the falling edge of ?R?A/S, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, ?C?A/S must be
pulsed HIGH for tCP.
16. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if tRCD is greater than the
specified tRCD (MAX) limit, then access time is
controlled exclusively by tCAC, provided tRAD is not
exceeded.
17. Operation within the tRAD (MAX) limit ensures that
tRAC (MIN) and tCAC (MIN) can be met. tRAD
(MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, then
access time is controlled exclusively by tAA, provided
tRCD is not exceeded.
AS4LC4M4
Rev. 11/97
DS000022
2-80
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
READ CYCLE
tRC
tRP
tRAS
V IH
V IL
RAS
tCSH
tRRH
tRSH
tRCD
tCRP
tCAS
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,, , ,
, ,
,,,,,,,,,,,,,
,,,,,,,,
,
,,,
V IH
V IL
CAS
tAR
tRAD
tASR
tRAL
tRAH
tASC
tCAH
tACH
V IH
V IL
ADDR
ROW
tWRP
V IH
V IL
WE
ROW
COLUMN
tWRH
tRCH
tRCS
NOTE 1
tAA
tRAC
NOTE 2
tOFF
tCAC
tCLZ
V OH
V OL
DQ
OPEN
OPEN
VALID DATA
t OE
t OD
V IH
V IL
OE
DON’T CARE
UNDEFINED
NOTE:
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
2. tOFF is referenced from rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
TIMING PARAMETERS
-6
SYM
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCLZ
tCRP
tCSH
tOD
tOE
tOFF
AS4LC4M4
Rev. 11/97
DS000022
MIN
-7
MAX
30
15
45
0
0
MIN
15
50
0
0
15
10
12
0
5
50
0
0
-8
MAX
35
10,000
15
15
15
MIN
20
60
0
0
20
15
15
0
5
55
0
0
-6
MAX
40
10,000
15
20
15
20
15
20
0
5
60
0
10,000
20
20
20
SYM
tRAC
tRAD
tRAH
tRAL
tRAS
tRC
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-81
MIN
15
10
30
60
110
16
0
0
40
0
10
10
10
-7
MAX
60
30
10,000
45
MIN
15
10
35
70
130
16
0
0
50
0
12
10
10
-8
MAX
70
35
10,000
50
MIN
15
10
40
80
150
20
0
0
60
0
15
10
10
MAX
80
40
10,000
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EARLY WRITE CYCLE
tRC
tRAS
RAS
tRP
V IH
V IL
tCSH
tRSH
,,, ,,,, ,,,,,,
,
,
,
,
,
,,,,,,, ,,,,,,,,
,,,,,,,,,, ,,,,,,,,,
,,,, , , ,, , , ,
,
,,
tCRP
CAS
tRCD
tCAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAL
tRAH
tASC
ROW
tCAH
tACH
ROW
COLUMN
tCWL
tRWL
tWCR
tWCS
tWRP
WE
V IH
V IL
tWCH
tWP
tWRH
NOTE 1
tDHR
tDS
V
DQ V IOH
IOL
tDH
VALID DATA
V IH
V IL
OE
DON’T CARE
UNDEFINED
NOTE:
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
tCRP
tCSH
tCWL
tDH
tDHR
tDS
tRAD
tRAH
AS4LC4M4
Rev. 11/97
DS000022
MIN
15
45
0
0
10
12
5
50
15
10
40
0
15
10
-7
MAX
10,000
30
MIN
15
55
0
0
15
15
5
55
15
12
50
0
15
10
-8
MAX
10,000
35
MIN
20
60
0
0
15
20
5
60
20
15
55
0
15
10
-6
SYM
tRAL
tRAS
tRC
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
MAX
UNITS
ns
ns
ns
ns
ns
10,000 ns
ns
ns
ns
ns
ns
ns
40
ns
ns
2-82
MIN
30
60
110
16
40
13
15
10
40
0
10
10
10
MAX
10,000
45
-7
MIN MAX
35
70 10,000
130
16
50
50
15
15
12
50
0
12
10
10
-8
MIN
40
80
150
20
60
0
20
15
60
0
15
10
10
MAX
10,000
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
RAS
tRP
V IH
V IL
tCSH
tRSH
,
,
,
,
,
,
,
,
,
,,, , , ,, , ,, ,
,, ,,
,,,,,,
,
,
,
,
,
,
,
,
,
,
,,,, ,, ,, ,,,,,,
,
tCRP
CAS
tRCD
tCAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAL
tASC
tRAH
ROW
tCAH
tRCS
tWRP
WE
V IH
V IL
tACH
COLUMN
tWRH
NOTE 1
ROW
tRWD
tCWL
tCWD
tRWL
tAWD
tWP
tAA
tRAC
tCAC
tDS
t CLZ
V
DQ V IOH
IOL
VALID D OUT
OPEN
tOE
OE
NOTE:
tDH
VALID D IN
tOD
OPEN
tOEH
V IH
V IL
,
DON’T CARE
UNDEFINED
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
SYM
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCLZ
tCRP
tCSH
tCWD
tCWL
tDH
tDS
tOD
AS4LC4M4
Rev. 11/97
DS000022
MIN
-7
MAX
30
15
45
0
0
55
MIN
15
55
0
0
65
15
10
12
0
5
50
35
15
10
0
0
10,000
15
MIN
MAX
40
20
60
0
0
65
20
15
15
0
5
55
40
15
12
0
0
-6
-8
MAX
35
10,000
15
20
15
20
0
5
60
45
20
15
0
0
10,000
20
SYM
MIN
tOE
tOEH
10
tRAC
tRAD
15
tRAH
10
tRAL
30
tRAS
60
tRCD
16
tRCS
0
tRP
40
tRSH
13
tRWC 150
tRWD
80
tRWL
15
tWP
10
tWRH
10
tWRP
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-83
-7
MAX
15
MIN
-8
MAX
20
12
60
30
10,000
45
MIN
MAX
20
15
70
35
15
10
35
70 10,000
16
50
0
50
15
180
90
15
12
10
10
15
10
40
80
20
0
60
15
200
105
20
15
10
10
80
40
10,000
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO-PAGE-MODE READ CYCLE
tRASP
RAS
tRP
V IH
V IL
tCSH
CAS
tRSH
tCAS
tPC
,,, ,,,, ,,, ,,,
,,,,,,
,
,
,
,,,,, ,,, ,
, ,
tCRP
tRCD
tCAS
tCP
tCP
tCAS
V IH
V IL
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tWRP
WE
tACH
V IH
V IL
tACH
tCAH
tASC
COLUMN
tWRH
NOTE:
tASC
NOTE 1
tAA
tAA
tRAC
tCPA
tCAC
tCAC
V OH
V OL
VALID
DATA
OPEN
tRRH
tAA
tCPA
tCAC
tCLZ
VALID
DATA
tOD
tOES
V IH
V IL
ROW
tRCH
tOEHC
tCOH
tCAH
COLUMN
tRCS
tOE
OE
tACH
COLUMN
tCLZ
DQ
tCAH
,
,
,
,, ,,
,, ,
,,,,, ,
,, ,
tRAL
tAR
tRAD
tCP
tOEP
tOFF
VALID
DATA
OPEN
tOE
tOD
tOES
DON’T CARE
UNDEFINED
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
SYM
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tOD
tOE
tOEHC
AS4LC4M4
Rev. 11/97
DS000022
MIN
-7
MAX
30
15
45
0
0
MIN
15
55
0
0
15
10
12
0
5
10
10,000
35
5
50
0
10
15
15
MIN
10,000
20
15
20
0
5
10
40
5
55
0
10
MAX
40
20
60
0
0
20
15
15
0
5
10
-6
-8
MAX
35
15
20
10,000
40
5
60
0
10
20
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tOEP
tOES
tOFF
tPC
tRAC
tRAD
tRAH
tRAL
tRASP
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
2-84
MIN
10
5
0
30
15
10
30
60
16
0
0
40
0
13
10
10
-7
MAX
15
60
30
100,000
45
MIN
10
5
0
35
15
10
35
70
16
0
0
50
0
15
10
10
MAX
15
70
35
100,000
50
-8
MIN
10
5
0
40
15
10
40
80
20
0
0
60
0
15
10
10
MAX
UNITS
ns
ns
20
ns
ns
80
ns
40
ns
ns
ns
100,000
ns
60
ns
ns
ns
ns
ns
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRP
tRASP
RAS
V IH
V IL
tCSH
tPC
tRSH
,
,
,
,
,
,
,, ,, , , ,, , ,
,
,
,
,
,
,
,
,
,,,,,, ,,, ,, ,,,,
,
,
,
,
,
,
,
,
,
,
,
,
,,,, ,, ,, , ,, ,, ,
tCRP
CAS
tRCD
tCAS
tCP
tCAS
tCP
V IH
V IL
tAR
tACH
tRAD
tASR
ADDR
V IH
V IL
tACH
tRAH
tASC
ROW
tACH
tCAH
tASC
COLUMN
tCAH
tWCS
tWRP
V IH
V IL
tWCH
tWRH
tASC
COLUMN
tCWL
WE
tCP
tCAS
COLUMN
tCWL
tWCS
tWP
tRAL
tCAH
tWCH
ROW
tCWL
tWCS
tWP
tWCH
tWP
NOTE 1
tRWL
tWCR
tDHR
tDS
V
DQ V IOH
IOL
OE
tDH
tDS
VALID DATA
tDH
VALID DATA
tDS
tDH
VALID DATA
V IH
V IL
,
DON’T CARE
UNDEFINED
NOTE:
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
tCP
tCRP
tCSH
tCWL
tDH
tDHR
tDS
tPC
AS4LC4M4
Rev. 11/97
DS000022
MIN
15
45
0
0
10
12
10
5
50
15
10
40
0
30
-7
MAX
10,000
MIN
15
55
0
0
12
15
10
5
55
15
12
50
0
35
-8
MAX
10,000
MIN
20
60
0
0
15
20
10
5
60
20
15
55
0
40
MAX
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tRAD
tRAH
tRAL
tRASP
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
2-85
-6
MIN
MAX
15
30
10
30
60 100,000
16
45
40
13
15
10
40
0
10
10
10
-7
-8
MIN
MAX
MIN
MAX
15
35
15
40
10
10
35
40
70 100,000 80
100,00
16
50
20
60
50
60
15
15
15
20
12
15
50
60
0
0
12
15
10
10
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP
RAS
tRP
V IH
V IL
tCSH
tPRWC NOTE 1
t PC
tRSH
,
,
, , ,,, ,,,,,,,,,
,
,
,,,,
,, ,
,,
,,
,
,
,,,,,,,,,, ,, , ,,,,,
,,,
tCRP
CAS
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tAR
tRAD
tASR
ADDR
tCP
V IH
V IL
V IH
V IL
tRAL
tRAH
tASC
ROW
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRWD
tRCS
tWRP
WE
V IH
V IL
tWRH
NOTE 2
tRWL
tCWL
tWP
tAWD
tCWL
tWP
tAWD
tAWD
tCWD
tCWD
tCWD
tAA
tAA
tRAC
tDH
tDS
V IOH
V IOL
tCLZ
VALID
D OUT
OPEN
tCLZ
VALID
D IN
tOE
tDH
tDS
tCAC
VALID
D OUT
tOD
OE
tCPA
tCAC
tCLZ
DQ
tAA
tDH
tDS
tCPA
tCAC
tCWL
tWP
VALID
D IN
VALID
D OUT
VALID
D IN
tOD
OPEN
tOD
tOE
tOE
tOEH
V IH
V IL
DON’T CARE
UNDEFINED
NOTE:
tPC
1.
is for LATE WRITE cycles only.
2. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
SYM
tAA
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCLZ
tCP
tCPA
tCRP
tCSH
tCWD
tCWL
tDH
tDS
tOD
AS4LC4M4
Rev. 11/97
DS000022
MIN
-7
MAX
30
45
0
0
55
MIN
55
0
0
65
15
10
12
0
10
10,000
35
5
50
35
15
10
0
0
15
MIN
10,000
20
15
20
0
10
40
5
55
40
15
12
0
0
MAX
40
60
0
0
65
20
15
15
0
10
-6
-8
MAX
35
15
10,000
40
5
60
45
20
15
0
0
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tOE
tOEH
tPC
tPRWC
tRAC
tRAD
tRAH
tRAL
tRASP
tRCD
tRCS
tRP
tRSH
tRWD
tRWL
tWP
tWRH
tWRP
2-86
MIN
-7
MAX
15
10
30
75
15
10
30
60
16
0
40
13
80
15
10
10
10
MIN
-8
MAX
20
12
35
85
60
30
100,000
45
70
15
35
10
35
70 100,000
16
50
0
50
15
90
15
12
10
10
MIN
MAX
20
UNITS
ns
15
ns
40
ns
90
ns
80
ns
15
40
ns
10
ns
40
ns
80 100,000
ns
20
60
ns
0
ns
60
ns
15
ns
105
ns
20
ns
15
ns
10
ns
10
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t RP
t RASP
RAS
V IH
V IL
t CSH
t PC
t CRP
t RCD
t RSH
t PC
t CP
t CAS
t CP
t CAS
,
,
,
,
,
,
,, ,,, ,, , ,
, ,, ,
,
,
,
,
,
,
,
, , ,
CAS
,
,,,
V IH
V IL
t RAL
t AR
t RAD
tASR
ADDR
V IH
V IL
t ASC
V IH
V IL
t CAH
t ASC
COLUMN (A)
ROW
tWRP
WE
t RAH
tWRH
t CAH
COLUMN (N)
t WCS
t CPA
t CAC
t CAC
t COH
OPEN
VALID DATA (A)
t DS
t DH
t WHZ
VALID
DATA (B)
VALID DATA
IN
t OE
OE
NOTE:
ROW
t WCH
t AA
t AA
t RAC
DQ V IOH
V IOL
t ASC
COLUMN (B)
t RCH
NOTE 1
t ACH
t CAH
t RCS
t CP
t CAS
V IH
V IL
,,,
,,
DON’T CARE
UNDEFINED
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
SYM
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCOH
tCP
tCPA
tCRP
tCSH
tDH
tDS
tOE
AS4LC4M4
Rev. 11/97
DS000022
MIN
-7
MAX
30
15
45
0
0
MIN
15
55
0
0
15
10
12
5
10
-8
MAX
35
10,000
10,000
20
15
20
5
10
40
5
55
12
0
15
MAX
40
20
60
0
0
20
15
15
5
10
35
5
50
10
0
MIN
10,000
40
5
60
15
0
20
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tPC
tRAC
tRAD
tRAH
tRAL
tRASP
tRCD
tRCH
tRCS
tRP
tRSH
tWCH
tWCS
tWHZ
tWRH
tWRP
2-87
MIN
30
15
10
30
60
16
0
0
40
13
10
0
0
10
10
-6
MAX
60
30
100,000
45
13
MIN
35
15
10
35
70
16
0
0
50
15
12
0
0
10
10
-7
MAX
70
35
100,000
50
15
MIN
40
15
10
40
80
20
0
0
60
15
15
0
0
10
10
-8
MAX
UNITS
ns
80
ns
40
ns
ns
ns
100,000
ns
60
ns
ns
ns
ns
ns
ns
ns
15
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
READ CYCLE
(with ?W/E-controlled disable)
V IH
V IL
RAS
tCSH
,
,
,
,
,
,
,
,
,
,
,
,,,, ,, ,
,,,,,,,,,,,,,
,,,,,,,,
,
,
,
,
tRCD
tCRP
tCAS
tCP
V IH
V IL
CAS
tAR
tRAD
tASR
V IH
V IL
ADDR
tRAH
ROW
tWRP
V IH
V IL
WE
tASC
tCAH
tASC
COLUMN
tWRH
COLUMN
tRCS
NOTE 1
tRCH
tWPZ
tRCS
tAA
tRAC
tCAC
tWHZ
tCLZ
V OH
V OL
DQ
OPEN
tCLZ
OPEN
VALID DATA
t OE
t OD
V IH
V IL
OE
DON’T CARE
UNDEFINED
NOTE:
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
SYM
tAA
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCLZ
tCP
tCRP
tCSH
tOD
AS4LC4M4
Rev. 11/97
DS000022
MIN
-7
MAX
30
45
0
0
MIN
55
0
0
15
10
12
0
10
5
50
0
10,000
15
MIN
MAX
40
60
0
0
20
15
15
0
10
5
55
0
-6
-8
MAX
35
10,000
15
20
15
20
0
10
5
60
0
10,000
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tOE
tRAC
tRAD
tRAH
tRCD
tRCH
tRCS
tWHZ
tWPZ
tWRH
tWRP
2-88
MIN
15
10
16
0
0
0
10
10
10
-7
MAX
15
60
30
45
14
MIN
15
10
16
0
0
0
12
10
10
-8
MAX
20
70
35
50
16
MIN
15
10
20
0
0
0
15
10
10
MAX
20
80
40
60
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
?R?A/S-ONLY REFRESH CYCLE
tRC
tRAS
V IH
V IL
,,,
,
,
,,
RAS
V IH
V IL
tASR
ADDR
WE
tRAH
V IH
V IL
V
DQ V OH
OL
,,,,,,,,,,
,
,
,
,
,
,
,,,, ,, , ,,,
tRPC
tCRP
CAS
ROW
ROW
OPEN
tWRP
V IH
V IL
tWRP
tWRH
tWRH
NOTE 1
CBR REFRESH CYCLE
(Addresses and ?O/E = DON’T CARE)
tRP
RAS
tRP
tRAS
tRP
tRAS
V IH
V IL
tRPC
,,,,,,,,,,,,,,,,,,,,
,
,,,
tCP
CAS
V IH
V IL
DQ
V OH
V OL
tCSR
tCSR
tCHR
OPEN
tWRP
WE
tRPC
tCHR
tWRH
tWRP
tWRH
V IH
V IL
,
DON’T CARE
UNDEFINED
NOTE:
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
SYM
tASR
tCHR
tCP
tCRP
tCSR
tRAH
AS4LC4M4
Rev. 11/97
DS000022
MIN
0
10
10
5
5
10
-7
MAX
MIN
0
15
10
5
5
10
-6
-8
MAX
MIN
0
15
10
5
10
10
MAX
UNITS
ns
ns
ns
ns
ns
ns
SYM
tRAS
tRC
tRP
tRPC
tWRH
tWRP
2-89
MIN
60
110
40
5
10
10
MAX
10,000
-7
MIN
70
130
50
5
10
10
MAX
10,000
-8
MIN
80
150
60
5
10
10
MAX
10,000
UNITS
ns
ns
ns
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
HIDDEN REFRESH CYCLE 24
(?W/E = HIGH; ?O/E = LOW)
tRAS
tRP
tRAS
V IH
V IL
,
,
,
,
,
,
,,
,
,
,
,
,
, ,, , , , , ,
,
,
,
,
,
,
,
,
,
,
,
,
,
, , ,,
,,, ,
RAS
tCRP
tRSH
tRCD
tCHR
CAS
V IH
V IL
tAR
tRAD
tASR
V IH
V IL
ADDR
tRAH
tASC
ROW
tRAL
tCAH
COLUMN
tAA
tRAC
tOFF
tCAC
tCLZ
V
DQ V OH
OL
OPEN
VALID DATA
OPEN
tOD
tOE
tORD
V
OE V IH
IL
,
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
SYM
tAA
tAR
tASC
tASR
tCAC
tCAH
tCHR
tCLZ
tCRP
tOD
tOE
AS4LC4M4
Rev. 11/97
DS000022
MIN
-7
MAX
30
45
0
0
MIN
55
0
0
15
10
10
0
5
0
-8
MAX
35
15
15
MIN
60
0
0
20
15
15
0
5
0
-6
MAX
40
15
20
20
15
15
0
5
0
20
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tOFF
tORD
tRAC
tRAD
tRAH
tRAL
tRAS
tRCD
tRP
tRSH
2-90
MIN
0
0
15
10
30
60
16
40
13
-7
MAX
15
60
30
10,000
45
MIN
0
0
15
10
35
70
16
50
15
-8
MAX
15
70
35
10,000
50
MIN
0
0
15
10
40
80
20
60
15
MAX
20
UNITS
ns
ns
80
ns
40
ns
ns
ns
10,000 ns
60
ns
ns
ns
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS
(per Method 5005, Table I)
MIL-STD-883 TEST REQUIREMENTS
INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS
(Method 5004)
2, 8A, 10
FINAL ELECTRICAL TEST PARAMETERS
(Method 5004)
1*, 2, 3, 7*, 8, 9, 10, 11
GROUP A TEST REQUIREMENTS
(Method 5005)
1, 2, 3, 4**, 7, 8, 9, 10, 11
GROUP C AND D END-POINT ELECTRICAL PARAMETERS
(Method 5005)
1, 2, 3, 7, 8, 9, 10, 11
* PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input
or output capacitance.
AS4LC4M4
Rev. 11/97
DS000022
2-91
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4
Rev. 11/97
DS000022
2-92
AS4LC4M4 883C
4 MEG x 4 DRAM
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.