8 MEG x 8 EDO DRAM DRAM MT4LC8M8P4, MT4LC8M8C2 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT (Top View) • Single +3.3V ±0.3V power supply • Industry-standard x8 pinout, timing, functions, and packages • 12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTLcompatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention OPTIONS 32-Pin SOJ VCC DQ0 DQ1 DQ2 DQ3 NC VCC WE# RAS# A0 A1 A2 A3 A4 A5 VCC MARKING • Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows C2 P4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-Pin TSOP VCC VSS DQ0 DQ7 DQ1 DQ6 DQ2 DQ5 DQ3 DQ4 NC Vss VCC CAS# WE# RAS# OE# NC/A12** A0 A1 A11 A2 A10 A3 A9 A4 A8 A5 A7 VCC A6 VSS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS DQ7 DQ6 DQ5 DQ4 VSS CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 VSS **NC on C2 version and A12 on P4 version • Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) DJ TG • Timing 50ns access 60ns access -5 -6 • Refresh Rates Standard Refresh (64ms period) Self Refresh (128ms period) 8 MEG x 8 EDO DRAM PART NUMBERS PART NUMBER MT4LC8M8C2DJ-x MT4LC8M8C2DJ-x S MT4LC8M8C2TG-x MT4LC8M8C2TG-x S MT4LC8M8P4DJ-x MT4LC8M8P4DJ-x S MT4LC8M8P4TG-x MT4LC8M8P4TG-x S None S* REFRESH ADDRESSING 4K 4K 4K 4K 8K 8K 8K 8K NOTE: 1. The 8 Meg x 8 EDO DRAM base number differentiates the offerings in one place— MT4LC8M8C2. The fifth field distinguishes the address offerings: C2 designates 4K addresses and P4 designates 8K addresses. 2. The “#” symbol indicates signal is active LOW. x = speed *Contact factory for availability GENERAL DESCRIPTION MT4LC8M8C2DJ-5 KEY TIMING PARAMETERS tRC tRAC tPC tAA tCAC tCAS 84ns 104ns 50ns 60ns 20ns 25ns 25ns 30ns 13ns 15ns 8ns 10ns 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP Standard Self Standard Self Standard Self Standard Self The 8 Meg x 8 DRAM is a high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits and designed to operate from 3V to 3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are functionally organized as 8,388,608 locations containing eight bits each. The 8,388,608 memory locations are arranged in 4,096 rows by 2,048 columns on the C2 version and 8,192 rows by 1,024 columns on the P4 version. During READ or WRITE cycles, each location is Part Number Example: SPEED -5 -6 PACKAGE REFRESH 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM FUNCTIONAL BLOCK DIAGRAM MT4LC8M8P4 (13 row addresses) WE# CAS# 8 DATA-IN BUFFER DQ0DQ7 CONTROL LOGIC DATA-OUT BUFFER NO. 2 CLOCK GENERATOR 8 8 OE# 10 COLUMNADDRESS BUFFER(10) COLUMN DECODER 10 8 1,024 REFRESH CONTROLLER A0A12 SENSE AMPLIFIERS I/O GATING 1,024 x 8 13 8,192 8,192 x 8 ROW SELECT 13 ROW DECODER 13 ROWADDRESS BUFFERS (13) COMPLEMENT SELECT REFRESH COUNTER 8,192 x 1,024 x 8 MEMORY ARRAY NO. 1 CLOCK GENERATOR RAS# VDD VSS FUNCTIONAL BLOCK DIAGRAM MT4LC8M8C2 (12 row addresses) WE# CAS# 8 DATA-IN BUFFER DQ0DQ7 CONTROL LOGIC DATA-OUT BUFFER NO. 2 CLOCK GENERATOR 8 8 OE# 11 COLUMNADDRESS BUFFER(11) COLUMN DECODER 11 2,048 REFRESH CONTROLLER A0A11 SENSE AMPLIFIERS I/O GATING 2,048 x 8 4,096 NO. 1 CLOCK GENERATOR 4,096 x 8 ROW SELECT 12 ROW DECODER 12 ROWADDRESS BUFFERS (12) COMPLEMENT SELECT REFRESH COUNTER 12 RAS# 8 4,096 x 2,048 x 8 MEMORY ARRAY VDD VSS 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM GENERAL DESCRIPTION (continued) EDO PAGE MODE uniquely addressed via the address bits. First, the row address is latched by the RAS# signal, then the column address is latched by CAS#. Both devices provide EDOPAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFYWRITE) within a given row. The 8 Meg x 8 DRAM must be refreshed periodically in order to retain stored data. DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. If CAS# went HIGH and OE# was LOW (active), the output buffers would be disabled. The 8 Meg x 8 DRAM offers an accelerated page mode cycle by eliminating output disable from CAS# HIGH. This option is called EDO, and it allows CAS# precharge time (tCP) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms in the noted appendix). EDO operates like any DRAM READ or FAST-PAGEMODE READ, except data is held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH. OE# can be brought LOW or HIGH while CAS# and RAS# are LOW, and the DQs will transition between valid data and High-Z. Using OE#, there are two methods to disable the outputs and keep them disabled during the CAS# HIGH time. The first method is to have OE# HIGH when CAS# transitions HIGH and keep OE# HIGH for tOEHC thereafter. This will disable the DQs, and they will remain disabled (regardless of the state of OE# after that point) until CAS# falls again. The second method is to have OE# LOW when CAS# transitions HIGH and then bring OE# HIGH for a minimum of tOEP anytime during the CAS# HIGH period. This will disable the DQs, and they will remain disabled (regardless of the state of OE# after that point) until CAS# falls again (see Figure 1). During DRAM ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description. The data for each location is accessed via the eight I/O pins (DQ0DQ7). A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping OE# LOW, no write will occur, and the data outputs will drive read data from the accessed location. RAS# V IH V IL CAS# V IH V IL ADDR V IH V IL DQ V IOH V IOL ROW COLUMN (A) OPEN COLUMN (B) VALID DATA (A) VALID DATA (A) VALID DATA (B) tOD tOD tOES OE# V IH V IL COLUMN (C) COLUMN (D) VALID DATA (C) VALID DATA (D) tOD tOEHC tOE tOEP The DQs go back to Low-Z if tOES is met. The DQs remain High-Z until the next CAS# cycle if tOEHC is met. The DQs remain High-Z until the next CAS# cycle if tOEP is met. DON’T CARE UNDEFINED Figure 1 OE# CONTROL of DQs 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM EDO PAGE MODE (continued) other cycles, the outputs are disabled at tOFF time after RAS# and CAS# are HIGH or at tWHZ after WE# transitions LOW. The tOFF time is referenced from the rising edge of RAS# or CAS#, whichever occurs last. WE# can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 2. EDO-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the EDO-PAGE-MODE operation. covers all rows. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method, some compatibility issues may become apparent. For example, both C2 and P4 versions require 4,096 CBR REFRESH cycles, yet each requires a different number of RAS#-ONLY REFRESH cycles (C2 = 4,096 and P4 = 8,192). JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The “S” option allows for an extended period of 128ms, or 31.25µs per row for a 4K refresh and 15.625µs per row for an 8K refresh, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst CBR refresh sequence, all 1,024 rows must be refreshed using a minimum tRC refresh rate prior to resuming normal operation. DRAM REFRESH The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all 8,192 rows (P4) or all 4,096 rows (C2) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC8M8P4 internally refreshes two rows for every CBR cycle, whereas the MT4LC8M8C2 refreshes one row for every CBR cycle. So with either device, executing 4,096 CBR cycles RAS# V IH V IL CAS# V IH V IL ADDR V IH V IL DQ V IOH V IOL ROW COLUMN (A) OPEN COLUMN (B) VALID DATA (A) VALID DATA (B) V IH V IL OE# V IH V IL COLUMN (D) INPUT DATA (C) tWHZ tWHZ WE# COLUMN (C) tWPZ The DQs go to High-Z if WE# falls and, if tWPZ is met, will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated). WE# may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated). DON’T CARE UNDEFINED Figure 2 WE# CONTROL of DQs 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VCC Relative to VSS ................ -1V to +4.6V Voltage on NC, Inputs or I/O Pins Relative to VSS ....................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0°C to +70°C Storage Temperature (plastic) ............ -55°C to +150°C Power Dissipation ................................................... 1W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Note: 1) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VCC 3 3.6 V INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC VIH 2 VCC + 0.3 V 26 INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 26 II -2 2 µA 27 OUTPUT HIGH VOLTAGE: IOUT = -2mA VOH 2.4 – V OUTPUT LOW VOLTAGE: IOUT = 2mA VOL – 0.4 V IOZ -5 5 µA INPUT LEAKAGE CURRENT: Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); All other pins not under test = 0V OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V); DQ is disabled and in High-Z state 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 5 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V) 4K 8K REFRESH REFRESH UNITS NOTES PARAMETER/CONDITION SYMBOL SPEED STANDBY CURRENT: TTL (RAS# = CAS# = VIH) ICC1 ALL 1 1 mA ICC2 ALL 500 500 µA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC3 -5 -6 175 165 135 125 mA 25 OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC4 -5 -6 155 125 155 125 mA 25 REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) ICC5 -5 -6 175 165 135 125 mA 22 REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC6 -5 -6 165 155 165 155 mA 4, 7 ICC7 ALL 400 400 µA 4, 7 ICC8 ALL 350 400 µA 4, 7 STANDBY CURRENT: CMOS (RAS# = CAS# VCC - 0.2V; DQs may be left open; other inputs: VIN VCC - 0.2V or VIN ≤ 0.2V) REFRESH CURRENT: Extended (“S” version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM CAPACITANCE (Note: 2) PARAMETER SYMBOL MAX UNITS Input Capacitance: Address pins CI 1 5 pF Input Capacitance: RAS#, CAS#, WE#, OE# CI 2 7 pF Input/Output Capacitance: DQ CIO 7 pF NOTES AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time Write command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 -5 -6 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH MIN 8 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tOEHC 5 5 4 0 10 5 5 0 ns ns ns ns tOEP tOES tOFF 7 MAX 25 12 38 0 0 42 MIN 15 45 0 0 49 13 8 8 15 8 0 3 8 10,000 15 10 10 15 10 0 3 10 28 5 38 5 28 8 8 0 0 MAX 30 12 12 12 10,000 35 5 45 5 35 10 10 0 0 15 15 15 18 4 13 4 18 19 19 23, 24 20 24 17, 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period Refresh period (2,048 cycles) “S” version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WE# to outputs in High-Z WRITE command pulse width WE# pulse widths to disable outputs WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 -5 SYMBOL tORD tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP 8 MIN 0 20 47 -6 MAX MIN 0 25 56 50 9 9 50 50 100 84 11 0 0 10,000 125,000 60 12 10 60 60 100 104 14 0 0 64 128 30 5 90 0 13 116 67 13 2 8 38 0 50 10,000 125,000 64 128 40 5 105 0 15 140 79 15 2 10 45 0 12 5 10 8 8 MAX 50 15 5 10 10 10 UNITS ns ns ns ns ns ns ns ns µs ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 15 14 16 23 16 18 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM NOTES 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 18.tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS MIN, the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD and tCWD define READMODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. OE# held HIGH and WE# taken LOW after CAS# goes LOW results in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 22. RAS#-ONLY REFRESH requires that all rows be refreshed at least once every 64ms (4,096 rows for the C2 version and 8,192 rows for the P4 version). CBR REFRESH requires that at least 4,096 cycles be completed every 64ms. 23. The DQs open during READ cycles once tOD or tOFF occur. If CAS# stays LOW while OE# is brought HIGH, the DQs will open. If OE# is brought back LOW (CAS# still LOW), the DQs will provide the previously read data. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while CAS# remains LOW, the DQs will remain open. 25. Column address changed once each cycle. 26. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. 27. NC pins are assumed to be left floating and are not tested for leakage. 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC = +3.3V; f = 1 MHz; TA = 25°C. 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 2.5ns. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. If CAS# and RAS# = VIH, data output is High-Z. 11. If CAS# = VIL, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates and 100pF; and VOL = 0.8V and VOH = 2V. 13. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP. 14. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. 15. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. 16. Either tRCH or tRRH must be satisfied for a READ cycle. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM READ CYCLE tRC tRP tRAS RAS# V IH V IL tCSH tRSH tRCD tCRP CAS# tRRH tCAS V IH V IL tAR tRAD tRAH tASR tASC tCAH tACH ADDR V IH V IL ROW ROW COLUMN tRCH tRCS WE# V IH V IL tAA tRAC NOTE 1 tOFF tCAC tCLZ DQ V OH V OL OPEN OE# OPEN VALID DATA tOE tOD V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA -6 MAX MIN UNITS SYMBOL 30 tOFF tACH 12 15 ns ns tAR 38 0 0 45 0 0 ns ns ns tRAD ns ns tRC ns ns ns tRCH tRRH 15 ns ns 15 ns tASC tASR 25 -5 MAX tCAC 13 tCAH 8 tCAS 8 0 5 tCLZ tCRP tCSH tOD tOE 38 0 15 10 10,000 12 12 10 0 5 45 0 10,000 MAX MIN MAX UNITS 0 12 50 0 15 60 ns ns 10,000 ns ns ns tRAC tRAH tRAS tRCD tRCS tRP tRSH -6 MIN 9 9 50 10,000 12 10 60 84 11 104 14 ns ns 0 0 30 0 0 40 ns ns ns 0 13 0 15 ns ns NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM EARLY WRITE CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tCRP CAS# tCAS tAR tASC tCAH V IH V IL tRAD tASR ADDR tRCD V IH V IL tACH tRAH ROW ROW COLUMN tCWL tRWL tWCR tWCH tWCS tWP WE# V IH V IL tDS V DQ V IOH IOL OE# tDH VALID DATA V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCRP tCSH MIN 12 38 -6 MAX MIN 15 45 -5 MAX UNITS ns ns SYMBOL tRAH tRAS 0 0 0 0 ns ns tRC 8 8 5 10 10 5 ns ns ns tRP 10,000 10,000 tRCD tRSH tRWL 38 8 45 15 ns ns tWCH 10 0 ns ns tWCS tDS 8 0 tRAD 9 12 ns tCWL tDH 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 tWCR tWP 11 -6 MIN 9 MAX MIN 10 MAX UNITS ns 50 84 11 10,000 60 104 14 10,000 ns ns ns 30 13 40 15 ns ns 13 8 38 15 10 45 ns ns ns 0 5 0 5 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS RAS# V IH V IL tCRP CAS# tCSH tRSH tCAS tRCD V IH V IL tAR tRAD tRAH tASR ADDR tRP V IH V IL tASC tCAH tACH ROW COLUMN tRCS WE# ROW tRWD tCWD tCWL tRWL tAWD tWP V IH V IL tAA tRAC tCAC tDS tCLZ V DQ V IOH IOL VALID D OUT OPEN VALID D IN tOD tOE OE# tDH OPEN tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tAWD MIN 0 0 42 0 0 49 ns ns ns tRAC ns ns tRAS ns ns ns tRCS 13 8 0 5 tCWL tDH tDS 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 SYMBOL tOD tOE tCAS tCWD UNITS ns ns ns 8 tCSH -5 MAX 30 15 45 tCAH tCRP MIN 12 38 tCAC tCLZ -6 MAX 25 15 10 10,000 10 0 5 10,000 tRAD tRAH tRCD tRP tRSH 38 28 45 35 ns ns tRWC 8 8 0 10 10 0 ns ns ns tRWL tRWD 12 -6 MAX 12 MIN 0 12 tOEH tWP MIN 0 8 UNITS ns 15 ns ns 60 ns ns ns 10,000 ns ns 10 50 9 9 50 11 MAX 15 12 10 10,000 60 14 0 30 13 0 40 15 ns ns ns 116 67 140 79 ns ns 13 5 15 5 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM EDO-PAGE-MODE READ CYCLE tRASP tRP V IH V IL RAS# tCSH tCRP tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL CAS# tAR tRAD tRAH tASR V IH V IL ADDR tACH tASC ROW tACH tACH tASC tCAH COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRCS tRCH V IH V IL WE# tAA tRAC tAA tCPA tCAC tCAC DQ V OH V OL VALID DATA OPEN tOFF tOEHC VALID DATA tOE OE# tCAC tCLZ tCOH tCLZ VALID DATA OPEN tOE tOD tOES V IH V IL tRRH tAA tCPA tOD tOES tOEP DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tACH -6 MAX MIN 25 tASC 12 38 0 15 45 0 tASR 0 0 tAR tCAC tCAH tCAS tCLZ tCOH tCP 13 8 8 0 3 8 tCPA tCRP tCSH tOD 0 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 UNITS 30 ns ns ns ns tOEHC ns ns tPC ns ns ns tRAD ns ns tRCD ns ns ns tRCS ns ns tRSH 15 10 10 0 10,000 3 10 28 5 38 tOE 10,000 -5 MAX 35 5 45 12 12 0 15 15 SYMBOL tOEP MIN 5 5 tOES 4 tOFF 0 20 tRAC tRAH tRASP tRCH tRP tRRH 13 -6 MAX MIN 0 25 50 ns 15 60 12 10 125,000 60 14 0 UNITS ns ns 5 12 9 9 50 11 0 MAX 10 5 ns ns ns ns ns 125,000 ns ns ns 0 30 0 40 ns ns 0 13 0 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM EDO-PAGE-MODE EARLY WRITE CYCLE t RP t RASP RAS# V IH V IL t CSH t PC t CRP CAS# t RCD t CAS t RSH t CP t CAS t CP t CP t CAS V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH tACH t ASC ROW t ACH t CAH t ASC COLUMN t WCH t WCS t CAH COLUMN t CWL ROW t CWL t WCH t WP WE# t ASC COLUMN t CWL t WCS t ACH t CAH t WCS t WP t WCH t WP V IH V IL t WCR t DS V DQ V IOH IOL t DH t DS VALID DATA t DH t DS VALID DATA t RWL t DH VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCP MIN 12 -6 MAX MIN 15 -5 MAX UNITS ns SYMBOL tPC 38 0 45 0 ns ns tRAD 0 8 8 0 10 10 ns ns ns tRASP 10,000 10,000 tRAH tRCD tRP 8 5 10 5 ns ns tRSH 45 10 10 ns ns ns tWCH tDH 38 8 8 tDS 0 0 ns tWP tCRP tCSH tCWL 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 tRWL tWCR tWCS 14 MIN 20 -6 MAX 9 9 50 11 30 MIN 25 MAX 12 10 125,000 60 14 40 UNITS ns ns ns 125,000 ns ns ns 13 13 15 15 ns ns 8 38 0 10 45 0 ns ns ns 5 5 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RASP t RP V IH V IL RAS# t CSH t CRP t CAS t RSH t PRWC NOTE 1 t PC tRCD t CP t CAS t CP t CAS t CP V IH V IL CAS# t AR t RAD t ASR t RAH V IH V IL ADDR t ASC ROW t CAH t ASC COLUMN t CAH t ASC COLUMN t CAH COLUMN ROW t RWD t RCS t RWL t CWL t CWL t WP t AWD t WP t AWD t AWD t CWD t CWD t CWD V IH V IL WE# t AA t AA t RAC t DH V IOH V IOL t CAC t CAC t CLZ t CLZ VALID D OUT OPEN tAA t DH t CPA t DS DQ t CWL t WP t DS t CAC t CLZ VALID DIN VALID D OUT t OD VALID D IN VALID D OUT t OD tOE OE# t DH tCPA t DS VALID D IN OPEN t OD t OE t OE t OEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD MIN tCAS tCLZ tCP 38 0 45 0 0 42 0 49 ns ns tPC ns ns ns tRAC ns ns tRASP 13 8 8 tCSH tCWD tCWL tDH tDS 10,000 0 8 tCPA tCRP MIN MAX 30 SYMBOL UNITS ns ns ns tCAC tCAH -5 -6 MAX 25 15 10 10 10,000 0 10 tOD tPRWC tRAD tRAH tRCD 5 45 ns ns ns tRCS 5 38 28 8 35 10 ns ns tRWD 8 0 10 0 ns ns tWP 28 35 MAX MIN MAX UNITS 0 12 12 0 15 15 8 12 ns ns ns 20 47 25 56 ns ns tOE tOEH tRP tRSH tRWL -6 MIN 50 9 9 50 11 60 ns ns ns 125,000 ns ns 12 10 125,000 60 14 0 30 13 0 40 15 ns ns ns 67 13 79 15 ns ns 5 5 ns NOTE: 1. tPC is for LATE WRITE cycles only. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RP t RASP RAS# V IH V IL t CSH tPC tCRP CAS# t RCD tRSH tPC t CP t CAS t CP t CAS t CP t CAS V IH V IL tAR tRAD tASR ADDR V IH V IL t ACH tRAH tASC ROW tCAH t ASC COLUMN (A) t CAH COLUMN (B) V IH V IL ROW tWCS tWCH tAA tAA tCPA tRAC tCAC tCAC tCOH DQ V IOH V IOL t CAH COLUMN (N) tRCH tRCS WE# tASC OPEN t DS VALID DATA (B) VALID DATA (A) t DH t WHZ VALID DATA IN tOE OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR MIN tCAS tCOH tCP MIN 12 38 15 45 0 0 0 0 ns ns tRAD ns ns ns tRASP ns ns tRCS tRSH tWCS 13 8 8 10,000 3 8 tCPA MAX 30 15 10 10 10,000 3 10 tCRP 5 5 ns ns tCSH 38 8 0 45 10 0 ns ns ns tDH tDS 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 SYMBOL UNITS ns ns ns tCAC tCAH -5 -6 MAX 25 28 35 MIN tOE MIN 12 tPC 20 tRAC tRAH tRCD tRCH tRP tWCH tWHZ 16 -6 MAX UNITS 15 ns ns 60 ns ns ns 125,000 ns ns 25 50 9 9 50 11 MAX 12 10 125,000 60 14 0 0 30 0 0 40 ns ns ns 13 8 15 10 ns ns 0 0 12 0 0 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM READ CYCLE (with WE#-controlled disable) RAS# V IH V IL tCSH tRCD tCRP CAS# tCAS tCP V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH tASC COLUMN COLUMN tRCS WE# tRCH tWPZ tRCS V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL tWHZ OPEN OPEN VALID DATA tOE OE# tCLZ tOD V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR tCAS tCLZ MIN 25 38 45 0 0 0 0 tCAC tCAH -6 MAX 13 8 8 10,000 10 10 -5 MAX UNITS 30 ns ns tOD tRAC 15 ns ns ns ns ns tRCD 10,000 tCRP 0 8 5 0 10 5 ns ns ns tCSH 38 45 ns tCP 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 SYMBOL MAX MIN MAX UNITS 0 12 12 0 15 15 ns ns 60 tOE 9 9 12 10 ns ns ns tRCH 11 0 14 0 ns ns tRCS 0 tRAD tRAH 50 tWHZ tWPZ 17 -6 MIN 0 12 10 15 10 ns ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) tRC tRAS RAS# tRP V IH V IL tRPC tCRP CAS# V IH V IL tASR ADDR tRAH V IH V IL ROW ROW V DQ V OH OL OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) t RP RAS# t RAS t RP NOTE 1 t RAS V IH V IL t RPC t CP CAS# V IH V IL DQ V OH V OL t CSR t CSR t CHR OPEN t WRP WE# t RPC t CHR t WRH t WRP t WRH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR tCHR tCP tCRP tCSR tRAH MIN -6 MAX MIN -5 MAX UNITS SYMBOL tRAS tRC 0 8 0 10 ns ns 8 5 10 5 ns ns tRP 5 9 5 10 ns ns tWRH tRPC tWRP MIN 50 84 -6 MAX 10,000 MIN 60 104 MAX 10,000 UNITS ns ns 30 5 40 5 ns ns 8 8 10 10 ns ns NOTE: 1. End of first CBR REFRESH cycle. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW) tRAS RAS# tRAS V IH V IL tCRP CAS# tRP tRSH tRCD tCHR V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tAA tRAC tOFF tCAC tCLZ V DQ V OH OL OPEN VALID DATA OPEN tOD tOE tORD V OE# V IH IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR MIN -6 MAX 25 MIN -5 MAX 30 38 45 UNITS ns ns SYMBOL tOE tOFF tASC 0 0 ns tORD tASR 0 0 tRAC tCAH 8 10 ns ns ns tCHR 8 0 10 0 ns ns tRAS ns ns tRP tCAC tCLZ tCRP tOD 13 5 0 12 15 5 0 15 tRAD tRAH tRCD tRSH MIN 0 -6 MAX 12 12 0 MIN 0 9 9 30 13 UNITS ns ns 60 ns ns ns 10,000 ns ns 0 50 50 11 MAX 15 15 ns 12 10 10,000 60 14 40 15 ns ns NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) RAS# V IH V IL (( )) tRPC tCSR tRPS NOTE 2 tRPC (( )) tCP CAS# NOTE 1 tRASS tRP (( )) tCP tCHD (( )) (( )) V IH V IL V DQ V OH OL (( )) tWRP OPEN tWRP tWRH tWRH (( )) (( )) V WE# V IH IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tCHD tCP tCSR tRASS tRP MIN 15 8 5 100 30 -6 MAX MIN 15 10 5 100 40 -5 MAX UNITS ns ns ns µs ns SYMBOL tRPC tRPS tWRH tWRP MIN 5 90 8 8 -6 MAX MIN 5 105 10 10 MAX UNITS ns ns ns ns NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM 32-PIN PLASTIC SOJ (400 mil) .829 (21.05) .823 (20.90) .445 (11.31) .435 (11.05) .405 (10.29) .399 (10.13) PIN #1 ID .050 (1.27) TYP .750 (19.05) TYP .037 (0.95) MAX DAMBAR PROTRUSION .024 (0.61) .032 (0.82) .026 (0.67) .030 (0.76) MIN .145 (3.68) .132 (3.35) .095 (2.42) .080 (2.03) SEATING PLANE .020 (0.51) .015 (0.38) R .040 (1.02) .030 (0.77) .380 (9.65) .360 (9.14) NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8 MEG x 8 EDO DRAM 32-PIN PLASTIC TSOP (400 mil) 20.96 ±0.08 SEE DETAIL A 1.27 TYP 0.95 11.76 ±0.10 10.16 ±0.08 PIN 1 ID 0.43 +0.07 -0.13 0.15 +0.03 -0.02 0.25 0.10 1.20 MAX GAGE PLANE 0.10 +0.10 -0.05 0.80 TYP 0.50 ±0.10 DETAIL A NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc.