4 MEG x 16 FPM DRAM DRAM MT4LC4M16F5 For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html FEATURES PIN ASSIGNMENT (Top View) • Single +3.3V ±0.3V power supply • Industry-standard x16 pinout, timing, functions, and packages • 12 row, 10 column addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • FAST PAGE MODE (FPM) access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms OPTIONS 50-Pin TSOP VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VCC WE# RAS# NC NC NC NC A0 A1 A2 A3 A4 A5 VCC MARKING • Plastic Package 50-pin TSOP (400 mil) TG • Timing 50ns access 60ns access -5 -6 • Refresh Rate Standard Refresh None Part Number Example MT4LC4M16F5TG-5 KEY TIMING PARAMETERS SPEED -5 -6 tRC 90ns 110ns tRAC 50ns 60ns tPC 30ns 35ns tAA 25ns 30ns tCAC 13ns 15ns 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC VSS CASL# CASH# OE# NC NC NC A11 A10 A9 A8 A7 A6 VSS NOTE: 1. The # symbol indicates signal is active LOW. GENERAL DESCRIPTION The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration. The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 rowaddress bits (A0-A11) and 10 column-address bits (A0A9). In addition, both byte and word accesses are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) are such that the internal 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and the last to transition back HIGH. The CAS# functionality and timing related to driving or latching data are such that each CAS# signal independently controls the associated eight DQ pins. The row address is latched by the RAS# signal, then the column address by CAS#. The device provides FASTPAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFYWRITE) within a given row. The MT4LC4M16F5 must be refreshed periodically in order to retain stored data. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM FAST PAGE MODE ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 16 I/O pins (DQ0-DQ15). Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. The WE# signal must be activated to execute a WRITE operation; otherwise a READ operation will be performed. The OE# signal must be activated to enable the DQ output drivers for a read access and can be deactivated to disable output data if necessary. FAST-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation. FUNCTIONAL BLOCK DIAGRAM MT4LC4M16F5 (12 row addresses) WE# CASL# CAS# 16 DATA-IN BUFFER CASH# DQ0DQ15 16 DATA-OUT BUFFER NO. 2 CLOCK GENERATOR OE# 16 10 COLUMNADDRESS BUFFER(10) 16 COLUMN DECODER 10 1,024 REFRESH CONTROLLER A0A11 SENSE AMPLIFIERS I/O GATING 1,024 x 16 RAS# 12 4,096 NO. 1 CLOCK GENERATOR 4,096 x 16 ROW SELECT 12 ROWADDRESS BUFFERS (12) ROW DECODER 12 COMPLEMENT SELECT REFRESH COUNTER 4,096 x 1,024 x 16 MEMORY ARRAY VDD VSS 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM DRAM REFRESH The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC4M16F5 internally refreshes one row for every CBR cycle, so executing 4,096 CBR cycles covers all rows. The CBR REFRESH will invoke the internal refresh counter for automatic RAS# address- ing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method some compatibility issues may become apparent. JEDEC strongly recommends the use of CBR REFRESH for this device. STANDBY Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time. WORD WRITE LOWER BYTE WRITE RAS# CASL# CASH# WE# LOWER BYTE (DQ0-DQ7) OF WORD UPPER BYTE (DQ8-DQ15) OF WORD STORED DATA 1 1 0 1 1 1 1 1 INPUT DATA 0 0 1 0 0 0 0 0 INPUT DATA STORED DATA 0 0 1 0 0 0 0 0 STORED DATA 0 0 1 0 0 0 0 0 INPUT DATA 1 1 0 1 1 1 1 1 0 1 0 1 X X X X X 1 0 1 0 1 1 0 1 0 1 0 1 0 X X X X 1 0 1 0 X 1 1 1 1 1 X X 1 1 X X 1 1 1 1 1 1 X X 1 1 0 0 0 0 ADDRESS 0 INPUT DATA STORED DATA 1 1 0 1 1 1 1 1 ADDRESS 1 X = NOT EFFECTIVE (DON'T CARE) Figure 1 WORD and BYTE WRITE Example 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM WORD READ LOWER BYTE READ RAS# CASL# CASH# WE# LOWER BYTE (DQ0-DQ7) OF WORD UPPER BYTE (DQ8-DQ15) OF WORD STORED DATA 1 OUTPUT DATA 1 OUTPUT DATA 1 STORED DATA 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 Z Z 0 1 0 STORED DATA 1 1 0 1 1 OUTPUT DATA 1 OUTPUT DATA 1 STORED DATA 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 Z Z Z Z 0 1 Z Z Z 0 1 0 0 1 0 0 1 0 Z Z Z Z Z Z 0 1 0 0 0 Z Z 0 0 0 0 0 0 Z Z Z Z 0 0 0 Z 0 0 0 Z Z 0 ADDRESS 0 ADDRESS 1 Z = High-Z Figure 2 WORD and BYTE READ Example 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VCC Relative to VSS ................ -1V to +4.6V Voltage on NC, Inputs or I/O Pins Relative to VSS ....................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0°C to +70°C Storage Temperature (plastic) ............ -55°C to +150°C Power Dissipation ................................................... 1W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VCC 3 3.6 V INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC VIH 2 VCC + 0.3 V 37 INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 37 II -2 2 µA OUTPUT HIGH VOLTAGE: IOUT = -2mA VOH 2.4 – V OUTPUT LOW VOLTAGE: IOUT = 2mA VOL – 0.4 V IOZ -5 5 µA INPUT LEAKAGE CURRENT: Any input at VIN (0V £ VIN £ VCC + 0.3V); All other pins not under test = 0V OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V £ VOUT £ VCC + 0.3V); DQ is disabled and in High-Z state UNITS NOTES IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL SPEED MAX STANDBY CURRENT: TTL (RAS# = CAS# = VIH) UNITS NOTES IDD1 ALL 1 mA STANDBY CURRENT: CMOS (RAS# = CAS# ³ VCC - 0.2V; DQs may be left open; Other inputs: VIN ³ VCC - 0.2V or VIN £ 0.2V) IDD2 ALL 500 µA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) IDD3 -5 -6 150 165 mA 25 OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) IDD4 -5 -6 105 95 mA 25 REFRESH CURRENT: RAS# ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) IDD5 -5 -6 150 165 mA 22 REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) IDD6 -5 -6 150 165 mA 4, 7 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM CAPACITANCE (Note: 2) PARAMETER SYMBOL MAX UNITS Input Capacitance: Address pins CI 1 5 pF Input Capacitance: RAS#, CAS#, WE#, OE# CI 2 7 pF Input/Output Capacitance: DQ CIO 7 pF UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) Last CAS# going LOW to first CAS# to return HIGH CAS# to output in Low-Z CAS# precharge time (FAST PAGE MODE) Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLCH tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH MIN tOFF 3 0 30 76 tORD tPC tPRWC 40 0 0 48 tRAH 6 MIN 8 13 15 5 3 8 10,000 15 10 15 15 5 3 10 30 5 50 5 36 13 8 0 3 13 13 13 10,000 35 5 60 5 40 15 10 0 3 15 15 15 13 3 0 35 85 50 13 8 MAX 30 45 0 0 55 13 tRAC tRAD -6 MAX 25 15 60 15 10 ns ns ns ns ns ns ns 26 18 28 26 32, 34 4, 27 29 26, 28 13, 32 27 27 27 4, 26 18, 26 28 19, 28 19, 28 23, 24, 36 20 24 17, 23, 28 30 30 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER RAS# pulse width RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 -5 SYMBOL tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP 7 MIN 50 50 90 18 0 0 -6 MAX 10,000 125,000 MIN 60 60 110 20 0 0 64 30 0 0 13 131 73 13 2 8 40 0 8 10 10 50 MAX 10,000 125,000 64 40 0 0 15 155 85 15 2 10 45 0 10 10 10 50 UNITS ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 14, 26 16, 27 26 22 16 35 18 35 18, 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM NOTES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD and tCWD define READ-MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. The values shown were calculated for reference allowing 10ns for the external latching of read data and application of write data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not applicable in a LATE WRITE cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 22. RAS#-ONLY REFRESH requires that all 4,096 rows be refreshed at least once every 64ms. CBR REFRESH requires that at least 4,096 cycles be completed every 64ms. 23. The DQs go High-Z during READ cycles once tOD or tOFF occur. If CAS# goes HIGH before OE#, the DQs will go High-Z regardless of the state of OE#. If CAS# stays LOW while OE# is brought HIGH, the DQs will go High-Z. If OE# is brought back LOW (CAS# still LOW), the DQs will provide the previously read data. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while CAS# remains LOW, the DQs will remain open. 25. Column address changed once each cycle. 26. The first CASx# edge to transition LOW. 27. The last CASx# edge to transition HIGH. 28. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 29. Last falling CASx# edge to first rising CASx# edge. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V; f = 1 MHz. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. An initial pause of 100µs is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 5ns. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. If CAS# = VIH, data output is High-Z. If CAS# = VIL, data output may contain data from the last valid READ cycle. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM NOTES (continued) 30. Last rising CASx# edge to next cycle’s last rising CASx# edge. 31. Last rising CASx# edge to first falling CASx# edge. 32. First DQs controlled by the first CASx# to go LOW. 33. Last DQs controlled by the last CASx# to go HIGH. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 34. 35. 36. 37. 9 Each CASx# must meet minimum pulse width. Last CASx# to go LOW. All DQs controlled, regardless CASL# and CASH#. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width £ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width £ 3ns, and the pulse width cannot be greater than one third of the cycle rate. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM READ CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tRCD tCRP CAS# tRRH tCAS V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH COLUMN ROW tRCH tRCS WE# V IH V IL tAA tRAC tOFF tCAC tCLZ V DQ V IOH IOL OPEN OPEN VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR -6 MAX MIN 25 tASC 40 0 45 0 tASR 0 0 tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tOD tOE 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 13 8 13 5 10,000 -5 MAX UNITS 30 ns ns ns 15 10 15 5 10,000 SYMBOL tOFF tRAC tRAD ns ns tRAH ns ns ns tRC tRAS tRCD tRCH 3 5 3 5 ns ns tRCS 50 3 60 3 tRRH 15 ns ns 15 ns 13 13 tRP tRSH 10 MIN 3 13 8 50 -6 MAX 13 50 10,000 MIN 3 15 10 60 MAX 15 60 UNITS ns ns 10,000 ns ns ns 90 18 110 20 ns ns 0 0 30 0 0 40 ns ns ns 0 13 0 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM EARLY WRITE CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tCRP CAS# tRCD tCAS V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH ROW COLUMN tCWL tRWL tWCR tWCH tWCS tWP WE# V IH V IL tDS V DQ V IOH IOL tDH VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL tDH tDS tRAD 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 MIN 40 -6 MAX 0 0 8 13 5 MIN 45 -5 MAX 0 0 10 10,000 15 5 10,000 UNITS ns SYMBOL MIN tRAH 8 ns ns ns tRAS 50 90 ns ns tRP tRC tRCD tRSH 5 50 13 5 60 15 ns ns ns tRWL 8 0 10 0 ns ns tWCS 13 15 ns tWCH tWCR tWP 11 -6 MAX MIN MAX 10 10,000 60 110 UNITS ns 10,000 ns ns 18 30 13 20 40 15 ns ns ns 13 8 15 10 ns ns 40 0 8 45 0 10 ns ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS RAS# V IH V IL tCRP CAS# tCSH tRSH tCAS tRCD V IH V IL tAR tRAD tRAH tASR ADDR tRP V IH V IL tASC tCAH ROW COLUMN tRCS WE# ROW tRWD tCWD tCWL tRWL tAWD tWP V IH V IL tAA tRAC tCAC tDS tCLZ V DQ V IOH IOL VALID D OUT OPEN VALID D IN tOD tOE OE# tDH OPEN tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD MIN tCAS tCLCH MIN -5 MAX 30 UNITS ns SYMBOL tOD 40 0 45 0 ns ns tOE 0 48 0 55 tRAC 15 ns ns ns ns ns tRAS 10,000 tCAC tCAH -6 MAX 25 13 8 13 10,000 10 15 tRAD tRAH tRCD 5 3 5 ns ns ns tRCS 50 36 60 40 ns ns tRWC 13 8 15 10 ns ns tRWL tDH tDS 0 0 ns tCRP tCSH tCWD tCWL 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 tRP tRSH tRWD tWP 12 -6 MAX 13 MIN 3 13 tOEH 5 3 5 tCLZ MIN 3 13 UNITS ns 15 ns ns 60 ns ns ns 10,000 ns ns 15 50 13 8 50 18 MAX 15 15 10 10,000 60 20 0 30 13 0 40 15 ns ns ns 131 73 155 85 ns ns 13 8 15 10 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM FAST-PAGE-MODE READ CYCLE tRASP tRP V IH V IL RAS# tCSH tCRP tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL CAS# tAR tRAD tRAH tASR V IH V IL ADDR tASC ROW tCAH tASC COLUMN tRCS tCAH COLUMN tCAH COLUMN tRCS tRCH tRCH ROW tRCS tRRH tRCH V IH V IL WE# tAA tRAC tAA tCPA tCAC tOFF tCLZ DQ tASC V IOH V IOL tOFF tCLZ tCAC tOFF tCLZ VALID DATA tOD OPEN tOE OE# tCAC tAA tCPA tOE VALID DATA tOD tOE VALID DATA tOD OPEN V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR 40 0 0 8 tCAS 13 5 3 tCP tCRP tCSH tOD 3 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 30 ns ns ns ns 15 10,000 15 5 3 10,000 10 30 5 50 UNITS 10 8 tCPA -5 MAX 45 0 0 13 tCAH tCLZ MIN 25 tCAC tCLCH -6 MAX 35 5 60 13 3 15 SYMBOL tOE tOFF tPC MAX 13 MIN MAX 15 UNITS ns 3 30 13 3 35 15 ns ns 60 ns ns ns 125,000 ns ns tRAC ns ns tRAD ns ns ns tRASP ns ns tRCS ns ns tRRH tRAH tRCD tRCH tRP tRSH -6 MIN 50 13 8 50 18 15 10 125,000 60 20 0 0 30 0 0 40 ns ns ns 0 13 0 15 ns ns ns 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM FAST-PAGE-MODE EARLY WRITE CYCLE tRP tRASP RAS# V IH V IL tCSH tCRP CAS# tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH tASC COLUMN tCAH COLUMN tCWL tWCH tWCS tWCS ROW tCWL tWCH tWCS tWP tWP V IH V IL tWCR tDH tDS V DQ V IOH IOL OE# tCAH COLUMN tCWL tWCH tWP WE# tASC tDS VALID DATA tDH tRWL tDH tDS VALID DATA VALID DATA V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCLCH tCP MIN 40 0 0 8 13 5 -6 MAX 10,000 MIN 45 0 0 10 15 5 -5 MAX 10,000 UNITS ns ns SYMBOL tPC tRAD ns ns ns ns tRAH tRASP tRCD tRP 8 5 10 5 ns ns tRSH 60 15 10 ns ns ns tWCH tDH 50 13 8 tDS 0 0 ns tWP tCRP tCSH tCWL 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 tRWL tWCR tWCS 14 MIN -6 MAX 30 13 8 50 18 MIN MAX 35 15 10 125,000 60 20 UNITS ns ns ns 125,000 ns ns 30 13 13 40 15 15 ns ns ns 8 40 10 45 ns ns 0 8 0 10 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP tRP V IH V IL RAS# tCSH tCRP tCAS tRSH tPRWC tCAS tPC NOTE 1 tRCD tCP tCP tCAS tCP V IH V IL CAS# tAR tRAD tRAH tASR V IH V IL ADDR tASC ROW tCAH tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRWD tRCS tCWL tWP tAWD tCWD tWP tAWD tCWD V IH V IL WE# tAA tAA tRAC tDH tCAC tCLZ V IOH V IOL tAA tDH tCPA tDS DQ tRWL tCWL tCWL tWP tAWD tCWD tCAC tCLZ VALID D OUT OPEN tDH tDS tCAC tCLZ VALID DIN VALID D OUT tOD VALID D IN VALID D OUT tOD tOE OE# tCPA tDS VALID D IN OPEN tOD tOE tOE tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD MIN 45 0 0 0 0 ns ns tOE tOEH 13 15 ns ns ns 48 55 ns ns ns tPC 30 76 35 85 ns ns ns ns tRAD ns ns ns tRASP 13 8 tCAS 13 5 tCP tCRP tCSH tCWD tCWL tDH 15 10 10,000 15 5 3 8 tCPA MAX 30 -6 40 tCAH tCLZ MIN -5 UNITS ns ns tCAC tCLCH -6 MAX 25 10,000 3 10 30 35 SYMBOL MIN tDS 0 tOD 3 tPRWC tRAC tRAH tRCD tRCS 5 50 5 60 ns ns tRP 36 13 40 15 ns ns tRWD 8 10 ns tWP tRSH tRWL MAX MIN 13 13 3 50 13 8 50 18 MAX 0 ns 15 15 60 ns ns ns 125,000 ns ns 15 10 125,000 60 20 UNITS 0 30 13 0 40 15 ns ns ns 73 13 85 15 ns ns 8 10 ns NOTE: 1. tPC is for LATE WRITE only. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP RAS# t RP V IH V IL t RSH t CSH t CRP CAS# t PC t RCD t CAS t CP t CAS t CP V IH V IL t AR t RAD t ASR ADDR V IH V IL ROW tASC t CAH t ASC t RAH COLUMN t CAH ROW COLUMN t CWL t RWL t WP t RCS t WCS WE# V IH V IL t CAC NOTE 1 t OFF t DS t CLZ DQ t WCH V OH V OL VALID DATA OPEN t DH VALID DATA t AA t RAC DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 40 0 0 tCAC 8 tCAS 13 3 8 tCP tCRP tCSH tCWL tDH tDS MIN -5 MAX 30 45 0 0 13 tCAH tCLZ -6 MAX 25 15 10 10,000 15 3 10 10,000 UNITS ns SYMBOL tOFF MAX MIN MAX UNITS 3 30 13 3 35 15 ns ns 60 ns ns ns ns ns tPC tRAD 13 ns ns tRAH ns ns ns tRCD 8 50 18 tRAC tRASP tRCS tRP 5 50 5 60 ns ns tRSH 13 8 0 15 10 0 ns ns ns tWCH tRWL tWCS tWP -6 MIN 50 15 125,000 10 60 20 125,000 ns ns ns 0 30 0 40 ns ns 13 13 8 15 15 10 ns ns ns 0 8 0 10 ns ns NOTE: 1. Do not drive input data prior to output data going High-Z. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) tRC tRAS RAS# tRP V IH V IL tCRP CAS# tRPC V IH V IL tASR ADDR tRAH V IH V IL ROW ROW V DQ V OH OL OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP RAS# tRAS tRP NOTE 1 tRAS V IH V IL tRPC tCP CAS# V IH V IL DQ V OH V OL tCSR tCSR tCHR OPEN tWRP WE# tRPC tCHR tWRH tWRP tWRH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR tCHR tCP tCRP tCSR tRAH MIN -6 MAX MIN -5 MAX UNITS SYMBOL tRAS tRC 0 15 0 15 ns ns 8 5 10 5 ns ns tRP 5 8 5 10 ns ns tWRH tRPC tWRP MIN 50 90 -6 MAX 10,000 MIN 60 110 MAX 10,000 UNITS ns ns 30 0 40 0 ns ns 10 10 10 10 ns ns NOTE: 1. End of first CBR REFRESH cycle. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW) tRC tRAS RAS# tRAS V IH V IL tCRP CASL#/CASH# tRP tRSH tRCD tCHR V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tAA tRAC tCAC tCLZ DQx V IOH V IOL tOFF OPEN VALID DATA OPEN tOE OE# V IH V IL tOD tORD DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR tCHR tCLZ tCRP tOD MIN 25 40 45 0 0 0 0 tCAC tCAH -6 MAX -5 MAX UNITS SYMBOL 30 ns ns tOE MAX tOFF 3 13 13 ns ns ns tORD 0 tRAC tRAD 13 10 15 ns ns tRAH 8 50 3 5 3 3 5 3 ns ns ns tRCD 13 15 15 tRAS tRP tRSH MIN MAX UNITS 3 15 15 ns ns 60 ns ns ns 0 50 8 15 13 -6 MIN 18 30 13 15 10,000 10 60 10,000 20 40 15 ns ns ns ns ns NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 16 FPM DRAM 50-PIN PLASTIC TSOP (400 mil) 21.04 20.88 .88 TYP 50 11.86 11.66 10.21 10.11 1 PIN #1 ID SEE DETAIL A 25 .80 TYP .18 .13 .45 .30 .25 .20 .25 GAGE PLANE .10 1.2 MAX .60 .40 DETAIL A .80 TYP NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 4 Meg x 16 FPM DRAM D28_2.p65 – Rev. 5/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc.