4 MEG x 4 FPM DRAM MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 DRAM For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT (Top View) • Industry-standard x4 pinout, timing, functions, and packages • High-performance, low-power CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or +5V ±0.5V) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR) • Optional self refresh (S) for low-power data retention • 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh) • FAST-PAGE-MODE (FPM) access • 5V tolerant inputs and I/Os on 3.3V devices OPTIONS 24/26-Pin SOJ VCC DQ0 DQ1 WE# RAS# **NC/A11 A10 A0 A1 A2 A3 VCC MARKING • Voltage 3.3V 5V • Refresh Addressing 2,048 (2K) rows 4,096 (4K) rows • Packages Plastic SOJ (300 mil) Plastic TSOP (300 mil) • Timing 50ns access 60ns access • Refresh Rates Standard Refresh Self Refresh (128ms period) LC C B1 A1 DJ TG -5 -6 None S* Part Number Example: MT4LC4M4B1DJ KEY TIMING PARAMETERS 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 tRAC 50ns 60ns tPC 20ns 35ns tAA 25ns 30ns tCAC 13ns 15ns 8 9 10 11 12 13 19 18 17 16 15 14 VCC VSS DQ0 DQ3 DQ1 DQ2 WE# CAS# RAS# OE# **NC/A11 A9 A10 A0 A8 A1 A7 A2 A6 A3 A5 VCC A4 VSS 1 2 3 4 5 6 26 25 24 23 22 21 VSS DQ3 DQ2 CAS# OE# A9 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS 4 MEG x 4 FPM DRAM PART NUMBERS *Contact factory for availability tRC 84ns 110ns 26 25 24 23 22 21 **NC on 2K refresh and A11 on 4K refresh options. NOTE: 1. The 4 Meg x 4 FPM DRAM base number differentiates the offerings in one place—MT4LC4M4B1. The fifth field distinguishes various options: B1 designates a 2K refresh and A1 designates a 4K refresh for FPM DRAMs. 2. The # symbol indicates signal is active LOW. SPEED -5 -6 1 2 3 4 5 6 24/26-Pin TSOP PART NUMBER REFRESH V CC ADDRESSING PACKAGE REFRESH MT4LC4M4B1DJ-6 MT4LC4M4B1DJ-6 S MT4LC4M4B1TG-6 MT4LC4M4B1TG-6 S MT4LC4M4A1DJ-6 MT4LC4M4A1DJ-6 S MT4LC4M4A1TG-6 MT4C4M4A1TG-6 S MT4C4M4B1DJ-6 MT4C4M4B1DJ-6 S MT4C4M4B1TG-6 MT4C4M4B1TG-6 S MT4C4M4A1DJ-6 MT4C4M4A1DJ-6 S MT4C4M4A1TG-6 MT4C4M4A1TG-6 S 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5V 5V 5V 5V 5V 5V 5V 5V 2K 2K 2K 2K 4K 4K 4K 4K 2K 2K 2K 2K 4K 4K 4K 4K SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self Standard Self tRP 30ns 40ns 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the latter 11 bits for 2K and the latter 10 bits for 4K; address pins A10 and A11 are “Don’t Care”). READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. If WE# goes LOW prior to CAS# going LOW, the output pins remain open (High- Z) until the next CAS# cycle, regardless of OE#. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READMODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location. The four data inputs and the four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE# and OE#. The MT4LC4M4B1 and MT4LC4M4A1 must be refreshed periodically in order to retain stored data. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the page mode of operation, i.e., closes the page. FAST PAGE MODE ACCESS STANDBY Page operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a rowaddress-defined page boundary. The page cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time. 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 DRAM REFRESH Preserve correct memory cell data by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR, or HIDDEN) so that all combinations of RAS# addresses (2,048 for 2K and 4,096 for 4K) are executed within tREF (MAX), regardless of sequence. The CBR and SELF REFRESH cycles will invoke the internal refresh counter for automatic RAS# addressing. An optional self refresh mode is also available the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The “S” option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 31.25µs per row for a 4K refresh and 62.5µs per row for a 2K refresh, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes RAS#-ONLY or burst CBR refresh sequence, all rows must be refreshed with a refresh rate of tRC minimum prior to resuming normal operation. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM FUNCTIONAL BLOCK DIAGRAM – 2K REFRESH WE# CAS# NO. 2 CLOCK GENERATOR DATA-IN BUFFER 4 DATA-OUT BUFFER 4 DQ0 DQ1 DQ2 DQ3 4 OE# 11 COLUMNADDRESS BUFFER(11) 10 COLUMN DECODER 1 1,024 REFRESH CONTROLLER 4 SENSE AMPLIFIERS I/O GATING 1,024 11 2,048 2,048 ROW TRANSFER (1 OF 2) ROW TRANSFER (2 OF 2) 11 ROWADDRESS BUFFERS (11) 2,048 2,048 2,048 ROW SELECT (2 of 4,096) 11 COMPLEMENT SELECT REFRESH COUNTER ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 4,096 x 1,024 x 4 MEMORY ARRAY NO. 1 CLOCK GENERATOR RAS# VDD VSS FUNCTIONAL BLOCK DIAGRAM – 4K REFRESH WE# CAS# NO. 2 CLOCK GENERATOR DATA-IN BUFFER 4 DATA-OUT BUFFER 4 DQ0 DQ1 DQ2 DQ3 4 OE# RAS# 10 COLUMNADDRESS BUFFER(10) COLUMN DECODER 10 1,024 REFRESH CONTROLLER 4 SENSE AMPLIFIERS I/O GATING 1,024 12 12 4,096 NO. 1 CLOCK GENERATOR 4,096 4,096 ROW SELECT (1 of 4096) 12 ROWADDRESS BUFFERS (12) COMPLEMENT SELECT REFRESH COUNTER ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 4,096 x 1,024 x 4 MEMORY ARRAY VDD Vss 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VCC Pin Relative to VSS 3.3V............................................. ......... -1V to +4.6V 5V................................................ ............ -1V TO +7V Voltage on NC, Inputs or I/O Pins Relative to VSS 3.3V............................................. ......... -1V to +5.5V 5V................................................ ............ -1V TO +7V Operating Temperature, TA (ambient) .... 0°C to +70°C Storage Temperature (plastic) ............ -55°C to +150°C Power Dissipation ................................................... 1W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 5, 6) (VCC (MIN) £ VCC£ VCC (MAX)) PARAMETER/CONDITION SYMBOL 3.3V MIN MAX MIN 5V MAX UNITS NOTES SUPPLY VOLTAGE VCC 3 3.6 4.5 5.5 V INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC VIH 2 5.5 2.4 Vcc+1 V 24 INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC VIL -1.0 0.8 -0.5 0.8 V 24 II -2 2 -2 2 µA OUTPUT HIGH VOLTAGE: IOUT = -2mA VOH 2.4 – 2.4 – V OUTPUT LOW VOLTAGE: IOUT = 2mA VOL – 0.4 – 0.4 V IOZ -5 5 -5 5 µA INPUT LEAKAGE CURRENT: Any input at VIN [0V £ VIN £ VCC (MAX)]; All other pins not under test = 0V OUTPUT LEAKAGE CURRENT: Any output at VOUT [0V £ VOUT £ VCC (MAX)]; DQ is disabled and in High-Z state 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6) [Vcc (MIN) £ Vcc £ Vcc (MAX)] 3.3V PARAMETER/CONDITION 5V 2K 4K 2K 4K SYM SPEED REFRESH REFRESH REFRESH REFRESH UNITS NOTES STANDBY CURRENT: TTL (RAS# = CAS# = VIH) ICC1 ALL 1 1 1 1 mA STANDBY CURRENT: CMOS (non-“S” version only) (RAS# = CAS# = other inputs = VCC - 0.2V) ICC2 ALL 500 500 500 500 mA STANDBY CURRENT: CMOS (“S” version only) (RAS# = CAS# = other inputs = VCC - 0.2V) ICC2 ALL 150 150 150 150 µA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC3 -5 -6 110 100 90 80 140 130 120 110 mA 23 OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC4 -5 -6 110 100 100 90 110 100 100 90 mA 23 REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) ICC5 -5 -6 110 100 90 80 140 130 120 110 mA REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC6 -5 -6 110 100 90 80 140 130 120 110 mA 4, 7 ALL 300 300 300 300 µA 4, 7 tRC 62.5 31.25 62.5 31.25 µs 23 ALL 300 300 300 300 µA 4, 7 REFRESH CURRENT: Extended (“S” version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) ICC7 ICC8 CAPACITANCE (Note: 6) PARAMETER SYMBOL MAX UNITS Input Capacitance: Address pins CI1 5 pF Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7 pF Input/Output Capacitance: DQ CIO 7 pF 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN) £ Vcc £ Vcc (MAX)] AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (2,048 cycles) Refresh period (4,096 cycles) 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH MIN tOFF 0 0 20 47 tORD tPC tPRWC -6 MAX 25 38 0 0 42 MIN 45 0 0 49 13 8 8 15 8 0 8 10,000 15 10 10 15 10 0 10 28 5 38 5 28 8 8 0 0 12 12 8 tRAC 9 9 50 50 100 84 11 0 0 tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF 6 15 15 10 12 10,000 125,000 32 64 tREF 10,000 35 5 45 5 35 10 10 0 0 0 0 25 56 50 tRAD MAX 30 15 60 12 10 60 60 100 104 14 0 0 10,000 125,000 32 64 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES ns ns ns ns ns ns ns ns ns µs ns ns ns ns ms ms 17, 22 18 4 22 13 4 18 19 19 22 20 15 14 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN) £ Vcc £ Vcc (MAX)] AC CHARACTERISTICS PARAMETER Refresh period “S” version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 -5 SYMBOL tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP 7 MIN 30 5 90 0 13 116 67 13 2 8 38 0 5 8 8 -6 MAX 128 50 MIN 40 5 105 0 15 140 79 15 2 10 45 0 5 10 10 MAX 128 50 UNITS ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 140 16 19 18 4, 23 4, 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM NOTES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V or 5.0V; f = 1 MHz. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. An initial pause of 100µs is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 5ns. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. If CAS# = VIH, data output is High-Z. If CAS# = VIL, data output may contain data from the last valid READ cycle. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was con- 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 16. 17. 18. 19. 20. 21. 22. 23. 24. 8 trolled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD, and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD ³ tRWD (MIN), tAWD ³ tAWD (MIN), and tCWD ³ tCWD (MIN), the cycle is a READ-MODIFYWRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not applicable in a LATE WRITE cycle. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not permissible and should not be attempted. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. The 3ns minimum is a parameter guaranteed by design. Column address changed once each cycle. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width £ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width £ 10ns, and the pu lse width cannot be greater than one third of the cycle rate. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM READ CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tRCD tCRP CAS# tRRH tCAS V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH COLUMN ROW tRCH tRCS WE# V IH V IL tAA tRAC tOFF tCAC tCLZ V DQ V IOH IOL OPEN OPEN VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR -6 MAX MIN 25 tASC 38 0 45 0 tASR 0 0 tCAC tCAH tCAS tCLZ tCRP 13 8 8 0 tCSH 5 38 tOD 0 tOE 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 10,000 -5 MAX UNITS 30 ns ns ns tOFF tRAD 9 ns ns tRAH 9 50 ns ns ns tRC ns ns tRCS ns ns tRRH 15 10 10 0 10,000 5 45 12 12 0 15 15 SYMBOL MAX MIN MAX UNITS 0 12 50 0 15 60 ns ns ns tRAC tRAS tRCD tRCH tRP tRSH 9 -6 MIN 12 10,000 10 60 10,000 ns ns 84 11 0 104 14 0 ns ns ns 0 30 0 40 ns ns 0 13 0 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM EARLY WRITE CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tCRP CAS# tRCD tCAS V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH ROW COLUMN tCWL tRWL tWCR tWCH tWCS tWP WE# V IH V IL tDS V DQ V IOH IOL tDH VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCRP MIN -6 MAX MIN -5 MAX UNITS SYMBOL 38 0 0 45 0 0 ns ns ns tRAH 8 8 10 10 ns ns tRCD 10,000 10,000 tRAS tRC tRP 5 38 8 5 45 10 ns ns ns tRSH 10 0 ns ns tWCR tDS 8 0 tRAD 9 12 ns tWP tCSH tCWL tDH 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 tRWL tWCH tWCS 10 MIN 9 50 -6 MAX MIN MAX UNITS 10,000 10 60 10,000 ns ns 84 11 30 104 14 40 ns ns ns 13 13 15 15 ns ns 8 38 0 10 45 0 ns ns ns 5 5 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS RAS# V IH V IL tCRP CAS# tCSH tRSH tCAS tRCD V IH V IL tAR tRAD tRAH tASR ADDR tRP V IH V IL tASC tCAH ROW COLUMN tRCS WE# ROW tRWD tCWD tCWL tRWL tAWD tWP V IH V IL tAA tRAC tCAC tDS tCLZ V DQ V IOH IOL VALID D OUT OPEN tOE OE# tDH VALID D IN tOD OPEN tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD MIN tCAS tCLZ tCRP tCSH tCWD tCWL tDH tDS 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 MIN -5 38 0 45 0 UNITS ns ns ns 0 42 0 49 ns ns tRAC tRAD 9 ns ns ns tRAH 9 50 tCAC tCAH -6 MAX 25 13 8 8 10,000 MAX 30 15 10 10 10,000 SYMBOL tOD MAX MIN MAX UNITS 0 12 12 0 15 15 ns ns 60 ns ns ns tOE tOEH tRAS tRCD 0 5 0 5 ns ns tRCS 38 28 45 35 ns ns tRSH 8 8 0 10 10 0 ns ns ns tRWD tRP tRWC tRWL tWP 11 -6 MIN 8 10 50 12 10,000 10 60 10,000 ns ns 11 0 30 14 0 40 ns ns ns 13 116 15 140 ns ns 67 13 5 79 15 5 ns ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM FAST-PAGE-MODE READ CYCLE tRASP tRP V IH V IL RAS# tCSH tCRP tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL CAS# tAR tRAD tRAH tASR V IH V IL ADDR tASC ROW tCAH tASC COLUMN tCAH COLUMN tRCS tCAH COLUMN tRCS tRCH tRCH ROW tRCS tRRH tRCH V IH V IL WE# tAA tRAC tAA tCPA tCAC tOFF tCLZ DQ tASC V IOH V IOL tOFF tCLZ OPEN tOE OE# tCAC tAA tCPA tCAC tOFF tCLZ VALID DATA tOD tOE VALID DATA tOD tOE VALID DATA tOD OPEN V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 38 0 tCLZ tCP 8 tCPA tCRP 5 38 tOD 0 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 10,000 15 10 10 0 10,000 10 28 tCSH -5 MAX 30 0 13 8 8 0 tCAS MIN 45 0 0 tCAC tCAH -6 MAX 25 35 5 45 12 0 15 UNITS ns ns ns SYMBOL tOE tOFF tPC MIN 0 20 ns ns tRAC tRAD 9 ns ns ns tRAH 9 50 11 ns ns tRCH ns ns tRP ns tRASP tRCD MIN 0 25 50 MAX 15 15 UNITS ns ns ns 60 ns ns 12 125,000 10 60 14 125,000 ns ns ns 0 0 0 0 ns ns tRRH 30 0 40 0 ns ns tRSH 13 15 ns tRCS 12 -6 MAX 12 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM FAST-PAGE-MODE EARLY WRITE CYCLE tRP tRASP RAS# V IH V IL tCSH tCRP CAS# tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH tASC COLUMN tCAH COLUMN tCWL tWCH tWCS tWCS tWCS tWP ROW tCWL tWCH tWP V IH V IL tWCR tDH tDS V DQ V IOH IOL OE# tCAH COLUMN tCWL tWCH tWP WE# tASC tDS VALID DATA tDH tDS VALID DATA tRWL tDH VALID DATA V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCP tCRP tCSH tCWL tDH tDS tPC 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 MIN 38 0 0 8 8 -6 MAX 10,000 MIN 45 0 0 10 10 -5 MAX 10,000 UNITS ns ns ns SYMBOL tRAD tRAH tRASP ns ns tRCD tRP 8 5 38 10 5 45 ns ns ns tRSH 8 8 10 10 ns ns tWCR 0 20 0 25 ns ns tWP tRWL tWCH tWCS 13 MIN 9 9 50 -6 MAX 125,000 MIN 12 10 60 MAX 125,000 UNITS ns ns ns 11 30 14 40 ns ns 13 13 8 15 15 10 ns ns ns 38 0 45 0 ns ns 5 5 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP tRP V IH V IL RAS# tCSH tCRP tCAS tRSH tPRWC tCAS tPC NOTE 1 tRCD tCP tCP tCAS tCP V IH V IL CAS# tAR tRAD tRAH tASR V IH V IL ADDR tASC ROW tCAH tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRWD tRCS tCWL tWP tAWD tCWD tWP tAWD tCWD V IH V IL WE# tAA tAA tRAC tDH tCAC tCLZ V IOH V IOL tAA tCPA tDS DQ tRWL tCWL tCWL tWP tAWD tCWD tDH tCAC tCLZ VALID D OUT OPEN tDS tCAC tCLZ VALID DIN VALID D OUT tOD VALID D IN VALID D OUT tOD tOE OE# tDH tCPA tDS VALID D IN OPEN tOD tOE tOE tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR -6 MAX MIN 25 tASR 38 0 0 45 0 0 tAWD 42 49 tASC tCAC tCAH 13 tCLZ 8 8 0 tCP 8 tCAS tCPA tCRP 10,000 -5 MAX UNITS 30 ns ns ns ns tOD tPC 8 20 ns ns tPRWC 47 ns ns ns tRAD ns ns tRCD 15 10 10 0 10,000 10 28 35 SYMBOL tRAH tRASP tRCS 5 45 35 ns ns ns tRP 10 10 ns ns tRWL tDH 8 8 tDS 0 0 ns tCWD tCWL MIN MAX UNITS 0 12 12 0 15 15 ns ns ns ns tRAC 5 38 28 tCSH MAX tOE tOEH tRSH tRWD tWP -6 MIN 10 25 56 50 9 9 50 125,000 12 10 60 60 ns ns 125,000 ns ns ns 11 0 14 0 ns ns 30 13 67 40 15 79 ns ns ns 13 5 15 5 ns ns NOTE: 1. tPC is for LATE WRITE only. 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP RAS# t RP V IH V IL t RSH t CSH t RCD t CRP CAS# t PC t CAS t CP t CAS t CP V IH V IL t AR t RAD t ASR ADDR V IH V IL t ASC t RAH ROW tASC t CAH COLUMN t CAH COLUMN ROW t CWL t RWL t WP t RCS t WCS WE# V IH V IL t CAC t CLZ DQ t WCH V OH V OL NOTE 1 t OFF t DS VALID DATA OPEN t DH VALID DATA t AA t RAC DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 38 0 0 tCAC 8 tCAS 8 0 8 tCP tCRP MIN -5 MAX 30 45 0 0 13 tCAH tCLZ -6 MAX 25 15 10 10,000 10 0 10 10,000 UNITS ns SYMBOL tOFF MIN 0 ns ns ns tPC tRAD 9 ns ns tRAH 9 50 ns ns ns tRCD 20 tRAC tRASP tRCS tRP -6 MAX 12 MIN 0 MAX 15 UNITS ns 60 ns ns ns 25 50 12 125,000 10 60 125,000 ns ns 11 0 30 14 0 40 ns ns ns 13 13 15 15 ns ns 5 38 5 45 ns ns tRSH 8 8 10 10 ns ns tWCH tDH tWCS 8 0 10 0 ns ns tDS 0 0 ns tWP 5 5 ns tCSH tCWL tRWL NOTE: 1. Do not drive data prior to tristate. 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) tRC tRAS RAS# tRP V IH V IL tCRP CAS# tRPC V IH V IL tASR ADDR tRAH V IH V IL ROW ROW V DQ V OH OL OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP tRAS tRP NOTE 1 tRAS V IH V IL RAS# tRPC tCP CAS# V IH V IL DQ V OH V OL tCSR tCSR tCHR OPEN tWRP WE# tRPC tCHR tWRH tWRP tWRH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR tCHR tCP tCRP tCSR tRAH MIN 0 -6 MAX MIN 0 -5 MAX UNITS ns SYMBOL tRAS 8 8 5 10 10 5 ns ns ns tRC 5 9 5 10 ns ns tWRH tRP tRPC tWRP MIN 50 -6 MAX 10,000 MIN 60 MAX 10,000 UNITS ns 84 30 104 40 ns ns 5 8 8 5 10 10 ns ns ns NOTE: 1. End of CBR REFRESH cycle. 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW) tRAS RAS# tRAS V IH V IL tCRP CASL#/CASH# tRP tRSH tRCD tCHR V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tAA tRAC tCAC tCLZ V DQx V IOH IOL tOFF OPEN VALID DATA OPEN t OE tOD t ORD OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR -6 MAX MIN 25 38 0 0 tCAC -5 MAX UNITS 30 ns ns ns ns 45 0 0 tRAD 0 0 8 10 tCHR 10 0 5 ns ns ns tRAS tCRP 8 0 5 tRP 50 11 30 tOD 0 ns tRSH 13 0 15 tRAH tRCD -6 MAX 12 12 MIN 0 0 50 tCAH 12 15 MIN ns ns tCLZ 13 SYMBOL tOE tOFF tORD tRAC 9 9 MAX 15 15 60 12 10 10,000 60 14 40 UNITS ns ns ns ns ns ns 10,000 15 ns ns ns ns NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP RAS# tRAS tRP tRAS V IH V IL tRPC tCP CAS# tCSR tRPC tCHR tCHR V IH V IL OPEN Q tWRP WE# tCSR tWRH tWRP tWRH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tCHD tCP tCSR tRASS tRP MIN 15 8 5 100 30 -6 MAX MIN 15 10 5 100 40 -5 MAX UNITS ns ns ns µs ns SYMBOL tRPC tRPS tWRH tWRP MIN 5 90 8 8 -6 MAX MIN 5 105 10 10 MAX UNITS ns ns ns ns NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used. 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM 24/26-PIN PLASTIC SOJ (300 mil) .679 (17.25) .673 (17.09) .305 (7.75) .299 (7.59) .340 (8.64) .330 (8.38) PIN #1 INDEX .050 (1.27) TYP .600 (15.24) TYP .037 (0.94) MAX DAMBAR PROTRUSION .032 (0.81) .026 (0.66) .112 (2.84) .102 (2.59) .105 (2.67) .090 (2.29) .142 (3.61) .132 (3.35) SEATING PLANE .020 (0.51) .015 (0.38) .040 (1.02) R .030 (0.76) NOTE: .275 (6.99) .260 (6.61) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 1. All dimensions in inches (millimeters) 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4 MEG x 4 FPM DRAM 24/26-PIN PLASTIC TSOP (300 mil) .678 (17.23) .672 (17.07) SEE DETAIL A 26 .367 (9.32) .359 (9.12) .302 (7.67) .298 (7.57) 1 13 .007 (0.18) .005 (0.13) PIN #1 INDEX .050 (1.27) TYP .020 (0.50) .012 (0.30) .010 (0.25) .004 (0.10) .047 (1.20) MAX SEATING PLANE .008 (0.20) .002 (0.05) DETAIL A NOTE: GAGE PLANE .024 (0.60) .016 (0.40) .0315 (0.80) TYP 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 4 Meg x 4 FPM DRAM D49_5V.p65 – Rev. 5/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc.