TPS717xx www.ti.com.................................................................................................................................................. SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009 Low Noise, High-Bandwidth PSRR Low-Dropout 150mA Linear Regulator FEATURES DESCRIPTION 1 • 150mA Low-Dropout Regulator with Enable • Low IQ: 45µA (typical) • Available in Multiple Output Versions: – Fixed Output with Voltages from 0.9V to 5.0V Using Innovative Factory EEPROM Programming – Adjustable Output Voltage from 0.9V to 6.2V • Ultra-High PSRR: – 70dB at 1kHz, 67dB at 100kHz and 45dB at 1MHz • Low Noise: 30µV typical (100Hz to 100kHz) • Stable with a 1.0µF Ceramic Capacitor • Excellent Load/Line Transient Response • 3% Overall Accuracy (over Load/Line/Temp) • Over-Current and Over-Temperature Protection • Very Low Dropout: 170mV Typical at 150mA • Small SC70-5, 2mm x 2mm SON-6, and 1.5mm × 1.5mm SON-6 Packages 23 The TPS717xx family of low-dropout (LDO), low-power linear regulators offers very high power supply rejection (PSRR) while maintaining very low 45µA ground current in an ultra-small, five-pin SC70 package. The family uses an advanced BiCMOS process and a PMOSFET pass device to achieve fast start-up, very low noise, excellent transient response, and excellent PSRR performance. The TPS717xx is stable with a 1.0µF ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations. It is fully specified from TJ = –40°C to +125°C and is offered in a small SC70-5 package, a 2mm × 2mm SON-6 package with a thermal pad, and a 1.5mm × 1.5mm SON package, which are ideal for small form factor portable equipment such as wireless handsets and PDAs. VIN IN 1 mF Ceramic EN GND VEN Typical Application Circuit for Fixed Voltage Versions Mobile Phone Handsets Wireless LAN, Bluetooth® PDAs and Smartphones 80 GND 2 EN 3 5 OUT NR/FB 4 TPS717xx DRV 2mm x 2mm SON (TOP VIEW) OUT 1 NR/FB 2 GND 3 6 GND 10mA 60 PSRR (dB) 1 150mA 70 TPS717xx DCK SC70-5 PACKAGE (TOP VIEW) IN 1mF Ceramic NR 0.01mF (Optional) APPLICATIONS • • • VOUT OUT TPS717xx TPS717xx DSE 1.5mm x 1.5mm SON (TOP VIEW) OUT 1 6 IN GND 2 5 N/C NR/FB 3 4 EN N/C 4 EN 40 75mA 30 20 (1) COUT = 1mF CNR = 10nF 10 0 10 IN 5 50 (1) 100 1k 100k 10k Frequency (Hz) 1M 10M NOTE: (1) N/C = Not connected. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2009, Texas Instruments Incorporated TPS717xx SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009.................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOUT (2) PRODUCT TPS717xxyyyz (1) (2) XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable). YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Output voltages from 0.9V to 5.0V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) Over operating temperature range (unless otherwise noted). All voltages are with respect to GND. PARAMETER TPS717xx UNIT Input voltage range, VIN –0.3 to +7.0 V Feedback input voltage range, VFB, VNR –0.3 to +3.6 V –0.3 to VIN + 0.3V (2) V –0.3 to +7.0 V Enable voltage range, VEN Output voltage range, VOUT Maximum output current, IOUT Internally limited Continuous total power dissipation, PDISS See Dissipation Ratings Table Junction temperature range, TJ –55 to +150 Storage junction temperature range, TSTG –55 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) (2) °C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. VEN absolute maximum rating is VIN + 0.3V or +7.0V, whichever is greater. DISSIPATION RATINGS PACKAGE RθJC RθJA DERATING FACTOR ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C (1) DCK 165°C/W 395°C/W 2.5mW/°C 250mW 140mW 100mW High-K (2) DCK 165°C/W 315°C/W 3.2mW/°C 320mW 175mW 130mW Low-K (1) DRV 20°C/W 140°C/W 7.1mW/°C 715mW 395mW 285mW High-K (2) DRV 20°C/W 65°C/W 15.4mW/°C 1540mW 845mW 615mW (2) DSE — 206°C/W 4.85mW/°C 485mW 269mW 194mW BOARD Low-K High-K (1) (2) 2 The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board. The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated TPS717xx www.ti.com.................................................................................................................................................. SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA, VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS VIN Input voltage range (1) VFB Internal reference (TPS71701) VOUT VOUT MIN TYP 2.5 0.790 0.800 MAX UNIT 6.5 V 0.810 V V Output voltage range (TPS717xx) 0.9 5.0 Output voltage range (TPS71701) 0.9 6.5 – VDO ±2.5 V Output accuracy Nominal TJ = +25°C mV Output accuracy (VOUT < 1.0V) Over VIN, IOUT, Temp (2) VOUT + 0.5V ≤ VIN ≤ 6.5V 0mA ≤ IOUT ≤ 150mA –30 +30 mV Output accuracy (VOUT ≥ 1.0V) Over VIN, IOUT, Temp (2) VOUT + 0.5V ≤ VIN ≤ 6.5V 0mA ≤ IOUT ≤ 150mA –3.0 +3.0 % VOUT(NOM) + 0.5V ≤ VIN ≤ 6.5V, IOUT = 5mA 125 µV/V Load regulation 0mA ≤ IOUT ≤ 150mA 120 µV/mA Dropout voltage (3) (VIN = VOUT(NOM) – 0.1V) IOUT = 150mA 170 300 mV ICL (Fixed) Output current limit (fixed output) VOUT = 0.9 × VOUT(NOM) 200 325 575 mA ICL (Adjustable) Output current limit (TPS71701) VOUT = 0.9 × VOUT(NOM) 200 325 575 mA IOUT = 0.1mA 45 80 µA IOUT = 150mA 100 VEN ≤ 0.4V, 2.5V ≤ VIN < 4.5V, TJ = –40°C to +85°C 0.20 VEN ≤ 0.4V, 4.5V ≤ VIN ≤ 6.5V, TJ = –40°C to +85°C 0.90 ΔVOUT/ ΔVIN Line regulation ΔVOUT/ ΔIOUT VDO IGND ISHDN IFB PSRR VN TSTR Ground pin current Shutdown current (IGND) Feedback pin current (TPS71701) Power-supply rejection ratio VIN = 3.8V, VOUT = 2.8V, IOUT = 150mA Output noise voltage BW = 100Hz to 100kHz, VIN = 3.8V, VOUT = 2.8V, IOUT = 10mA Startup time VOUT = 90% VOUT(NOM), RL = 19Ω, COUT = 1.0µF VEN(HI) Enable high (enabled) VEN(LO) Enable low (shutdown) IEN(HI) UVLO (1) (2) (3) (4) (1) 0.02 1.0 µA dB 70 dB f = 10kHz 67 dB f = 100kHz 67 dB f = 1MHz 45 dB CNR = none (fixed output, TPS71701) 95 × VOUT µVRMS 25 × VOUT µVRMS CNR = 0.01µF 12.5 × VOUT µVRMS CNR = 0.1µF 11.5 × VOUT µVRMS CNR = 0.001µF 0.9V ≤ VOUT ≤ 1.6V, CNR = 0.001µF 0.700 1.6V < VOUT < VMAX, CNR = 0.01µF VIN ≤ 5.5V 5.5V < VIN ≤ 6.5V VIN rising Hysteresis VIN falling Operating junction temperature µA f = 1kHz Under-voltage lockout TJ µA 70 EN = 6.5V Thermal shutdown temperature 1.5 f = 100Hz Enable pin current, enabled TSD µA ms 0.160 ms 1.2 6.5 (4) V 1.25 6.5 V 0 0.4 V 0.02 1.0 µA 2.45 2.49 2.41 V 150 mV Shutdown, temperature increasing +160 °C Reset, temperature decreasing +140 –40 °C +125 °C Minimum VIN = VOUT + VDO or 2.5V, whichever is greater. Does not include external resistor tolerances. VDO is not measured for devices with VOUT(NOM) < 2.6V because minimum VIN = 2.5V. Maximum VEN(HI) = VIN + 0.3 or 6.5V, whichever is smaller. Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS717xx SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009.................................................................................................................................................. www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAMS OUT IN 2.5mA Current Limit EN Thermal Shutdown UVLO Quickstart 1.20V Bandgap VOUT > 1.6V NR 360kW 0.8V 250kW VOUT £ 1.6V 640kW GND Figure 1. Fixed Voltage Versions OUT IN Current Limit EN Thermal Shutdown 3.3MW UVLO 1.20V Bandgap 360kW FB 0.8V 250kW 640kW GND Figure 2. Adjustable Voltage Version 4 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated TPS717xx www.ti.com.................................................................................................................................................. SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009 PIN CONFIGURATIONS TPS717xx DCK SC70-5 PACKAGE (TOP VIEW) IN 1 GND 2 EN 3 5 4 TPS717xx DRV 2mm x 2mm SON (TOP VIEW) OUT NR/FB OUT 1 NR/FB 2 GND 3 GND TPS717xx DSE 1.5mm x 1.5mm SON (TOP VIEW) 6 IN 5 N/C 4 EN (1) OUT 1 6 IN GND 2 5 N/C NR/FB 3 4 EN (1) NOTE: (1) N/C = Not connected. Table 1. PIN DESCRIPTIONS TPS717xx NAME SC70 (DCK) 2×2 SON (DRV) 1.5×1.5 SON (DSE) IN 1 6 6 Input to the device. GND 2 3 2 Ground. EN 3 4 4 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into standby mode, thereby reducing operating current. NR 4 2 3 Fixed voltage versions only. An external capacitor connected to this terminal bypasses noise generated by the internal bandgap, lowering output noise. FB 4 2 3 Adjustable voltage version only. The voltage at this pin is fed to the error amplifier. A resistor divider from OUT to FB sets the output voltage when in regulation. OUT 5 1 1 This is the regulated output voltage. A small capacitor is needed from this pin to ground to assure stability; a 1.0µF ceramic capacitor is adequate. NC – 5 5 Not connected. This pin can be tied to ground to improve thermal dissipation. Copyright © 2006–2009, Texas Instruments Incorporated DESCRIPTION Submit Documentation Feedback 5 TPS717xx SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA, VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V. Typical values are at TJ = +25°C. LOAD REGULATION LOAD REGULATION UNDER LIGHT LOADS 50 50 TJ = -40°C TJ = +25°C TJ = +85°C TJ = +125°C 40 30 30 20 DVOUT (mV) DVOUT (mV) 20 10 0 -10 10 0 -10 -20 -20 -30 -30 -40 -40 -50 -50 0 50 0 150 100 1 3 2 4 IOUT (mA) IOUT (mA) Figure 3. Figure 4. LINE REGULATION IOUT = 5mA LINE REGULATION IOUT = 150mA 1.0 5 3.0 TJ = -40°C TJ = +25°C TJ = +85°C TJ = +125°C 0.8 0.6 TJ = -40°C TJ = +25°C TJ = +85°C TJ = +125°C 2.0 1.0 DVOUT (%) 0.4 DVOUT (%) TJ = -40°C TJ = +25°C TJ = +85°C TJ = +125°C 40 0.2 0 -0.2 0 -1.0 -0.4 -0.6 -2.0 -0.8 -3.0 -1.0 2.5 3.5 4.5 VIN (V) 5.5 6.5 2.5 3.5 4.5 VIN (V) Figure 5. Figure 6. OUTPUT VOLTAGE vs TEMPERATURE DROPOUT VOLTAGE vs OUTPUT CURRENT TJ = +125°C 1.5 200 IOUT = 5mA 0.5 0 -0.5 IOUT = 100mA -1.0 VDO (mV) 1.0 DVOUT (%) 6.5 250 2.0 150 TJ = +85°C 100 TJ = +25°C 50 IOUT = 150mA TJ = -40°C -1.5 0 -2.0 -40 -25 -10 5 20 35 50 TJ (°C) Figure 7. 6 5.5 Submit Documentation Feedback 65 80 95 110 125 0 50 100 150 IOUT (mA) Figure 8. Copyright © 2006–2009, Texas Instruments Incorporated TPS717xx www.ti.com.................................................................................................................................................. SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA, VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V. Typical values are at TJ = +25°C. DROPOUT VOLTAGE vs TEMPERATURE GROUND PIN CURRENT vs INPUT VOLTAGE 300 150 VOUT = 2.8V IOUT = 150mA 250 120 IOUT = 150mA 150 IGND (mA) VDO (mV) 200 90 60 100 30 50 IOUT = 10mA 0 IOUT = 100mA 0 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 95 110 125 3.5 2.5 4.5 VIN (V) 5.5 Figure 9. Figure 10. GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE (ENABLED) 150 150 120 120 90 90 6.5 IGND (mA) IGND (mA) IOUT = 150mA 60 30 30 0 IOUT = 100mA 0 50 0 100 150 IOUT (mA) 35 50 TJ (°C) Figure 11. Figure 12. GROUND PIN CURRENT vs TEMPERATURE (DISABLED) CURRENT LIMIT vs INPUT VOLTAGE 4 65 80 95 110 125 TJ = -40°C 500 IGND (mA) 2 20 600 VEN = 0.4V 3 5 -40 -25 -10 5 IGND (mA) 60 TJ = +25°C TJ = +85°C 400 VIN = 4.5V VIN = 6.5V 300 1 TJ = +125°C VIN = 3.3V 0 200 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 Figure 13. Copyright © 2006–2009, Texas Instruments Incorporated 95 110 125 2.5 3.5 4.5 VIN (V) 5.5 6.5 Figure 14. Submit Documentation Feedback 7 TPS717xx SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA, VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V. Typical values are at TJ = +25°C. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 1V) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 0.5V) 80 80 150mA 70 10mA 60 50 PSRR (dB) PSRR (dB) 60 40 75mA 30 20 40 30 COUT = 1mF CNR = 10nF 0 10 100 1k 100k 10k Frequency (Hz) 1M 10M 10 100 1k 100k 10k Frequency (Hz) 10M 1M Figure 15. Figure 16. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 0.25V) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 1V) 80 80 70 10mA 60 10mA 60 75mA PSRR (dB) PSRR (dB) 50 10 0 50 75mA 150mA 20 COUT = 1mF CNR = 10nF 10 70 10mA 70 40 150mA 30 20 50 40 150mA 30 20 COUT = 1mF CNR = 10nF 10 COUT = 10mF CNR = 10nF 10 0 0 10 100 1k 100k 10k Frequency (Hz) 1M 10M 10 100 1k 100k 10k Frequency (Hz) 10M 1M Figure 17. Figure 18. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 0.25V) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 1V) 80 80 70 70 10mA 60 50 50 PSRR (dB) PSRR (dB) 10mA 60 40 150mA 30 20 150mA 30 20 COUT = 10mF CNR = 10nF 10 0 COUT = 10mF CNR = 0nF 10 0 10 100 1k 100k 10k Frequency (Hz) Figure 19. 8 40 Submit Documentation Feedback 1M 10M 10 100 1k 100k 10k Frequency (Hz) 1M 10M Figure 20. Copyright © 2006–2009, Texas Instruments Incorporated TPS717xx www.ti.com.................................................................................................................................................. SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA, VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V. Typical values are at TJ = +25°C. POWER-SUPPLY RIPPLE REJECTION vs (VIN – VOUT) 80 POWER-SUPPLY RIPPLE REJECTION vs (VIN – VOUT) 80 1kHz 70 10kHz 100kHz 50 1MHz 40 30 20 60 40 1MHz 30 IOUT = 75mA COUT = 1mF CNR = 10nF 10 0 0 0 80 0.5 1.0 1.5 2.0 2.5 VIN - VOUT (V) 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 VIN - VOUT (V) 3.0 3.5 Figure 21. Figure 22. POWER-SUPPLY RIPPLE REJECTION vs (VIN – VOUT) OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT CURRENT 16 60 10kHz 50 40 1MHz 30 20 IOUT = 150mA COUT = 1mF CNR = 10nF 10 0 Output Noise Density (mV/ÖHz) 1kHz 100kHz 70 COUT = 1mF CNR = 10nF IOUT = 150mA 14 4.0 12 IOUT = 10mA 10 8 6 4 2 0 0 0.5 1.0 1.5 2.0 2.5 VIN - VOUT (V) 3.0 3.5 4.0 Figure 24. OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT CAPACITANCE OUTPUT SPECTRAL NOISE DENSITY vs NOISE REDUCTION IOUT = 10mA CNR = 10nF COUT = 10mF 10 COUT = 1mF 6 4 2 0 100 100k Figure 23. 14 8 10k 1k Frequency (Hz) 16 12 100 10k 1k 100k Output Spectral Noise Density (mV/ÖHz) PSRR (dB) 50 20 IOUT = 10mA COUT = 1mF CNR = 10nF 10 10kHz 100kHz PSRR (dB) PSRR (dB) 60 Output Noise Density (mV/ÖHz) 1kHz 70 30 IOUT = 10mA COUT = 1mF 25 20 15 10 CNR = 0nF CNR = 10nF CNR = 1nF CNR = 100nF 5 0 100 10k 1k Frequency (Hz) Frequency (Hz) Figure 25. Figure 26. Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 100k 9 TPS717xx SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA, VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V. Typical values are at TJ = +25°C. TOTAL OUTPUT NOISE vs NOISE REDUCTION 300 TOTAL OUTPUT NOISE vs OUTPUT CAPACITANCE 50 IOUT = 10mA COUT = 1mF 270 40 Total Noise (mVRMS) 240 Total Noise (mVRMS) VOUT = 2.8V, CNR = 10nF VOUT = 1.3V, CNR = 1nF 45 210 180 150 120 90 35 30 25 20 15 60 10 30 5 0 0 0 CNR (nF) 10 15 COUT (mF) Figure 27. Figure 28. LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE 10 1 5 0 100 20 25 VIN = 3.3V COUT = 1mF 10mV/div VOUT dVIN = 1V/ms dt 50mV/div COUT = 1mF VOUT 6.5V 3.3V VIN IOUT 100ms/div Figure 29. Figure 30. TURN-ON RESPONSE POWER-UP/POWER-DOWN COUT = 10mF 1V/div VOUT VIN IOUT = 150mA 6 5 VOUT 4 3 VOUT 2 1V/div 1 6.5V VIN 0 0V 50ms/div Figure 31. 10 0mA 100ms/div COUT = 1mF 4V/div 40mV/div Volts 1V/div 150mA Submit Documentation Feedback 50ms/div Figure 32. Copyright © 2006–2009, Texas Instruments Incorporated TPS717xx www.ti.com.................................................................................................................................................. SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009 APPLICATION INFORMATION The TPS717xx belongs to a family of new generation LDO regulators that use innovative circuitry to achieve ultra-wide bandwidth and high loop gain, resulting in extremely high PSRR (up to 1MHz) at very low headroom (VIN – VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise generated by the bandgap reference and to improve PSRR while a quick-start circuit fast-charges this capacitor. These features, combined with low noise, enable, low ground pin current, and ultra-small packaging, make this part ideal for portable applications. This family of regulators offers sub-bandgap output voltages, current limit and thermal protection, and is fully specified from –40°C to +125°C. For the adjustable version (TPS71701), the NR pin is replaced with a feedback (FB) pin. The voltage on this pin sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be calculated for any voltage using the formula given in Equation 1: Figure 33 shows the basic circuit connections for the fixed voltage options. Figure 34 gives the connections for the adjustable output version (TPS71701). Note that the NR pin is not available on the adjustable version. Table 2. Sample 1% Resistor Values for Common Output Voltages Optional 1.0mF input capacitor. May improve source impedance, noise or PSRR. VIN IN VOUT OUT TPS717xx EN GND 1mF Ceramic NR VEN Optional 1.0mF input capacitor. May improve source impedance, noise or PSRR. IN TPS71701 EN VOUT OUT GND R1 FB 1m F Ceramic R2 VEN (R1 + R2 ) x 0.800, R2 ~ 320kW R2 (1) The value of R2 directly impacts the stability of the device and should be chosen at approximately 160kΩ or 320kΩ. Sample resistor values for common output voltages are shown in Table 2. VOUT R1 R2 1.0 80.6kΩ 324kΩ 1.2 162kΩ 324kΩ 1.5 294kΩ 332kΩ 1.8 402kΩ 324kΩ 2.5 665kΩ 316kΩ 3.3 1.02MΩ 324kΩ 5.0 1.74MΩ 332kΩ Input and Output Capacitor Requirements Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1µF to 1.0µF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor will counteract reactive input sources and improve transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1µF input capacitor may be necessary to ensure stability. Optional 0.01mF bypass capacitor to reduce output noise and increase PSRR. Figure 33. Typical Application Circuit (Fixed Voltage Versions) VIN VOUT = The TPS717xx is designed to be stable with standard ceramic capacitors of values 1.0µF or larger. X5Rand X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be <1.0Ω. The TPS717xx implements an innovative internal compensation circuit that does not require a feedback capacitor across R2 for stability. A feedback capacitor should not be used for this device. Figure 34. Typical Application Circuit (Adjustable Voltage Version) Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS717xx SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009.................................................................................................................................................. www.ti.com Output Noise Dropout Voltage In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS717xx, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01µF (minimum) noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that gives 2.5µA of divider current has the same noise performance as a fixed voltage version. The TPS717xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO will approximately scale with output current because the PMOS device behaves like a resistor in dropout. Equation 2 approximates the total noise referred to the feedback point (FB pin) when CNR = 0.01µF, total noise is approximately given by Equation 2: mVRMS x VOUT VN = 11.5 V (2) Board Layout Recommendations to Improve PSRR and Noise Performance To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. Internal Current Limit The TPS717xx internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time. The PMOS pass element in the TPS717xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 21 through Figure 23 in the Typical Characteristics section. Startup Fixed voltage versions of the TPS717xx use a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see Functional Block Diagrams, Figure 1). This circuit allows the combination of very low output noise and fast start-up times. The NR pin is high impedance, so a low leakage CNR capacitor must be used; most ceramic capacitors are appropriate in this configuration. Note that for fastest startup, VIN should be applied first, then the enable pin (EN) driven high. If EN is tied to IN, startup will be somewhat slower. Refer to Figure 31 in the Typical Characteristics section. The quick-start switch is closed for approximately 135µs. To ensure that CNR is fully charged during the quick-start time, a 0.01µF or smaller capacitor should be used. For output voltages below 1.6V, a voltage divider on the bandgap reference voltage is employed to optimize output regulation performance for lower output voltages. This configuration results in an additional resistor in the quick-start path and combined with the noise reduction capacitor (CNR) results in slower start-up times for output voltages below 1.6V. Equation 3 approximates the start-up time as a function of CNR for output voltages below 1.6V: ms tSTART = 160ms + (540 x CNRnF)ms nF (3) Shutdown The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN. 12 Submit Documentation Feedback Transient Response As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. Copyright © 2006–2009, Texas Instruments Incorporated TPS717xx www.ti.com.................................................................................................................................................. SBVS068G – FEBRUARY 2006 – REVISED APRIL 2009 Under-Voltage Lock-Out (UVLO) The TPS717xx utilizes an under-voltage lock-out circuit to keep the output shut off until internal circuitry is operating properly. The UVLO circuit has a de-glitch feature so that it typically ignores undershoot transients on the input if they are less than 50µs duration. Minimum Load The TPS717xx is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS717xx employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. THERMAL INFORMATION Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least Copyright © 2006–2009, Texas Instruments Incorporated +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS717xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS717xx into thermal shutdown will degrade device reliability. Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC lowand high-K boards are given in the Dissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 4: P D + ǒVIN * VOUTǓ I OUT (4) Package Mounting Solder pad footprint recommendations for the TPS717xx are available from the Texas Instruments web site at www.ti.com. Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS71701DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BMT TPS71701DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BMT TPS71701DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BMT TPS71701DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BMT TPS71709DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FY TPS71709DSERG4 ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FY TPS71709DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FY TPS71709DSETG4 ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FY TPS71710DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMU TPS71710DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMU TPS71710DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMU TPS71710DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMU TPS71710DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BMU TPS71710DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BMU TPS71710DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BMU TPS71710DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BMU TPS71711DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BRL Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS71711DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BRL TPS71711DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BRL TPS71711DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BRL TPS71712DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CKE TPS71712DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CKE TPS71712DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CKE TPS71712DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CKE TPS71713DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMW TPS71713DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMW TPS71713DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMW TPS71713DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMW TPS71715DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CAA TPS71715DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CAA TPS71715DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CAA TPS71715DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CAA TPS717185DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KB TPS717185DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 KB TPS71718DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMX Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS71718DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMX TPS71718DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMX TPS71718DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMX TPS71718DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 G6 TPS71718DSERG4 ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 G6 TPS71718DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 G6 TPS71718DSETG4 ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 G6 TPS71719DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CCZ TPS71719DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CCZ TPS71719DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CCZ TPS71719DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CCZ TPS71721DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NXL TPS71721DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NXL TPS71725DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CAF TPS71725DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CAF TPS71725DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CAF TPS71725DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CAF TPS71726DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BRK Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS71726DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BRK TPS71726DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BRK TPS71726DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BRK TPS71727DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BSC TPS71727DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BSC TPS71727DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BSC TPS71727DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BSC TPS71727DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KU TPS71727DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 KU TPS717285DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BRJ TPS717285DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BRJ TPS717285DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BRJ TPS717285DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BRJ TPS71728DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMZ TPS71728DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMZ TPS71728DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMZ TPS71728DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BMZ TPS71728DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FU Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS71728DSERG4 ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FU TPS71728DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FU TPS71728DSETG4 ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FU TPS71729DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CJR TPS71729DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CJR TPS71729DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CJR TPS71729DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CJR TPS71730DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNA TPS71730DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNA TPS71730DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNA TPS71730DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNA TPS71733DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNB TPS71733DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNB TPS71733DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNB TPS71733DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNB TPS71733DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNB TPS71733DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNB TPS71733DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNB Addendum-Page 5 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS71733DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 BNB TPS71733DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FV TPS71733DSERG4 ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FV TPS71733DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FV TPS71733DSETG4 ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FV TPS71745DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GL TPS71745DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GL TPS71750DSER ACTIVE WSON DSE 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PD TPS71750DSET ACTIVE WSON DSE 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 6 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS71709, TPS71750 : • Automotive: TPS71709-Q1, TPS71750-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 7 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS71701DCKR Package Package Pins Type Drawing SC70 DCK 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71701DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71709DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71709DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71710DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71710DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71710DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS71710DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS71711DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71711DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71712DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71712DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71713DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71713DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71715DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71715DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS717185DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS717185DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS71718DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71718DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71718DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71718DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71719DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71719DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71721DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71721DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71725DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71725DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71726DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71726DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71727DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71727DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71727DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71727DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS717285DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS717285DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71728DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71728DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71728DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71728DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71729DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71730DCKR SC70 DCK 5 3000 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71730DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71733DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TPS71733DCKT SC70 DCK 5 250 179.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3 TPS71733DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS71733DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS71733DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71733DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71745DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71745DSER WSON DSE 6 3000 330.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2 TPS71745DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2 TPS71745DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71750DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TPS71750DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS71701DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71701DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71709DSER WSON DSE 6 3000 203.0 203.0 35.0 TPS71709DSET WSON DSE 6 250 203.0 203.0 35.0 TPS71710DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71710DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71710DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS71710DRVT SON DRV 6 250 203.0 203.0 35.0 TPS71711DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71711DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71712DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71712DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71713DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71713DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71715DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71715DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS717185DSER WSON DSE 6 3000 203.0 203.0 35.0 TPS717185DSET WSON DSE 6 250 203.0 203.0 35.0 TPS71718DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71718DCKT SC70 DCK 5 250 203.0 203.0 35.0 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS71718DSER WSON DSE 6 3000 203.0 203.0 35.0 TPS71718DSET WSON DSE 6 250 203.0 203.0 35.0 TPS71719DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71719DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71721DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71721DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71725DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71725DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71726DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71726DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71727DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71727DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71727DSER WSON DSE 6 3000 203.0 203.0 35.0 TPS71727DSET WSON DSE 6 250 203.0 203.0 35.0 TPS717285DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS717285DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71728DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71728DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71728DSER WSON DSE 6 3000 203.0 203.0 35.0 TPS71728DSET WSON DSE 6 250 203.0 203.0 35.0 TPS71729DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71730DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71730DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71733DCKR SC70 DCK 5 3000 203.0 203.0 35.0 TPS71733DCKT SC70 DCK 5 250 203.0 203.0 35.0 TPS71733DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS71733DRVT SON DRV 6 250 203.0 203.0 35.0 TPS71733DSER WSON DSE 6 3000 203.0 203.0 35.0 TPS71733DSET WSON DSE 6 250 203.0 203.0 35.0 TPS71745DSER WSON DSE 6 3000 203.0 203.0 35.0 TPS71745DSER WSON DSE 6 3000 367.0 367.0 35.0 TPS71745DSET WSON DSE 6 250 210.0 185.0 35.0 TPS71745DSET WSON DSE 6 250 203.0 203.0 35.0 TPS71750DSER WSON DSE 6 3000 203.0 203.0 35.0 TPS71750DSET WSON DSE 6 250 203.0 203.0 35.0 Pack Materials-Page 4 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