19-1100; Rev 0; 6/96 KIT ATION EVALU BLE A IL A V A 8-Bit, 300Msps Flash ADC The MAX1125 is a monolithic, flash analog-to-digital converter (ADC) capable of digitizing a 2V analog input signal into 8-bit digital words at a typical 300Msps update rate. For most applications, no external sample-and-hold is required for accurate conversion due to the device's narrow aperture time, wide bandwidth, and low input capacitance. A single standard -5.2V power supply is required to operate the MAX1125, with nominal 2.2W power dissipation. A special decoding scheme reduces metastable errors to 1LSB. The part is packaged in a 42-pin ceramic sidebraze that is pin compatible with the CX20116 and CX41396D. The surface-mount 44-pin CERQUAD package allows access to additional reference ladder taps, an overrange bit, and a data-ready output. The pincompatible 150Msps MAX1114 is also available. ________________________Applications Digital Oscilloscopes Transient Capture Radar, EW, ECM Direct RF Down-Conversion Medical Electronics Ultrasound, CAT Instrumentation D8 (MSB) D7 D6 D5 D4 D3 D2 D1 D0 (LSB) DREADY DGND 44 43 42 41 40 39 38 37 36 35 34 DGND 1 33 AGND AGND 2 32 VEE VEE 3 31 LINV MINV 4 30 N.C. CLK 5 29 DRINV CLK 6 VEE MAX1125 Metastable Errors Reduced to 1LSB 10pF Input Capacitance 210MHz Input Bandwidth 300Msps Conversion Rate 2.2W Typical Power Dissipation Single -5.2V Supply ______________Ordering Information PART TEMP. RANGE PIN-PACKAGE INL (LSBs) MAX1125AIDO -20°C to +85°C 42 Ceramic SB ±0.75 MAX1125BIDO -20°C to +85°C 42 Ceramic SB MAX1125AIBH -20°C to +85°C 44 CERQUAD MAX1125BIBH -20°C to +85°C 44 CERQUAD ±1 ±0.75 ±1 Functional Diagram appears at end of data sheet. ____Pin Configurations (continued) TOP VIEW _________________Pin Configurations TOP VIEW ____________________________Features ♦ ♦ ♦ ♦ ♦ ♦ VEE 1 42 N.C. N.C. 2 41 VRTF LINV 3 40 N.C. VEE 4 AGND 5 38 VEE DGND 6 37 N.C. DO (LSB) 7 36 N.C. D1 8 35 AGND D2 9 34 VIN MAX1125 39 VEE D3 10 33 AGND D4 11 32 VR2 D5 12 31 AGND D6 13 30 VIN 29 AGND D7 (MSB) 14 28 N.C. DGND 15 28 N.C. 7 27 VEE AGND 16 27 N.C. AGND 8 26 AGND AGND VEE 22 VR3 21 AGND 20 VIN 19 AGND 18 VR2 17 AGND 16 23 VRTF VIN 15 VRBF 11 AGND 14 24 VRTS VEE 12 25 AGND VR1 13 9 VRBS 10 VEE 17 26 VEE MINV 18 25 VEE N.C. 19 24 N.C. CLK 20 23 VRBF CLK 21 22 N.C. Ceramic SB CERQUAD ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX1125 _______________General Description MAX1125 8-Bit, 300Msps Flash ADC ABSOLUTE MAXIMUM RATINGS Negative Supply Voltage (VEE TO GND) ..............-7.0V to +0.5V Ground Voltage Differential ...................................-0.5V to +0.5V Analog Input Voltage ...............................................VEE to +0.5V Reference Input Voltage ..........................................VEE to +0.5V Digital Input Voltage ................................................VEE to +0.5V Reference Current VRTF to VRBF ........................................25mA Digital Output Current ...........................................0mA to -30mA Operating Temperature Range ...........................-25°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec). ............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VEE = -5.2V, RSOURCE = 50Ω, VRBF = -2.00V, VR2 = -1.00V, VRTF = 0.00V, fCLK = 150MHz, 50% Duty Cycle, TA = TMIN to TMAX, unless otherwise noted.) TEST LEVEL MIN Integral Linearity VI -0.75 Differential Linearity VI -0.75 PARAMETER CONDITIONS MAX1125A TYP MAX MIN MAX1125B TYP MAX UNITS DC ACCURACY No Missing Codes ±0.60 +0.75 -0.95 +0.75 -0.95 Guaranteed ±0.80 +0.95 LSB +0.95 LSB Guaranteed ANALOG INPUT Offset Error VRT IV -30 +30 -30 +30 mV Offset Error VRB IV -30 +30 -30 +30 mV Input Voltage Range VI -2.0 0.0 -2.0 0.0 Input Capacitance Over full input range V 10 10 V pF Input Resistance V 15 Input Current VI 250 15 Input Slew Rate V 1,000 1,000 V/µs 500 250 kΩ 500 µA Large Signal Bandwidth VIN = full scale V 210 210 MHz Small Signal Bandwidth IN = 500mVp-p V 335 335 MHz REFERENCE INPUT Ladder Resistance VI Reference Bandwidth V 100 200 300 100 10 200 300 Ω 10 MHz 300 Msps TIMING CHARACTERISTICS Maximum Sample Rate VI Clock to Data Delay V 2.4 2.4 ns Output Delay TEMPCO V 2 2 ps/°C CLK-to-Data Ready Delay (tD) V 2.0 2.0 ns Aperture Jitter V 5 5 ps Acquisition Time V 1.5 1.5 ns 2 250 300 250 _______________________________________________________________________________________ 8-Bit, 300Msps Flash ADC (VEE = -5.2V, RSOURCE = 50Ω, VRBF = -2.00V, VR2 = -1.00V, VRTF = 0.00V, fCLK = 150MHz, 50% Duty Cycle, TA = TMIN to TMAX, unless otherwise noted.) TEST LEVEL MIN FIN = 3.58MHz VI 45 47 44 46 FIN = 100MHz VI 39 42 38 41 FIN = 3.58MHz VI -48 -52 -46 -50 FIN = 100MHz VI -40 -43 -39 -42 FIN = 3.58MHz VI 44 46 42 44 FIN = 100MHz VI 37 39 35 37 Digital Input High Voltage (MINV, LINV) VI -1.1 -0.7 -1.1 -0.7 V Digital Input Low Voltage (MINV, LINV) VI -2.0 -1.5 -2.0 -1.5 V Clock Synchronous Input Currents V Clock Low Width, TPWL VI 2 1.8 Clock High Width, TPWH VI 2 1.8 -1.1 PARAMETER CONDITIONS MAX1114A TYP MAX MIN MAX1114B TYP MAX UNITS DYNAMIC PERFORMANCE Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-Noise and Distortion (SINAD) dB dB dB DIGITAL INPUTS 40 40 µA 2 1.8 ns 2 1.8 ns DIGITAL OUTPUTS Digital Output High Voltage 50Ω to -2V VI Digital Output Low Voltage 50Ω to -2V VI -1.1 V -1.5 -1.5 V 2.4 Supply Current TA = +25 °C I 425 550 425 550 mA Power Dissipation TA = +25 °C I 2.2 2.9 2.2 2.9 W TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed; therefore, Tj = TC = TA. TEST LEVEL 2.4 V POWER-SUPPLY REQUIREMENTS ns TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25°C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characterization data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25°C. Parameter is guaranteed over specified temperature range. _______________________________________________________________________________________ 3 MAX1125 ELECTRICAL CHARACTERISTICS (continued) __________________________________________Typical Operating Characteristics fs = 250Msps 48 65 46 60 44 42 fs = 250Msps 70 THD (dB) 55 50 40 45 38 40 36 35 30 34 1 10 100 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE AND DISTORTION vs. INPUT FREQUENCY SNR, THD, SINAD vs. TEMPERATURE fs = 250Msps 50 1 100 50 MAX1125 -03 52 10 fs = 250Msps fIN = 100MHz SNR, THD, SINAD (dB) 48 46 44 42 40 MAX1125 -04 SNR (dB) 50 75 MAX1125 -01 52 MAX1125 -02 TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY SINAD (dB) MAX1125 8-Bit, 300Msps Flash ADC 45 THD SNR 40 SINAD 35 38 36 30 34 1 10 INPUT FREQUENCY (MHz) 4 100 -40 -20 0 20 40 TEMPERATURE (°C) _______________________________________________________________________________________ 60 80 8-Bit, 300Msps Flash ADC PIN NAME FUNCTION Ceramic SB CERQUAD 1, 4, 17, 25, 26, 38, 39 3, 7, 12, 22, 27, 32 VEE Negative Analog Supply (nominally -5.2V) 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 28, 30 N.C. No Connect. Not internally connected. 3 31 LINV D0–D6 Output Inversion Control 5, 16, 29, 31, 33, 35 2, 8, 9, 14, 16, 18, 20, 25, 26, 33 AGND Analog Ground 6, 15 1, 34 DGND Digital Ground 7 36 D0 8–13 37–42 D1–D6 14 43 D7 18 4 MINV — 44 D8 20 5 CLK Inverse ECL Clock Input Pin ECL Clock Input Pin Digital Data Output (LSB) Digital Data Output Digital Data Output (MSB) D7 Output Inversion Control Overrange Output 21 6 CLK — 10 VRBS Reference Voltage Bottom, Sense 23 11 VRBF Reference Voltage Bottom, Force 30, 34 15, 19 VIN Analog Input. Can be connected to the input signal or used as a sense. — 13 VR1 Reference Voltage Tap 1 (typically -1.5V) 32 17 VR2 Reference Voltage Tap 2 (typically -1V) — 21 VR3 Reference Voltage Tap 3 (typically -0.5V) 41 23 VRTF Reference Voltage Top, Force — 24 VRTS Reference Voltage Top, Sense — 29 DRINV Data-Ready Inverse — 35 DREADY Data-Ready Output _______________Detailed Description The MAX1125 is a 300Msps, monolithic, 8-bit parallel flash analog-to-digital converter (ADC) with an analog bandwidth of over 200MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators. (See Functional Diagram.) This feature not only reduces clock-transient kickback to the input and reference ladder due to a low AC beta, but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so it remains constant for varying input voltages and frequencies, making the part easier to drive than previous flash converters. The MAX1125 incorporates a special decoding scheme that reduces metastable errors (sparkle codes or flyers) to a maximum of 1LSB. _______________________________________________________________________________________ 5 MAX1125 ______________________________________________________________Pin Description MAX1125 8-Bit, 300Msps Flash ADC The MAX1125 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current-Mode Logic) for reducing potential missing codes while rejecting common-mode noise. Careful layout of the analog circuitry reduces signature errors. Every comparator also has a clock buffer to reduce differential delays and to improve signal-tonoise ratio. The output-drive capability of the device can provide full ECL swings into 50Ω loads. ___________Typical Interface Circuit Figure 1 shows the typical interface circuit. The MAX1125 is relatively easy to apply depending on the accuracy needed. Wire-wrap may be employed with careful point-to-point ground connections if desired, but a double-sided PC board with a ground plane on the component side, separated into digital and analog sections, gives the best performance. The converter is bonded-out to place the digital pins on the left side of the package and the analog pins on the right side. Additionally, an RF bead connection through a single point from the analog to digital ground planes reduces ground noise pickup. Figure 2 (CERQUAD package only) shows the most elaborate method of achieving the least error by correcting for integral nonlinearity, input induced distortion, and power-supply/ground noise. It uses external reference ladder tap connections, an input buffer, and supply decoupling. The function of each pin and external connections to other components is as follows: VEE, AGND, DGND V EE is the supply pin with AGND as ground for the device. The power-supply pins should be bypassed as close to the device as possible with at least a 0.01µF ceramic capacitor. A 1µF tantalum should also be used for low-frequency suppression. DGND is the ground for the ECL outputs and should be referenced to the output pulldown voltage and bypassed as shown in Figure 1. Analog Input VIN There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The MAX1125 is superior to similar devices due to a preamplifier stage before the comparators (Figure 4). This makes the device easier to drive because it has constant capacitance and induces less slew-rate distortion. An optional input buffer may be used. 6 Clock Inputs CLK, CLK The clock inputs are designed to be driven differentially with ECL levels. Because CLK is internally biased to -1.3V, the clock may be driven single-ended (Figure 5). CLK may be left open, but a 0.01µF bypass capacitor from CLK to AGND is recommended. NOTE: System performance may be degraded due to increased noise or jitter. Output Logic Control MINV, LINV These are ECL-compatible digital controls for changing the output code from straight binary to two's complement, etc. (Table 1 and Figure 4). Both MINV and LINV are in the logic low (0) state when left open. The high state can be obtained by tying to AGND through a diode or 3.9kΩ resistor. Table 1. Output Coding MINV LINV 0 0 0 1 1 0 1 1 0V 111...11 100...00 011...11 000...00 . 111...10 100...01 011...10 000...01 . . . . . . . VIN . . . 100...00 . . 111...11 . . 000...00 . . 011...11 . 011...11 000...00 111...11 100...00 . . . . . . . . . . . . . . . . 000...01 011...10 100...01 111...10 -2V 000...00 011...11 100...00 111...11 1: VIH, VOH 0: VIL, VOL Digital Outputs D0 to D7 The digital outputs can drive ECL levels into 50Ω when pulled down to -2V. When pulled down to -5.2V, the outputs can drive 150Ω to 1kΩ loads. Reference Inputs VRBF, VR2, VRTF There are two reference inputs and one external reference voltage tap. These are -2V (VRBF), mid-tap (VR2) and AGND (VRTF). The reference pins can be driven as shown in Figure 1. VR2 should be bypassed to AGND for further noise suppression. Reference Inputs VRBF, VRBS, VR1, VR2, VR3, VRTF, VRTS (CERQUAD package only) These are five external reference voltage taps from -2V (VRBF) to AGND (VRTF) that can be used to control integral linearity over temperature. The taps can be driven by _______________________________________________________________________________________ 8-Bit, 300Msps Flash ADC Not Connected (N.C.) All N.C. pins should be tied to DGND on the left side of the package and to AGND on the right side of the package. Data Ready and Data Ready Inverse DREADY, DRINV (CERQUAD package only) The data-ready pin is a flag that goes high or low at the output when data is valid or ready to be received. It is essentially a delay line that accounts for the time necessary for information to be clocked through the MAX1125's decoders and latches. This function is useful for interfacing with high-speed memory. Using the data-ready output to latch the output data ensures minimum setup and hold times. DRINV is a data-ready inverse control pin (Figure 3). Overrange Input D8 (CERQUAD package only) When the MAX1125 is in an overrange state, D8 goes high, and all data outputs go high as well. This makes it possible to include the MAX1125 in higher resolution systems. Operation The MAX1125 has 256 preamp/comparator pairs that are each supplied with the voltage from VRTF to VRBF divided equally by the resistive ladder as shown in the Functional Diagram. This voltage is applied to the posi- tive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparator states are then clocked through each comparator's individual clock buffer. When CLK is low, the comparators' master, or input stage, compares the analog input voltage to the respective reference voltage. When CLK changes from low to high, the comparators are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRTF (0V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when CLK changes from high to low. At the output of the decoders is a set of four 7-bit latches that are enabled (track) when CLK changes from high to low. From here, the outputs of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Next are the MINV and LINV controls for output inversions that consist of a set of eight XOR gates. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs. _________________Evaluation Boards The MAX1114/MAX1125 evaluation kit (EV kit) demonstrates the full performance of the MAX1125. This board includes a voltage reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. A separate data sheet describing the operation of this board is also available. Contact the factory for price and delivery. _______________________________________________________________________________________ 7 MAX1125 op amps (Figure 2). These voltage level inputs can be bypassed to AGND for further noise suppression, if so desired. VRB and VRT have force and sense pins for monitoring the top and bottom voltage references. MAX1125 8-Bit, 300Msps Flash ADC L ANALOG INPUT CAN BE EITHER FORCE OR SENSE. OPTIONAL BUFFER VRTF 0.01µF VEE -5.2V LINV VIN MINV PREAMP COMPARATOR 256 CLOCK BUFFER = AGND 255 = DGND 152 D7 (MSB) 151 D6 256-BIT TO 8-BIT ENCODER 128 VR2 ECL LATCHES AND BUFFERS D5 0.01µF 127 D4 64 D3 D2 63 D1 2 D0 (LSB) VREF -2V 1 10Ω TO 25Ω OP07 VRBF 0.01µF * 50Ω x 8 MAX1125 VIN 100116 CLK CONVERT 50Ω -2V (ANALOG) 50Ω 2 CLK 0.01µF 0.01µF VEE -5.2V 0.01µF -2V (DIGITAL) Figure 1. Typical Interface Circuit 1 8 _______________________________________________________________________________________ 8-Bit, 300Msps Flash ADC MAX1125 OPTIONAL BUFFER * DGND 10Ω TO 25Ω L AGND 0.01µF VEE -5.2V VRTF U1 LINV VIN VRTS 0.01µF MINV PREAMP COMPARATOR 256 CLOCK BUFFER *ANALOG INPUT (FORCE) **ANALOG INPUT (SENSE) 255 1k, 0.1% OVERRANGE D8 152 10Ω TO 25Ω VR3 U2 D7 (MSB) 151 0.01µF 1k, 0.1% D6 10Ω TO 25Ω NOTE: U1–U5 ARE OP07 OR EQUIVALENT, LOW-NOISE, LOW-OFFSET AMPLIFIERS. ECL LATCHES AND BUFFERS 256-BIT TO 8-BIT ENCODER 128 VR2 U3 D5 127 0.01µF D4 1k, 0.1% 10Ω TO 25Ω 64 D3 VR1 U4 D2 63 0.01µF D1 2 1k, 0.1% D0 (LSB) VREF -2V 1 10Ω TO 25Ω VRBF U5 VRBS 0.01µF 100116 50Ω x 10 CLK 2 CONVERT 50Ω -2V (ANALOG) 50Ω DRINV DREADY MAX1125 CLK ** VIN 0.01µF 0.01µF VEE 0.01µF VEE -5.2V AGND -2V 0.01µF -2V (DIGITAL) Figure 2. Typical Interface Circuit 2 (CERQUAD package only) _______________________________________________________________________________________ 9 MAX1125 8-Bit, 300Msps Flash ADC N+2 N ANALOG INPUT N+1 VIN Tpw1 CLOCK Tpw0 CLK CLK MASTER INTERNAL TIMING COMPARATOR OUTPUT SLAVE 6-BIT LATCH OUTPUT 8-BIT LATCH OUTPUT DATA OUTPUT D0–D7 N-1 OVERRANGE D8 N N+1 tD DREADY TIMING FOR CERQUAD PACKAGE ONLY Figure 3. Timing Diagram AGND AGND VIN AGND DGND VR 10k MINV LINV -1.3V DATA OUT 16k VEE VEE INPUT CIRCUIT OUTPUT CIRCUIT MINV, LINV INPUT CIRCUIT Figure 4. Subcircuit Schematics 10 ______________________________________________________________________________________ 8-Bit, 300Msps Flash ADC MAX1125 AGND -1.3V CLK 13k CLK 13k VEE Figure 5. Clock Input VEE 1N4736 -2V R4 R4 VREF R1 R1 R1 R1 R1 R1 R1 R1 R3 VRBF VEE D0 D1 D2 R2 MAX1125 VIN D3 VIN D4 D5 CLK D6 R2 CLK D7 CLK CLK LINV AGND R1 = 50Ω 1/4 Watt CC 5% R2 = 1kΩ 1/4 Watt CC 5% R3 = 6.5Ω 1/4 Watt CC 5% R4 = 6.5Ω 1/2 Watt CC 5% VREF = -2.00V VEE = -6.6V VRTF DGND R2 MINV R2 -2V Figure 6. Burn-In Circuit (Ceramic SB package only) ______________________________________________________________________________________ 11 MAX1125 8-Bit, 300Msps Flash ADC _________________________________________________________Functional Diagram ANALOG INPUT (FORCE OR SENSE) AGND DGND VEE LINV MINV VRTS MAX1125 VRTF PREAMP COMPARATOR 256 DRINV CLOCK BUFFER 255 VR3 D7 (MSB) DREADY 152 OVERRANGE D7 (MSB) 151 D6 ECL LATCHES AND BUFFERS 256-BIT TO 8-BIT ENCODER 128 VR2 D5 127 D4 D6 64 D5 D3 D4 VR1 63 D2 D3 D2 D1 2 D1 D0 (LSB) 1 D0 (LSB) VRBE VRBS CONVERT CLK THESE FUNCTIONS ARE AVAILABLE IN THE CERQUAD PACKAGE ONLY. 2 CLK ANALOG INPUT (FORCE OR SENSE) VEE AGND Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.