A m p l i fy t h e H u m a n E x p e r i e n c e www.cadeka.com KH563 Wideband, Low Distortion Driver Amplifier Features I I I I I General Description 150MHz bandwidth at +24dBm output Low distortion (2nd/3rd: -59/-62dBc @ 20MHz and 10dBm) Output short circuit protection User-definable output impedance, gain, and compensation Internal current limiting With the output current internally limited to 250mA, the KH563 is fully protected against shorts to ground and can, with the addition of a series limiting resistor at the output, withstand shorts to the ±15V supplies. Applications I I I I I I Output amplification Arbitrary waveform generation ATE systems Cable/line driving Function generators SAW drivers Flash A/D driving and testing Frequency Response vs. Output Power 16 Po = 10dBm Vo = 2Vpp 14 Gain (dB) I Po = 24dBm Vo = 10Vpp 12 Po = 27.5dBm Vo = 15Vpp 10 Po = 18dBm Vo = 5Vpp 8 6 0 40 80 120 160 200 Frequency (MHz) V+ 8 + V- 18 - 5 10 15 20 The KH563 is a wideband DC coupled, amplifier that combines high output drive and low distortion. At an output of +24dBm (10Vpp into 50Ω), the -3dB bandwidth is 150MHz. As illustrated in the table below, distortion performance remains excellent even when amplifying high-frequency signals to high output power levels. 4 +VCC 19 Compensation 23 Vo The KH563 has been designed for maximum flexibility in a wide variety of demanding applications. The two resistors comprising the feedback network set both the gain and the output impedance, without requiring the series backmatch resistor needed by most op amps. This allows driving into a matched load without dropping half the voltage swing through a series matching resistor. External compensation allows user adjustment of the frequency response. The KH563 is specified for both maximally flat frequency response and 0% pulse overshoot compensations. The combination of wide bandwidth, high output power, and low distortion, coupled with gain, output impedance and frequency response flexibility, makes the KH563 ideal for waveform generator applications. Excellent stability driving capacitive loads yields superior performance driving ADC’s, long transmission lines, and SAW devices. A companion part, the KH560, offers superior pulse fidelity for high accuracy DC coupled applications. The KH563 is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions: KH563AI -25°C to +85°C 24-pin Ceramic DIP Typical Distortion Performance 21 -VCC Output Power 10dBm 18dBm 24dBm 20MHz 2nd 3rd 50MHz 2nd 3rd 100MHz 2nd 3rd -59 -52 -50 -52 -45 -36 -35 -30 -40 -62 -48 -41 -60 -46 -32 -49 -36 -30 REV. 1A January 2008 DATA SHEET KH563 KH563 Electrical Characteristics (Av = +10V, VCC = ±15V, RL = 50Ω, Rf = 410Ω, Rg = 40Ω, Ro = 50Ω; unless specified) NOTES TO THE ELECTRICAL SPECIFICATIONS The electrical characteristics shown here apply to the specific test conditions shown above (see also Figure 1 in description of the operation). The KH563 provides an equivalent, non-zero, output impedance determined by the external resistors. The signal gain to the load is therefore load dependent. The signal gain shown above (Av = +10) is the no load gain. The actual gain to the matching 50Ω load used in these specifications is half of this (+5). The KH563 requires an external compensation capacitor. Unless otherwise noted, this has been set to 10.5pF for the frequency domain specifications (yielding a maximally flat frequency response) and 12.5pF for the time domain specifications (yielding a 0% small signal pulse overshoot response). PARAMETERS CONDITIONS Case Temperature KH563AI FREQUENCY DOMAIN RESPONSE (Max. Flat Compensation) -3dB bandwidth maximally flat compensation Vo <2Vpp (+10dBm) 0% overshoot compensation Vo <2Vpp (+10dBm) large signal bandwidth Vo <10Vpp (+24dBm) (see Frequency Response vs. Output Power plot) gain flatness Vo <2Vpp (+10dBm) peaking 0.1 -50MHz peaking >50MHz rolloff at 100MHz group delay to 100MHz linear phase deviation to 100MHz return loss (see discussion of Rx) to 100MHz DISTORTION (Max. Flat Compensation) 2nd harmonic distortion 24dBm (10Vpp): 20MHz 50MHz 100MHz 18dBm (5Vpp): 20MHz 50MHz 100MHz 10dBm (2Vpp): 20MHz 50MHz 100MHz 3rd harmonic distortion 24dBm (10Vpp): 20MHz 50MHz 100MHz 18dBm (5Vpp): 20MHz 50MHz 100MHz 10dBm (2Vpp): 20MHz 50MHz 100MHz 2-tone 3rd order intermod intercept2 20MHz 50MHz 100MHZ TYP MIN & MAX RATINGS UNITS SYM >175 >170 >120 MHz MHz MHz SSBW <0.40 <0.75 <0.75 – <1.2 <-11 <0.50 <1.00 <1.00 – <1.7 <-11 dB dB dB ns ° dB GFPL GFPH GFR GD LPD RL <-38 <-29 <-25 <-42 <-30 <-22 <-48 <-36 <-27 <-40 <-29 <-25 <-44 <-35 <-25 <-52 <-40 <-28 <-38 <-22 <-25 <-42 <-30 <-25 <-48 <-40 <-28 dBc dBc dBc dBc dBc dBc dBc dBc dBc HD2HL HD2HM HD2HH HD2ML HD2MM HD2MH HD2LL HD2LM HD2LH -41 -32 -30 -48 -46 -36 -62 -60 -49 <-34 <-26 <-24 <-40 <-37 <-30 <-54 <-49 <-45 <-34 <-26 <-24 <-44 <-37 <-30 <-57 <-52 <-45 <-30 <-21 <-24 <-44 <-35 <-30 <-57 <-49 <-45 dBc dBc dBc dBc dBc dBc dBc dBc dBc HD3HL HD3HM HD3HH HD3ML HD3MM HD3MH HD3LL HD3LM HD3LH 38 35 29 >36 >32 >27 >36 >32 >27 >36 >32 >23 dBm dBm dBm IM3L IM3M IM3H +25°C -25°C +25°C +85°C 215 210 150 >175 >170 >145 >185 >180 >135 0 0 0.1 2.9 0.6 -15 <0.50 <1.75 <1.00 – <1.7 <-11 -50 -36 -40 -52 -45 -30 -59 -52 -35 FPBW Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. 2 REV. 1A January 2008 KH563 DATA SHEET KH563 Electrical Characteristics (Av = +10V, VCC = ±15V, RL = 50Ω, Rf = 410Ω, Rg = 40Ω, Ro = 50Ω; unless specified) PARAMETERS CONDITIONS Case Temperature KH563AI STATIC, DC PERFORMANCE * input offset voltage average temperature coefficient * non-inverting bias current average temperature coefficient * inverting bias current average temperature coefficient * power supply rejection ratio (DC) * supply current MISCELLANEOUS PERFORMANCE open loop current gain average temperature coefficient inverting input resistance average temperature coefficient non-inverting input resistance non-inverting input capacitance output voltage range output current limit MIN & MAX RATINGS UNITS SYM +25°C -25°C +25°C +85°C 1.5 2.4 7 1.5 3300 <2.0 <2.8 <12 <2.0 >3000 <1.9 <2.8 <12 <2.0 >2900 <2.0 <3.4 <15 <2.0 >2500 ns ns ns % V/µs TRS TRL TS SE SR 5 0 <13 <5 <10 <3 <13 <5 % % OSMF OSZO >100KHz >100KHz >100KHz >100KHz 1kHz to 200MHz >100KHz 2.1 34 2.8 -159 35 15 <2.5 <40 <4.5 <-157 <45 <17 <2.5 <40 <4.5 <-157 <45 <17 <2.5 <45 <5.0 <-157 <45 <17 nV/√Hz pA/√Hz pA/√Hz µV dB VN ICN NCN SNF INV NF no load 2.0 35 5.0 20 10.0 100 57 50 <14.0 <100 <35 <175 <50 <200 >54 <60 <5.0 – <20 – <30 – >54 <60 <15.0 <100 <20 <100 <50 <200 >52 <65 mV µV/°C µA nA/°C µA nA/°C dB mA VIO DVIO IBN DIBN IBI DIBI PSRR ICC 10.0 +0.02 14.0 +.02 700 2.7 ±10.5 210 – <+.03 – <+.025 >200 <3.5 – <250 – – – – >400 <3.5 >±10.0 <250 – <+.02 – <+.025 >400 <3.5 – <250 mA/mA %/°C Ω Ω/°C KΩ pF V mA G DG RIN DRIN RNI CNI VO OCL TIME DOMAIN RESPONSE (0% Overshoot Compensation) rise and fall time 2V step 10V step settling time to 0.5% (time <1µs) 5V step long term thermal tail (time >1µs) 5V step slew rate 10Vpp, 175MHz overshoot 2V step maximally flat compensation 0% overshoot compensation EQUIVALENT INPUT NOISE voltage inverting current non-inverting current noise floor integrated noise noise figure TYP (±2% tolerance) (±5% tolerance) to 100MHz 150mA load current dBm/(1Hz) Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings VCC (reversed supplies will destroy part) differential input voltage common mode input voltage junction temperature (see thermal model) storage temperature lead temperature (soldering 10s) output current (internally limited) Recommended Operating Conditions ±20V ±3V ±VCC +175°C -65°C to +150°C +300°C ±250mA VCC Io common mode input voltage output impedance gain range (no-load voltage gain) case temperature: AI ±10V to ±15V ″ ±200mA < ±(|VCC| -6)V 25Ω to 200Ω +5 to +80 -25°C to +85°C Notes 1) * AI: 100% tested at +25°C AI: sample tested at +25°C 2) Test Tones are set ±100kHz of indicated frequency. REV. 1A January 2008 3 DATA SHEET KH563 KH563 Typical Performance Characteristics (TA = +25°C, Circuit in Figure 1; unless specified) Frequency Response vs. Gain Maximally Flat 0% Overshoot 0 10 -90 Gain Phase -180 8 -270 -360 6 0 50 100 150 200 Av = 10 Av = 5 Av = 15 Normalized Magnitude (1dB/div) 561 Plot1 16 Pi = -4dBm 6 50 100 150 200 250 Frequency Response vs. Power Supply 561 Plot3 Gain (dB) RL = 75Ω ±VCC = 18 RL = 100Ω 12 ±VCC = 15 10 ±VCC = 12 ±VCC = 10 8 Fixed gain and compensated vs. load Re-compensated at each supply voltage 6 200 250 0 50 Frequency (MHz) 150 200 250 160 Ro = 50Ω Ro = 75Ω Ro = 100Ω Response measured with matched load Re-compensated at each Ro 50 100 150 200 Internal Current Gain and Phase Gain (10dB/div) Gain (0.1dB/div) Phase Gain 30 20 180 Phase 10 90 0 0 -90 -10 -20 Re-compensated at each gain 0 50 -180 Phase consistant with current polarity connection of Figure 3 -30 100 150 200 250 0 20 Frequency (MHz) 40 60 80 0 100 100 Two Tone, 3rd-Order Intermodulation 561 Plot7 -25 200 300 400 500 Frequency (MHz) Frequency (MHz) 45 Phase (90°/div) Av = 20 Phase (0.5°/div) Av = 15 560 Plot6 Cx = 0 RL = 0 Gain Av = 10 250 Frequency (MHz) Po = 10dBm Av = 5 200 561 Plot2 Ro = 25Ω 0 Gain Flatness/Deviation from Linear Phase 561 Plot5 Vo = 2Vpp 120 Pi = -4dBm Frequency (MHz) Frequency Response vs. Gain (Ro, RL = 561 75Ω) Plot4 Normalized Magnitude (1dB/div) 100 80 Frequency Response vs. Ro Po = 10dBm 14 150 40 0 Frequency (MHz) RL = 25Ω RL = 50Ω 100 Po = 18dBm Vo = 5Vpp Frequency (MHz) Frequency Response vs. RL 50 Po = 27.5dBm Vo = 15Vpp 10 8 Frequency (MHz) 0 Po = 24dBm Vo = 10Vpp 12 Av = 20 Re-compensated at each gain (see text) 0 250 Po = 10dBm Vo = 2Vpp 14 Normalized Magnitude (1dB/div) 12 Phase (degrees) Gain (dB) 14 Frequency Response vs. Output Power 16 Po = 10dBm Gain (dB) Po = 10dBm Normalized Magnitude (1dB/div) Small Signal Gain and Phase 16 2nd Harmonic Distortion vs. Frequency 561 Plot8 -25 3rd Harmonic Distortion vs. Frequency 561 Plot9 35 Av = 15 Av = 20 -45 50MHz 20MHz -55 10MHz -65 25 Re-compensated at each gain 40 60 80 Frequency Response Driving CL 561 Plot10 CL = 20pF CL = 100pF CL = 50pF 12 16 20 -30 4 24 8 -40 CL = 20pF -50 -60 CL = 50pF -70 200 250 10 20 30 Av = +5 Ro = 25 Vo = 2Vpp 40 50 70 100 16 20 24 -30 3rd Harmonic Distortion Driving CL561 Plot12 Av = +5 Ro = 25 Vo = 2Vpp -40 -50 -60 CL = 50pF CL = 100pF CL = 20pF -70 -80 10 20 30 40 50 70 100 Frequency (MHz) Frequency (MHz) 561 Plot13 12 Output Power (dB) 2nd Harmonic Distortion Driving C561 L Plot11 -80 150 Frequency (MHz) 4 8 CL = 100pF Re-compensated at each CL 100 20MHz 10MHz Compensation as shown in Frequency Response plot Distortion (5dBc/div) Gain (1dB/div) Av = +5 Ro = 25 Vo = 2Vpp 50 -55 Output Power (dB) Frequency (MHz) 0 -45 -75 4 100 Distortion (5dBc/div) 20 100MHz -65 -75 20 0 -35 Distortion (dBc) Av = 10 30 100MHz -35 Distortion (dBc) Intercept (2.5dB/div) 50MHz Av = 5 40 561 Plot14 561 Plot15 REV. 1A January 2008 KH563 DATA SHEET KH563 Typical Performance Characteristics (TA = +25°C, Circuit in Figure 1; unless specified) 0.8 0% Overshoot Compensation 0.4 0 -0.4 -0.8 -1.2 4 0 -2 -4 Settling Time into 50Ω Load -4 Settling Time into 500Ω Load 561 Plot16 0.5 0 -0.5 -1.0 0.5 0 -0.5 -1.0 -1.5 -1.5 -2.0 -2.0 10-1 101 Reverse Transmission Gain & Phase561 (S12)Plot18 -20 Reverse Gain (dB) 1.0 Settling Error (%) 1.0 10-3 0 5V Output Step 1.5 -40 Gain -60 -80 -100 10-9 10-7 10-5 Time (sec) -45 -90 -135 10-3 10-1 101 0 50 Time (sec) Settling Time into 50pF Load 561 Plot19 2.0 0 5V Output Step Magnitude (dB) 0 -0.5 -1.0 150 200 250 0 Input Return Loss (S11) 561 Plot22 -10 -20 -15 -20 Ro = 40Ω Rx = 10Ω -25 -30 -35 -30 Magnitude -40 -50 0 Phase -45 -90 -135 -40 -1.5 -50 10-7 10-5 10-3 10-1 101 0 50 Time (sec) 561 Plot21 -1dB Compensation Point 22 33 21 Noise Figure (dBm) Ro = 50Ω Ro = 75Ω 29 28 27 26 Match Load Re-compensated at each load 25 200 0 250 561 Plot24 40 60 80 Ro = 100Ω 19 Ro = 75Ω 18 Ro = 50Ω 17 16 15 14 Ro = 25Ω 561 Plot25 Non-inverting input impedance matched to source impedance 10 15 20 Gain Error at Load (%) 3.6 3.4 3.2 3.0 2.8 2.6 2.4 Aperture set to 5% of span (12.8MHz) 5 100 150 200 250 3 20 20 10 10 6 4 Non-Inverting Current 2.8pA/√Hz 2 Non-Inverting Voltage 2.1nV/√Hz 100 1k Rf and Rg tolerance = ±0.1% 0 561 Plot28 10k 100k 1M 10M 6 4 2 1 100M PSRR 561 Plot27 100 80 2 1 40 Frequency (Hz) -1 -2 -3 70 60 50 40 30 20 Rf and Rg tolerance = ±1% 5 9 13 17 21 10 0 25 No Load Gain Frequency (MHz) REV. 1A January 2008 Inverting Current 34pA/√Hz 90 -5 50 60 40 30 Ro (nominal) = 50Ω RL = 50Ω ± 0% -4 2.0 0 25 Gain Error Band (Worst Case, DC)561 Plot26 4 3.8 2.2 100 No Load Gain 4.0 250 561 Plot23 1 5 Frequency (MHz) Group Delay 200 60 20 100 150 Equivalent Input Noise PSRR (dB) 20 100 Frequency (MHz) 12 0 50 100 13 24 -180 Noise Current (pA/√Hz) 32 30 150 Noise Figure 34 31 100 Frequency (MHz) Noise Voltage (nV/√Hz) 10-9 Re-compensated at each Rx Re-compensated at each Rx -45 -2.0 Phase (degrees) 0.5 561 Plot20 Ro = 50Ω Rx = 0Ω -10 1.0 100 Frequency (MHz) Output Return Loss (S22) -5 1.5 0 Phase -180 Magnitude (dB) 10-5 561 Plot17 2.0 1.5 10-7 Time (5ns/div) Reverse Phase (degrees) Settling Error (%) 0 -2 -6 5V Output Step Settling Error (%) 2 Time (5ns/div) 2.0 -1dB Compensation (dBm) 4 -6 10-9 Maximally Flat Compensation 6 0% Overshoot Compensation 2 Time (2ns/div) Group Delay (ns) Uni-Polar Pulse Response Maximally Flat Compensation 6 Output Voltage (V) 1.2 Output Voltage (V) Large Signal Pulse Response Maximally Flat Compensation Output Voltage (V) Small Signal Pulse Response 100 1k 10k 100k 1M 10M 100M Frequency (Hz) 561 Plot29 561 Plot30 5 DATA SHEET KH563 SUMMARY DESIGN EQUATIONS AND DEFINITIONS R f = (G + 1) Ro − A vRi R − Ro Rg = f Av − 1 Cx = 1 Ro − 0.08 2 300 1 − Rg Rf – Feedback resistor from output to inverting input Rg – Gain setting resistor from inverting input to ground 6.8m F KH563 Description of Operation Looking at the circuit of Figure 1 (the topology and resistor values used in setting the data sheet specifications), the KH563 appears to bear a strong external resemblance to a classical op amp. As shown in the simplified block diagram of Figure 2, however, it differs in several key areas. Principally, the error signal is a current into the inverting input (current feedback) and the forward gain from this current to the output is relatively low, but very well controlled, current gain. The KH563 has been intentionally designed to have a low internal gain and a current mode output in order that an equivalent output impedance can be achieved without the series matching resistor more commonly required of low output impedance op amps. Many of the benefits of a high loop gain have, however, been retained through a very careful control of the KH563’s internal characteristics. The feedback and gain setting resistors determine both the output impedance and the gain. Rf predominately sets the output impedance (Ro), while Rg predominately determines the no load gain (Av). solving for the required Rf and Rg, given a desired Ro and Av, yields the design equations shown below. Conversely, given an Rf and Rg, the performance equations show that both Rf and Rg play a part in setting Ro and Av. Independent Ro and Av adjustment would be possible if the inverting input impedance (Ri) were 0 but, with Ri = 14Ω as shown in the specification listing, independent gain and output impedance setting is not directly possible. + .1m F Cx 4 Vi (Pi) 8 Rs 50W 18 19 10.5pF + KH563 - Ro 23 Vo (Po) RL 50W 5,10,15, 20 21 Cx – External compensation capacitor from output to pin 19 (in pF) Where: Ro – Desired equivalent output impedance Av – Non-inverting input to output voltage gain with no load G – Internal current gain from inverting input to output = 10 ±1% Ri – Internal inverting input impedance = 14Ω ±%5 Rs – Non-inverting input termination resistor RL – Load resistor AL – Voltage gain from non-inverting input to load resistor 6 +VCC (+15) Rf Resistor Values shown result in: 410W Rg 40W Ro = 50W .1m F + 6.8m F Av = +10 (no-load gain) AL = +5 [14dB] (gain to 50W load) -VCC (-15) Figure 1: Test Circuit KH563 Fig 1 Design Equations R f = (G + 1) Ro − A vRi Rg = R f − Ro Av − 1 Where: R R f + Ri 1 + f Rg Ro = R G + 1+ i Rg Ri G− R Rf A v = 1+ f R g G + 1 + Ri Rg G ≡ forward current gain (=10) Ri ≡ inverting node input resistance (=14Ω) Ro ≡ desired output impedance Av ≡ desired noninverting voltage gain with no load Performance Equations Simplified Circuit Description Looking at the KH563’s simplified schematic in Figure 2, the amplifier’s operation may be described. Going from the non-inverting input at pin 8 to the inverting input at pin 18, transistors Q1 – Q4 act as an open loop unity gain buffer forcing the inverting node voltage to follow the noninverting voltage input. Transistors Q3 and Q4 also act as a low impedance (14Ω looking into pin 18) path for the feedback error current. This current, (ierr), flows through those transistors into a very well defined current mirror having a gain of 10 from this error current to the output. The current mirror outputs act as the amplifier output. The input stage bias currents are supply voltage independent. Since these set the bias level for the whole REV. 1A January 2008 KH563 DATA SHEET part, relatively constant performance over supply voltage is achieved. A current sense in the error current leg of the 10X current mirror feeds back to the bias current setup providing a current shutdown feature when the output current approaches 250mA. +VCC 4 Current Limit Ibias Q1 Vi 19 Cx ierr -VCC +VCC 8 Q4 Ibias Current Limit 23 Ro Vo Rf Rg Q2 Io 5pF 5pF Io 10X Current Mirror 21 -VCC KH560 Fig 2 Figure 2: Simplified Circuit Diagram Developing the Performance Equations The KH563 is intended to provide both a controllable voltage gain from input to output as well as a controllable output impedance. It is best to treat these two operations separately with no load in place. Then, with the no-load gain and output impedance determined, the gain to the load will simply be the no-load gain attenuated by the voltage divider formed by the load and the equivalent output impedance. Figure 3 steps through the output impedance development using an equivalent model of Figure 2. Offering an equivalent, non-zero, output impedance into a matched load allows the KH563 to operate at lower internal voltage swings for a given desired swing at the load. This allows higher voltage swings to be delivered at the load for a given power supply voltage at lower distortion levels than an equivalent op amp needing to generate twice the voltage swing actually desired at the matched load. This improved distortion is specified and tested over a wide range as shown in the specification listing. + ierr Ro Ri Gierr VRg REV. 1A January 2008 if = ierr + R V− = ierr 1 + i Rg Rg R Vo = ierr R f + Ri 1 + f R g and if Rf Ri 1 + R g R Io = Gierr + if = ierr G + 1 + i R g then R R f + Ri 1 + f Rg V Ro ≡ o = R Io G + 1+ i Rg note that Ro = Rf G+1 Ri = 0 Figure 3: Output Impedance Derivation Note that the Ro expression simplifies considerably if Ri = 0. Also note that if the forward current gain were to go to infinity, the output impedance would go to 0. This would be the normal op amp topology with a very high internal gain. The KH563 achieves a non-zero Ro by setting the internal forward gain to be a low, well controlled, value. Developing the No-Load Gain Expression Taking the output impedance expression as one constraint setting the external resistor values, we now need to develop the no-load voltage gain expression from the non-inverting input to the output as the other constraint. Figure 4 shows the derivation of the no load gain. + Vi X1 - V − = ierr Ri and Vo = V − + if R f = ierr Ri + R f 10X Current Mirror Q3 Get both Vo and Io into terms of just the error current, ierr, using: X1 Vo lo ierr Vo Ri Gierr VRg Rf 7 DATA SHEET KH563 recognize that [taking Vi positive] Equivalent Model Given that the physical feedback and gain setting resistors have been determined in accordance with the design equations shown above, an equivalent model may be created for the gain to the load where the amplifier block is taken as a standard op amp. Figure 5 shows this analysis model and the resulting gain equation to the load. Vo = V − + Gierr R f solving for V − from two directions V − = Vi − ierr Ri = (G + 1) ierr R g solving for ierr from this ierr = Vi (G + 1) Rg + Ri Vi + then Classical op-amp Vi Ri V − = Vi − (G + 1) Rg + Ri GR f − Ri Vo = Vi 1 + (G + 1) R g + Ri Ri G− V R Rf A v ≡ o = 1+ f Vi R g G + 1 + Ri Rg Rf Rg Ri = 0 Rf - Ro Vo R f − Ro RL = 1+ Vi R g RL + Ro KH560 Fig 5 substituting in for R f and R g with their design equation yields Vo RL = Av = AL (gain to load) RL + Ro Vi G G + 1 Figure 5: Equivalent Model Figure 4: Voltage Gain Derivation Note again that if Ri = 0 this expression would simplify considerably. Also, if G were very large the voltage gain expression would reduce to the familiar non-inverting op amp gain equation. These two performance equations, shown below, provide a means to derive the design equations for Rf and Rg given a desired no load gain and output impedance. Performance Equations R R f + Ri 1 + f Rg Ro = R G + 1+ i Rg Ri G− Rf R A v = 1+ f R g G + 1 + Ri Rg 8 RL Rg Rf out of the fraction Rg note that A v = 1 + Vo - and, substituting for V − and ierr in the original Vo expression pulling an Ro Design Equations R f = (G + 1) Ro − A v Ri Rg = R f − Ro Av − 1 This model is used to generate the DC error and noise performance equations. As with any equivalent model, the primary intent is to match the external terminal characteristics recognizing that the model distorts the internal currents and voltages. In this case, the model would incorrectly predict the output pin voltage swing for a given swing at the load. But it does provide a simplified means of getting to the external terminal characteristics. External Compensation Capacitor (Cx) As shown in the test circuit of Figure 1, the KH563 requires an external compensation capacitor from the output to pin 19. The recommended values described here assume that a maximally flat frequency response into a matched load is desired. The required Cx varies widely with the desired value of output impedance and to a lesser degree on the desired gain. Note from Figure 2, the simplified internal schematic, that the actual total compensation (Ct) is the series combination of Cx and the internal 10pF from pin 19 to the compensation nodes. The total compensation (Ct) is developed in two steps as shown below. C1 = Ct = 300 2.0 pF intermediate equation 1− Ro R g C1 pF total compensation 1 + (0.02) C1 REV. 1A January 2008 KH563 DATA SHEET Cx = 10 C t 10 − C t or Cx = 1 pF Ro − 0.08 2 300 1 − Rg The plot in Figure 6 shows the required Cx vs. gain for several desired output impedances using the equations shown above. Note that for lower Ro’s, Cx can get very large. But, since the total compensation is actually the series combination of Cx and 10pF, going to very high Cx’s is increasingly ineffective as the total compensation is only slightly changed. This, in part, sets the lower limits on allowable Ro. Gain and Output Impedance Range Figure 7 shows a plot of the recommended gain and output impedances for the KH563. Operation outside of this region is certainly possible with some degradation in performance. Several factors contribute to set this range. At very low output impedances, the required value of feedback resistor becomes so low as to excessively load the output causing a rapid degradation in distortion. The maximum Ro was set somewhat arbitrarily at 200Ω. This allows the KH563 to drive into a 2:1 step down transformer matching to a 50Ω load. (This offers some advantages from a distortion standpoint. 100 Low Rf or Rg Region 90 80 No Load Gain With this total value derived, the required external Cx is developed by backing out the effect of the internal 10pF. This, and an expression for the external Cx without the intermediate steps are shown below. 70 60 50 Recommended Region 40 30 20 10 20 18 0 20 40 60 80 100 120 140 160 180 200 Output Impedance (Ω) 16 14 Cx (pF) High Noise Region 0 Maximally Flat Response into a Matched Load KH560 Fig 7 12 Figure 7: Recommended Gain and Output Impedance Range Ro = 50Ω 10 8 6 Ro = 75Ω 4 Ro = 100Ω 2 0 5 10 15 20 25 30 35 40 45 50 55 No Load Voltage Gain KH560 Fig (C 6 ) Figure 6: External Compensation Capacitance x A 0% small signal overshoot response can be achieved by increasing Cx slightly from the maximally flat value. Note that this applies only for small signals due to slew rate effects coming into play for large, fast edge rates. Beyond the nominal compensation values developed thus far, this external Cx provides a very flexible means for tailoring the frequency response under a wide variety of gain and loading conditions. It is oftentimes useful to use a small adjustable cap in development to determine a Cx suitable to the application, then fixing that value for production. An excellent 5pF to 20pF trimmer cap for this is a Sprague-Goodman part #GKX20000. When the KH563 is used to drive a capacitive load, such as an ADC or SAW device, the load will act to compensate the response along with Cx. Generally, considerably lower Cx values are required than the earlier development would indicate. This is advantageous in that a low Ro would be desired to drive a capacitive load which, without the compensating effect of load itself, would otherwise require very large Cx values. REV. 1A January 2008 For a given Ro, the minimum gain shown in Figure 7 has been set to keep the equivalent input noise voltage less than 4nV/√Hz. Generally, the equivalent input noise voltage decreases with higher signal gains. The high gain limit has been set by targeting a minimum Rg of 10Ω or a minimum Rf of 100Ω. Amplifier Configurations The KH563 is intended for a fixed, non-inverting, gain configuration as shown in Figure 1. The KH560 offers the better pulse fidelity with its improved thermal tail in the pulse response (vs. the KH563). Due to its low internal forward gain, the inverting node does not present a low impedance, or virtual ground, node. Hence, in an inverting configuration, the signal’s source impedance will see a finite load whose value depends on the output loading. Inverting mode operation can be best achieved using a wideband, unity gain buffer with low output impedance, to isolate the source from this varying load. A DC level can, however, be summed into the inverting node to offset the output either for offset correction or signal conditioning. Accuracy Calculations Several factors contribute to limit the achievable KH563 accuracy. These include the DC errors, noise effects, and the impact internal amplifier characteristics have on the signal gain. Both the output DC error and noise model may be developed using the equivalent model of Figure 5. Generally, non-inverting input errors show up at the 9 DATA SHEET KH563 output with the same gain as the input signal, while the inverting current errors have a gain of simply (Rf - Ro) to the output voltage (neglecting the Ro to RL attenuation). Output DC Offset: The DC error terms shown in the specification listing along with the model of Figure 5 may be used to estimate the output DC offset voltage and drift. Each term shown in the specification listing can be of either polarity. While the equations shown below are for output offset voltage, the same equation may be used for the drift with each term replaced by its temperature drift value shown in the specification listing. R − Ro Vos = (Ibn ⋅ R s ± Vio ) ⋅ 1 + f ± Ibi (R f − Ro ) R g where: Ibn ≡ non − inverting bias current Ibi ≡ inverting bias current Vio ≡ input offset voltage An example calculation for the circuit in Figure 1 using typical 25°C DC error terms and Rs = 25Ω, RL = 50Ω yields: [ ] Vo = (5µA ⋅ 25Ω ± 2.0mV) 10 ± 10µA (360Ω) L 1/ 2 = ±12.4mV DC ↑ attentuation between Ro and RL Recall that the source impedance, Rs, includes both the terminating and signal source impedance and that the actual DC level to the load includes the voltage divider between Ro and RL. Also note that for the KH563, as well as for all current feedback amplifiers, the non-inverting and inverting bias currents do not track each other in either magnitude or polarity. Hence, there is no meaning in an offset current specification, and source impedance matching to cancel bias currents is ineffective. Noise Analysis: Although the DC error terms are in fact random, the calculation shown above assumes they are all additive in a worst case sense. The effect of all the various noise sources are combined as a root sum of squared terms to get an overall expression for the spot noise voltage. The circuit of Figure 8 shows the equivalent circuit with all the various noise voltages and currents included along with their gains to the output. Rs √4kTRs e*ni * ini * + Classical op-amp - * ii √4kT Rg * Rg Rf - Ro eo Ro √4kT(Rf - Ro) * where: KH560 FigGain 8 eni – non-inverting input voltage noise ini – non-inverting input current noise ii – inverting input current noise to eo Av AvRs Rf - Ro 4kTRs − source resis tan ce voltage noise Av 4kT / R g − gain settling resistor noise current Rf - Ro 4kT(R f − Ro ) − feedback resistor voltage noise 1 4kTRo − output resistor voltage noise 1 Figure 8: Equivalent Noise Model To get an expression for the equivalent output noise voltage, each of these noise voltage and current terms must be taken to the output through their appropriate gains and combined as the root sum of squares. eo = (e ni 2 ) + (iniR s ) + 4kTRs A v 2 + ii2 (R f − Ro ) L 2 2 + 4kT (R f − Ro ) A v + 4kTRo Where the 4kT(Rf - Ro) Av term is the combined noise power of Rg and Rf - Ro. It is often more useful to show the noise as an equivalent input spot noise voltage where every term shown above is reflected to the input. This allows a direct measure of the input signal to noise ratio. This is done by dividing every term inside the radical by the signal voltage gain squared. This, and an example calculation for the circuit of Figure 1, are shown below. Note that RL may be neglected in this calculation. en = eni2 + (iniR s ) + 4kTRs + 2 ii2 (R f − Ro ) Av2 4kT (R f − Ro ) Av 10 * √4kTRVo + 2 +L 4kTRo Av2 REV. 1A January 2008 KH563 DATA SHEET For the circuit of Figure 1, the equivalent input noise voltage may be calculated using the data sheet spot noises and Rs = 25Ω, RL = ∞. Recall that 4kT = 16E-21J. All terms cast as (nV/√Hz)2 en = Vi + Rs KH563 current gain G inverting input Ri Rf Rg Vo RR o L= R'o - Rx With: Ro = KH563 output impedance and Ro + Rx = RL generally Increases AL Decreases AL lncreases AL Decreases AL Applications Suggestions Driving a Capacitive Load: The KH563 is particularly suitable for driving a capacitive load. Unlike a classical op amp (with an inductive output impedance), the KH563’s output impedance, while starting out real at the programmed value, goes somewhat capacitive at higher frequencies. This yields a very stable performance driving a capacitive load. The overall response is limited by the (1/RC) bandwidth set by the KH563’s output impedance and the load capacitance. It is therefore advantageous to set a low Ro with the constraint that extremely low Rf values will degrade the distortion performance. Ro = 25Ω was selected for the data sheet plots. Note from distortion plots into a capacitive load that the KH563 achieves better than 60dBc THD (10-bits) driving 2Vpp into a 50pF load through 30MHz. Improving the Output Impedance Match vs. Frequency - Using Rx: Using the loop gain to provide a non-zero output impedance provides a very good impedance match at low frequencies. As shown on the Output Return Loss plot, however, this match degrades at higher frequencies. Adding a small external resistor in series with the output, Rx, as part of the output impedance (and adjusting the programmed Ro accordingly) provides a much better match over frequency. Figure 9 shows this approach. REV. 1A January 2008 Rx Rf Rg Gain Accuracy (DC): A classical op amp’s gain accuracy is principally set by the accuracy of the external resistors. The KH563 also depends on the internal characteristics of the forward current gain and inverting input impedance. The performance equations for Av and Ro along with the Thevinin model of Figure 5 are the most direct way of assessing the absolute gain accuracy. Note that internal temperature drifts will decrease the absolute gain slightly as the part warms up. Also note that the parameter tolerances affect both the signal gain and output impedance. The gain tolerance to the load must include both of these effects as well as any variation in the load. The impact of each parameter shown in the performance equations on the gain to the load (AL) is shown below. Increasing Increasing Increasing Increasing R'o = Rx + Ro - (2.1)2 + (.07)2 + (.632)2 + (1.22)2 + (.759)2 + (.089)2 = 2.62nV/ Hz Cx Case Temperature Tc Figure 9: Improving Output Impedance Match vs. Frequency θca Case to Ambient 20∞C/W 200∞C/W Termal Impedance T T j(t) j(q) Increasing Rx will decrease the achievableTAvoltage swing at the Rx should Pt load. A minimum Pq Pcircuit be used consistent Ambient in the with the desired output match. As discussed Temperature thermal analysis discussion, Rx is also very useful in limiting the internal power under an output shorted condition. KH563 Fig 9 Interpreting the Slew Rate: The slew rate shown in the data sheet applies to the voltage swing at the load for the circuit of Figure 1. Twice this value would be required of a low output impedance amplifier using an external matching resistor to achieve the same slew rate at the load. Layout Suggestions: The fastest fine scale pulse response settling requires careful attention to the power supply decoupling. Generally, the larger electrolytic capacitor ground connections should be as near the load ground (or cable shield connection) as is reasonable, while the higher frequency ceramic de-coupling caps should be as near the KH563’s supply pins as possible to a low inductance ground plane. Evaluation Boards: An evaluation board (showing a good high frequency layout) for the KH563 is available. This board may be ordered as part #730019. Thermal Analysis and Protection A thermal analysis of a chip and wire hybrid is directed at determining the maximum junction temperature of all the internal transistors. From the total internal power dissipation, a case temperature may be developed using the ambient temperature and the case to ambient thermal impedance. Then, each of the dominant power dissipating paths are considered to determine which has the maximum rise above case temperature. The thermal model and analysis steps are shown below. As is typical, the model is cast as an electrical model where the temperatures are voltages, the power dissipators are current sources, and the thermal impedances are resistances. Refer to the summary design equations and Figure 1 for a description of terms. 11 RL - Ro = R'o - Rx Rf DATA SHEET With: Rg Case Temperature Tc 20°C/W 200°C/W Tj(t) Tj(q) Pt Pq θca Case to Ambient Termal Impedance TA Pcircuit Ambient Temperature Figure 10: Thermal Model Io = Vo /R eq total output current with R eq = RL It = KH560 Fig 9 2 R A f L total load AL − 1 ( ) ( ) Pq = 0.1 ⋅ It ⋅ VCC − Vo − 0.7 − 15.3Ω ⋅ It power in hottest internal junction prior to output stage ( ) ) Pcircuit = 1.3 ⋅ VCC ⋅ 2 ⋅ It − Io + 19.2mA − Pt − Pq power in remainder of circuit [note VCC = | − VCC|] Note that the Pt and Pq equations are written for positive Vo. Absolute values of -VCC, Vo, and Io, should be used for a negative going Vo. since we are only interested in delta V’s. For bipolar swings, the two powers for each output polarity are developed as shown above then ratioed by the duty cycle. Having the total internal power, as well as its component parts, the maximum junction temperature may be computed as follows. Tc = TA + (Pq + PT + Pcircult) • θca Case Temperature θca = 35°C/W for the KH563 with no heatsink in still air Tj(t) = Tc + Pt • 20°C/W output transistor junction temperature Tj(q) = Tc + Pq • 200°C/W hottest internal junction temperature The Limiting Factor for Output Power is Maximum Junction Temperature Reducing θca through either heatsinking and/or airflow can greatly reduce the junction temperatures. One effective means of heatsinking the KH563 is to use a thermally conductive pad under the part from the package bottom to a top surface ground plane on the component side. Tests have shown a θca of 24°C in still air using a “Sil Pad” available from Bergquist (800-347-4572). 12 410Ω ⋅ 5 = 45.6Ω 5 −1 R eq = 50Ω ( ) Io = 2.5V/ 45.6Ω = 54.9mA 1 2 54.9mA + (54.9mA ) + (.06 ) 2 2 = 68.1mA PT = 68.1mA 15 − 2.5 − 0.7 − 15.3Ω ⋅ 68.1mA = 733mW total power in both sides of the output stage e Pt = I t ⋅ VCC − 1.4 − 17.3Ω ⋅ It output stage power ( As an example of calculating the maximum internal junction temperatures, consider the circuit of Figure 1 driving ±2.5V, 50% duty cycle, square wave into a 50Ω load. IT = 2 2 Io + Io + .06 total internal output stage current 1 KH563 Ro = KH560 output impedance and Ro + Rx = RL generally Pq = 0.1 ⋅ 68.1mA 15 − 1.4 − 17.3Ω ⋅ 68.1mA = 84.5mW total power in both sides of hottest junctions prrior to output stage ( ) Pcircuit = 1.3 ⋅ 15 ⋅ 2 ⋅ 68.1mA − 54.9mA + 19.2mA − 733mW − 169mW = 1.058W power in the remainder of circuit With these powers and TA = 25°C and θ ca = 35°C/W ( ) Tc = 25°C + .733 + .169 + 1.058 ⋅ 35 = 94°C case temperature From this, the hottest internal junctions may be found as 1 .733 ⋅ 20 = 101°C output stage () ) 2( Tj ( q) = 94°C + 1 (.0845 ) ⋅ 200 = 102°C 2 Tj t = 94°C + hottest internal junction Note that 1/2 of the total PT and Pa powers were used here since the 50% duty cycle output splits the power evenly between the two halves of the circuit whereas the total powers were used to get case temperature. Even with the output current internally limited to 250mA, the KH563’s short circuiting capability is principally a thermal issue. Generally, the KH563 can survive short duration shorts to ground without any special effort. For protection against shorts to the ±15 volt supply voltages, it is very useful to reduce some of the voltage across the output stage transistors by using some external output resistance, Rx, as shown in Figure 9. Evaluation Board An evaluation board (part number 730019) for the KH563 is available. REV. 1A January 2008 DATA SHEET KH563 KH563 Package Dimensions 24-Pin 0.6" Side-Brazed Ceramic DIP C b1 Pin #1 Index Q A L b E1 E e D1 A1 D Symbol Inches Minimun A Maximum Milimeters Minimum 0.225 Maximum 5.72 A1 0.139 0.192 3.53 4.88 b 0.014 0.026 0.36 0.66 b1 0.050 BSC 1.27 BSC c 0.008 0.018 0.20 0.46 D 1.190 1.290 30.23 32.77 D1 1.095 1.105 27.81 28.07 E 0.500 0.610 12.70 15.49 E1 0.600 BSC 15.24 BSC e 0.100 BSC 2.54 BSC L Q 0.165 BSC 0.015 0.075 NOTES: Seal: seam weld (AM, AK), epoxy (AI) Lead finish: gold finish Package composition: Package: ceramic Lid: kovar/nickel (AM, AK), ceramic (AI) Leadframe: alloy 42 Die attach: epoxy 4.19 BSC 0.38 1.91 ©1998 KOTA Microcircuits, Inc. Life Support Policy Cadeka’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Cadeka Microcircuits, Inc. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Cadeka does not assume any responsibility for use of any circuitry described, and Cadeka reserves the right at any time without notice to change said circuitry and specifications. www.cadeka.com © 2008 Cadeka Microcircuits, LLC