OPA847 OPA 847 SBOS251C – JULY 2002 – REVISED OCTOBER 2003 Wideband, Ultra-Low Noise, Voltage-Feedback OPERATIONAL AMPLIFIER with Shutdown FEATURES DESCRIPTION z z z z z z z z The OPA847 combines very high gain bandwidth and large signal performance with an ultra-low input noise voltage (0.85nV/√Hz) while using only 18mA supply current. Where power savings is critical, the OPA847 also includes an optional power shutdown pin that, when pulled low, disables the amplifier and decreases the supply current to < 1% of the powered-up value. This optional feature may be left disconnected to ensure normal amplifier operation when no powerdown is required. HIGH GAIN BANDWIDTH: 3.9GHz LOW INPUT VOLTAGE NOISE: 0.85nV/√Hz VERY LOW DISTORTION: –105dBc (5MHz) HIGH SLEW RATE: 950V/µs HIGH DC ACCURACY: VIO < ±100µV LOW SUPPLY CURRENT: 18.1mA LOW SHUTDOWN POWER: 2mW STABLE FOR GAINS ≥ 12 The combination of very low input voltage and current noise, along with a 3.9GHz gain bandwidth product, make the OPA847 an ideal amplifier for wideband transimpedance applications. As a voltage gain stage, the OPA847 is optimized for a flat frequency response at a gain of +20V/V and is stable down to gains as low as +12V/V. New external compensation techniques allow the OPA847 to be used at any inverting gain with excellent frequency response control. Using this technique in a differential Analog-to-Digital Converter (ADC) interface application, shown below, can deliver one of the highest dynamic-range interfaces available. APPLICATIONS z HIGH DYNAMIC RANGE ADC PREAMPS z LOW NOISE, WIDEBAND, TRANSIMPEDANCE AMPLIFIERS z WIDEBAND, HIGH GAIN AMPLIFIERS z LOW NOISE DIFFERENTIAL RECEIVERS z ULTRASOUND CHANNEL AMPLIFIERS z IMPROVED UPGRADE FOR THE OPA687, CLC425, AND LMH6624 OPA847 RELATED PRODUCTS SINGLES OPA842 OPA843 OPA846 +5V 0.001µF 100Ω 39pF 850Ω –75 VCM ADS5421 14-Bit 40MSPS 0.1µF 2kΩ +5V 1.7pF 0.001µF 20Ω 2VPP, at converter input. VIN+ 100pF VIN– 100pF OPA847 24.6dB Gain Harmonic Distortion (dBc) 2kΩ 850Ω –5V 200 800 1750 DIFFERENTIAL OPA847 DRIVER DISTORTION 39pF 100Ω 2.6 2.0 1.2 –70 –5V 1:2 < 5.1dB Noise Figure GAIN BANDWIDTH PRODUCT (MHz) +5V 20Ω OPA847 1.7pF 50Ω Source INPUT NOISE VOLTAGE (nV/ √Hz ) –80 –85 –90 2nd-Harmonic –95 3rd-Harmonic –100 –105 Ultra-High Dynamic Range Differential ADC Driver –110 10 20 30 40 50 Frequency (MHz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002-2003, Texas Instruments Incorporated www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation ........................ See Thermal Analysis Section Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: D, DBV .......................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ............................................................ +150°C ESD Rating (Human Body Model) .................................................. 1500V (Charge Device Model) ............................................... 1500V (Machine Model) ........................................................... 100V Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Texas Instruments recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. PACKAGE/ORDERING INFORMATION PRODUCT OPA847 PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY SO-8 D –40°C to +85°C OPA847 " " " " SOT23-6 DBV –40°C to +85°C OATI " " " " OPA847ID OPA847IDR OPA847IDBVT OPA847IDBVR Rails, 100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000 " OPA847 " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATIONS DIS Inverting Input 2 7 +VS Noninverting Input 3 6 Output –VS 4 5 NC 1 6 +VS –VS 2 5 DIS Noninverting Input 3 4 Inverting Input 4 8 Output OATI 1 NC = No Connection 3 1 SOT 2 NC Top View 5 SO 6 Top View Pin Orientation/Package Marking 2 OPA847 www.ti.com SBOS251C ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. RL = 100Ω, RF = 750Ω, RG = 39.2Ω, and G = +20 (see Figure 1 for AC performance only), unless otherwise noted. OPA847ID, IDBV TYP PARAMETER AC PERFORMANCE (see Figure 1) Closed-Loop Bandwidth Gain Bandwidth Product (GBP) Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +12 Harmonic Distortion 2nd-Harmonic 3rd-Harmonic 2-Tone, 3rd-Order Intercept Input Voltage Noise Density Input Current Noise Density Pulse Response Rise-and-Fall Time Slew Rate Settling Time to 0.01% 0.1% 1% DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift (magnitude) Input Offset Current Input Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential Common-Mode OUTPUT Output Voltage Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio +PSRR, –PSRR POWER-DOWN (disabled low) Power-Down Quiescent Current (+VS) On Voltage (enabled high or floated) Off Voltage (disabled asserted low) Power-Down Pin Input Bias Current Power-Down Time Power-Up Time Off Isolation THERMAL Specification ID, IDBV Thermal Resistance, θJA D SO-8 DBV SOT23 MIN/MAX OVER TEMPERATURE CONDITIONS +25°C +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) UNITS MIN/ TEST MAX LEVEL(3) G = +12, RG = 39.2Ω, VO = 200mVPP G = +20, RG = 39.2Ω, VO = 200mVPP G = +50, RG = 39.2Ω, VO = 200mVPP G ≥ +50 G = +20, RL = 100Ω 600 350 78 3900 60 4.5 230 63 3100 40 7 210 60 3000 35 10 195 57 2800 30 12 MHz MHz MHz MHz MHz dB typ min min min min max C B B B B B G = +20, f = 5MHz, VO = 2VPP RL = 100Ω RL = 500Ω RL = 100Ω RL = 500Ω G = +20, f = 20MHz f > 1MHz f > 1MHz –74 –105 –103 –110 39 0.85 2.5 –70 –90 –96 –105 37 0.92 3.5 –69 –89 –91 –100 36 0.98 3.6 –68 –88 –88 –90 35 1.0 3.7 dBc dBc dBc dBc dBm nV/√Hz pA/√Hz max max max max min max max B B B B B B B 0.2V Step 2V Step 2V Step 2V Step 2V Step 1.2 950 20 10 6 1.75 700 2.0 625 2.2 535 12 8 14 10 18 12 ns V/µs ns ns ns max min typ max max B B C B B VO = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V 98 ±0.1 ±0.25 –19 –15 ±0.1 ±0.1 90 ±0.5 ±0.25 –39 –15 ±0.6 ±0.1 89 ±0.58 ±1.5 –41 –40 ±0.7 ±2 88 ±0.60 ±1.5 –42 –70 ±0.85 ±3.5 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B VCM = ±0.5V, Input Referred ±3.3 110 ±3.1 95 ±3.0 93 ±2.9 90 V dB min min A A VCM = 0V VCM = 0V 2.7 || 2.0 2.3 || 1.7 kΩ || pF MΩ || pF typ typ C C ≥ 400Ω Load 100Ω Load VO = 0V VO = 0V G = +20, f = < 100kHz ±3.5 ±3.4 100 –75 0.003 V V mA mA Ω min min min min typ A A A A C ±3.3 ±3.2 60 –60 ±3.1 ±3.0 56 –56 ±3.0 ±2.9 52 –52 VS = ±5V VS = ±5V ±5 ±6 18.1 18.1 ±6 18.4 17.8 ±6 18.7 17.5 ±6 18.9 17.1 V V mA mA typ max max min C A A A |VS| = 4.5V to 5.5V, Input Referred 100 95 93 90 dB min A –200 3.5 1.8 150 200 60 70 –270 3.75 1.7 190 –320 3.85 1.6 200 –370 3.95 1.5 210 µA V V µA ns ns dB max min max max typ typ typ A A A A C C C –40 to +85 °C typ C 125 150 °C/W °C/W typ typ C C (Pin 8 on SO-8; Pin 5 on SOT23-6) (VDIS = 0) 5MHz, Input to Output Junction-to-Ambient NOTES: (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits. OPA847 SBOS251C www.ti.com 3 TYPICAL CHARACTERISTICS: VS = ±5V TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 0 VO = 0.2VPP RL = 100Ω RG = RS = 50Ω RF Adjusted G = +12 3 Normalized Gain (dB) –3 G = +20 –6 G = +30 –9 G = +50 0 –3 –6 –9 G = –40 –12 –12 –15 1 10 100 1000 1 10 100 Frequency (MHz) NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 35 RG = 39.2Ω RL = 100Ω G = +20V/V VO = 200mVPP 26 See Figure 2 32 VO = 0.2VPP VO = 1VPP 29 Gain (dB) 23 20 17 VO = 2VPP 26 23 VO = 5VPP VO = 1VPP 20 14 VO = 2VPP 11 17 VO = 5VPP See Figure 1 10 100 10 1000 NONINVERTING PULSE RESPONSE Large Signal ± 1V Right Scale 0.15 0.10 0.25 1.00 0.20 0.75 0.50 Small Signal ± 100mV 0.05 Left Scale 0 0.25 0 0.15 0.10 0.05 0 –0.05 –0.25 –0.10 –0.50 –0.15 –0.75 –0.20 –1.00 –0.20 –1.25 –0.25 See Figure 1 –0.25 1000 INVERTING PULSE RESPONSE 1.25 Output Voltage (50mV/div) G = +20V/V Output Voltage (250mV/div) 0.25 100 Frequency (MHz) Frequency (MHz) Output Voltage (50mV/div) RL = 100Ω RG = RS = 50Ω G = –40V/V 14 8 Large Signal ± 1V Right Scale Small Signal ± 100mV Left Scale –0.05 –0.15 1.25 1.00 0.75 0.50 0.25 0 –0.25 –0.10 Time (5ns/div) 4 1000 Frequency (MHz) 29 Gain (dB) G = –50 See Figure 2 See Figure 1 –15 0.20 G = –30 G = –20 –0.50 G = –40V/V RG = RS = 50Ω RL = 100Ω –0.75 See Figure 2 –1.00 –1.25 Time (5ns/div) OPA847 www.ti.com SBOS251C Output Voltage (250mV/div) Normalized Gain (dB) 6 VO = 0.2VPP RG = 39.2Ω RL = 100Ω RF Adjusted 3 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted. 1MHz HARMONIC DISTORTION vs LOAD RESISTANCE 5MHz HARMONIC DISTORTION vs LOAD RESISTANCE –70 Harmonic Distortion (dBc) –75 Harmonic Distortion (dBc) –75 G = +20V/V VO = 2VPP –80 –85 –90 2nd-Harmonic –95 –100 3rd-Harmonic –105 G = +20V/V VO = 5VPP –80 2nd-Harmonic –85 –90 –95 3rd-Harmonic –100 –110 See Figure 1 See Figure 1 –115 –105 100 150 200 250 300 350 400 450 500 100 150 200 –75 G = +20V/V VO = 2VPP RL = 200Ω –80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 300 350 400 450 500 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY –65 –75 250 Load Resistance (Ω) Load Resistance (Ω) 2nd-Harmonic –85 –95 3rd-Harmonic –105 G = +20V/V F = 5MHz RL = 200Ω –85 2nd-Harmonic –90 –95 –100 3rd-Harmonic –105 –110 See Figure 1 See Figure 1 –115 –115 0.1 1 10 0.1 100 1 HARMONIC DISTORTION vs INVERTING GAIN HARMONIC DISTORTION vs NONINVERTING GAIN –70 –75 –75 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –80 2nd-Harmonic –85 –90 –95 10 Output Voltage Swing (VPP) Frequency (MHz) VO = 2VPP RL = 200Ω F = 5MHz RF = 750Ω RG Adjusted –100 3rd-Harmonic –105 –80 –85 –90 –95 –100 2nd-Harmonic VO = 2VPP RL = 200Ω F = 5MHz RG = 50Ω RF Adjusted 3rd-Harmonic –105 See Figure 2 See Figure 1 –110 –110 15 20 25 30 35 40 45 50 55 20 50 OPA847 SBOS251C 25 30 35 40 45 50 Gain –V/V Gain (V/V) www.ti.com 5 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT 50 G = +20V/V 20dB to matched load. 45 2.7pA/√Hz Current Noise Intercept Point (+dBm) Voltage Noise (nV/√Hz) Current Voise (pA/√Hz) 10 1 0.85nV/√Hz Voltage Noise 40 35 50Ω PI 30 PO 50Ω OPA847 50Ω 750Ω 25 39.2Ω 20 0 101 102 103 104 105 106 107 5 10 15 20 Frequency (Hz) NONINVERTING GAIN FLATNESS TUNE VO = 200mVPP AV = +12V/V NG = Noise Gain 0.4 0.3 NG = 12 40 45 50 0 NG = 14 Normalized Gain (1dB) Deviation from 21.58dB Gain (0.1dB) 35 LOW GAIN INVERTING BANDWIDTH NG = 16 0.2 0.1 0 –0.1 NG = 18 –0.2 NG = 20 External Compensation See Figure 8 –0.4 G = –8 –1 –2 –3 VO = 0.2VPP RF = 750Ω –4 G = –1 –5 –6 G = –2 –7 –0.3 G = –4 External Compensation See Figure 6 –8 –9 –0.5 1 10 100 1000 1 10 Frequency (MHz) Normalized Gain to Capacitive Load (dB) G = +20V/V 10 1 10 100 1000 FREQUENCY RESPONSE vs CAPACITIVE LOAD RECOMMENDED RS vs CAPACITIVE LOAD 1 100 Frequency (MHz) 100 RS (Ω) 30 1 0.5 1000 Capacitive Load (pF) 6 25 Frequency (MHz) 29 RS adjusted for capacitive load. C = 10pF 26 C = 22pF 23 C = 47pF C = 100pF RS VI 20 VO 50Ω OPA847 CL 1kΩ 750Ω 17 (1kΩ is optional.) 39.2Ω 14 1 10 100 1000 Frequency (MHz) OPA847 www.ti.com SBOS251C TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted. COMMON-MODE REJECTION RATIO AND POWER-SUPPLY REJECTION RATIO vs FREQUENCY CMRR 0 +PSRR 110 –30 100 100 Open-Loop Gain (dB) CMRR and PSRR (dB) OPEN-LOOP GAIN AND PHASE 120 90 80 –PSRR 70 60 50 40 30 20log (AOL) 80 60 –90 40 –120 20 –150 0 –180 –210 –20 20 102 103 104 105 106 107 108 102 103 104 105 106 107 108 109 Frequency (Hz) Frequency (Hz) CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY OUTPUT VOLTAGE AND CURRENT LIMITATIONS 4 10 VDIS 3 Output Impedance (Ω) RL = 100Ω 2 1 VO (V) –60 ∠AOL Open-Loop Phase (°) 120 RL = 50Ω 0 RL = 25Ω –1 –2 G = +20V/V ZO OPA847 1 750Ω 0.1 39.2Ω 0.01 –3 0.001 –100 –50 0 50 100 103 150 104 10 0.4 8 0.3 6 0.2 Output Left Scale 2 0.1 0 0 Output Voltage (V) 4 G = +20V/V RL = 100Ω 0.5 Input Voltage (mV) Output Voltage (V) 6 4 Input Right Scale 0.20 0.15 0.10 0.05 0 –2 –0.1 –0.2 –6 –0.3 –6 –8 –0.4 –8 –0.5 –10 –4 –0.05 –0.10 Output Left Scale –0.15 –0.20 See Figure 2 –0.25 Time (40ns/div) Time (40ns/div) OPA847 SBOS251C 0.25 G = –40V/V RG = 50Ω RL = 100Ω 0 –4 –10 108 2 –2 See Figure 1 107 INVERTING OVERDRIVE RECOVERY NONINVERTING OVERDRIVE RECOVERY 10 Input Right Scale 106 Frequency (Hz) IO (mA) 8 105 www.ti.com 7 Input Voltage (mV) –4 –150 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted. PHOTODIODE TRANSIMPEDANCE FREQUENCY RESPONSE SETTLING TIME 0.25 0.15 Transimpedance Gain (dBΩ) 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 RF = 20kΩ CF Adjusted 86 83 80 0.01µF 77 20kΩ IO CF CDIODE [CD] 74 5 10 15 20 25 30 35 1 40 10 TYPICAL DC DRIFT OVER TEMPERATURE SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 0.2 100 12.5 VIO 0 0 –0.1 –12.5 Ib –0.2 Supply Current 0 25 50 75 100 18 Sourcing Output Current 80 16 Sinking Output Current 70 14 60 12 50 –25.0 –25 20 90 Output Current (mA) 100 x IOS 0.1 Input Bias and Offset Current (µA) 25.0 –50 100 Frequency (MHz) Time (ns) Input Offset Voltage (mV) VO 20kΩ OPA847 71 0 125 10 –50 –25 0 25 50 75 100 Ambient Temperature (°C) Ambient Temperature (°C) COMMON-MODE INPUT RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE COMMON-MODE AND DIFFERENTIAL INPUT IMPEDANCE RL = 100Ω 3 Common-Mode (2.3MΩ, DC) 106 Input Impedance (Ω) Positive Output 2 1 Positive Input 0 125 107 5 Voltage Range (V) CD = 20pF CD = 50pF CD = 100pF See Figure 1 –0.25 4 CD = 10pF [20log 20kΩ] –1 Negative Input –2 105 Differential (2.7kΩ, DC) 104 103 –3 Negative Output –4 102 102 6.00 5.75 5.50 5.25 5.00 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 2.75 2.50 –5 103 104 105 106 107 108 Frequency (Hz) Supply Voltage (±V) 8 OPA847 www.ti.com SBOS251C Supply Current (mA) Percent of Final Value (%) 89 G = +20V/V RL = 100Ω VO = 2V Step 0.20 TYPICAL CHARACTERISTICS: VS = ±5V TA = 25°C, GD = 40V/V, RG = 50Ω, and RL = 400Ω, unless otherwise noted. DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL PERFORMANCE TEST CIRCUIT 3 +5V 0 Normalized Gain (dB) DIS OPA847 GD = –5V RG 50Ω RF RG 50Ω VI VO R = F VI RG RL RF VO GD = +20V/V –3 GD = +30V/V –6 –12 RG = 50Ω VO = 400mVPP –15 +5V GD = +40V/V GD = +50V/V –9 RF Adjusted –18 10 OPA847 100 1000 Frequency (MHz) –5V DIS DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE GD = 40V/V GD = 40V/V VO = 4VPP F = 5MHz Harmonic Distortion (dBc) –60 32 Gain (dB) DIFFERENTIAL DISTORTION vs LOAD RESISTANCE –55 35 VO = 400mVPP VO = 5VPP 29 VO = 8VPP 26 –65 –70 –75 2nd-Harmonic –80 –85 –90 –95 3rd-Harmonic –100 –105 –110 23 1 10 100 1000 50 100 150 Frequency (MHz) 350 400 450 500 GD = 40V/V RL = 400Ω F = 5MHz –80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 300 DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE –75 GD = 40V/V RL = 400Ω VO = 4VPP –75 250 Resistance (Ω) DIFFERENTIAL DISTORTION vs FREQUENCY –65 200 2nd-Harmonic –85 –95 3rd-Harmonic –105 –85 2nd-Harmonic –90 –95 –100 3rd-Harmonic –105 –115 –110 1 10 100 1 Frequency (MHz) OPA847 SBOS251C 10 Differential Output Voltage Swing (VPP) www.ti.com 9 APPLICATIONS INFORMATION WIDEBAND, NONINVERTING OPERATION The OPA847 provides a unique combination of a very low input voltage noise along with a very low distortion output stage to give one of the highest dynamic range op amps available. Its very high gain bandwidth product (GBP) can be used to either deliver high signal bandwidths at high gains, or to deliver very low distortion signals at moderate frequencies and lower gains. To achieve the full performance of the OPA847, careful attention to PC board layout and component selection is required, as discussed in the following sections of this data sheet. Figure 1 shows the noninverting gain of a +20V/V circuit used as the basis for most of the Typical Characteristics. Most of the curves are characterized using signal sources with a 50Ω driving impedance and with measurement equipment presenting a 50Ω load impedance. In Figure 1, the 50Ω shunt resistor at the VI terminal matches the source impedance of the test generator, while the 50Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet voltage swing specifications are at the output pin (VO in Figure 1) while output power specifications are at the matched 50Ω load. The total 100Ω load at the output combined with the 790Ω total feedback network load presents the OPA847 with an effective output load of 89Ω for the circuit of Figure 1. Voltage-feedback op amps, unlike current-feedback designs, can use a wide range of resistor values to set their gain. The circuit of Figure 1, and the specifications at other gains, use an RG set to 39.2Ωand RF adjusted to get the desired gain. Using this guideline ensures that the noise added at the output due to the Johnson noise of the resistors does not significantly increase the total over that due to the 0.85nV/√Hz input WIDEBAND, INVERTING GAIN OPERATION There can be significant benefits to operating the OPA847 as an inverting amplifier. This is particularly true when a matched input impedance is required. Figure 2 shows the inverting gain of a –40V/V circuit used as a starting point for the Typical Characteristics showing inverting mode performance. Driving this circuit from a 50Ω source, and constraining the gain resistor (RG) to equal 50Ω, gives both a signal bandwidth and a noise advantage. RG, in this case, acts as both the input termination resistor and the gain setting resistor for the circuit. Although the signal gain for the circuit of Figure 2 is double that for Figure 1, their noise gains are nearly equal when the 50Ω source resistor is included. This has the interesting effect of approximately doubling the equivalent GBP for the amplifier. This can be seen by observing that the gain of –40 bandwidth of 240MHz shown in the Typical Characteristics implies a gain bandwidth product of 9.6GHz, giving a far higher bandwidth at a gain of –40 than at a gain of +40. While the signal gain from RG to the output is –40, the noise gain for bandwidth setting purposes is 1 + RF/(2 • RG). In the case of a –40V/V gain, using an RG = RS = 50Ω gives a noise gain = 1 + 2kΩ/100Ω = 21. This inverting gain of –40V/V therefore has a frequency response that more closely matches the gain of a +20 frequency response. If the signal source is actually the low impedance output of another amplifier, RG should be increased to be greater than the minimum value allowed at the output for that amplifier and RF adjusted to get the desired gain. It is critical for stable operation of the OPA847 that this driving amplifier show a very low output impedance through frequencies exceeding the expected closed-loop bandwidth for the OPA847. WIDEBAND, HIGH SENSITIVITY, TRANSIMPEDANCE DESIGN +5V +VS 0.1µF voltage noise for the op amp itself. This RG is suggested as a good starting point for design. Other values are certainly acceptable, if required by the design. +5V +VS 6.8µF + 0.1µF 50Ω Source VDIS VI 50Ω 50Ω Load VO OPA847 + 6.8µF VDIS 50Ω 0.01µF RF 750Ω 50Ω Source RG 50Ω VO 95.3Ω 50Ω Load 50Ω OPA847 RF 2kΩ VI RG 39.2Ω + 6.8µF 0.1µF 0.1µF 6.8µF –VS –5V –VS –5V FIGURE 1. Noninverting G = +20 Specification and Test Circuit. 10 + FIGURE 2. Noninverting G = –40 Specification and Test Circuit. OPA847 www.ti.com SBOS251C The high GBP and low input voltage and current noise for the OPA847 make it an ideal wideband transimpedance amplifier for low to moderate transimpedance gains. Very high transimpedance gains (> 100kΩ) will benefit from the low input noise current of a JFET input op amp such as the OPA657. Unity-gain stability in the op amp is not required for application as a transimpedance amplifier. Figure 3 shows one possible transimpedance design example that would be particularly suitable for the 155Mbit data rate of an OC-3 receiver. Designs that require high bandwidth from a large area detector with relatively low transimpedance gain will benefit from the low input voltage noise for the OPA847. The amplifier’s input voltage noise is peaked up over frequency by the diode source capacitance, and can (in many cases) become the limiting factor to input sensitivity. The key elements to the design are the expected diode capacitance (CD) with the reverse bias voltage (–VB) applied, the desired transimpedance gain (RF), and the GBP for the OPA847 (3900MHz). With these three variables set (including the parasitic input capacitance for the OPA847 added to CD), the feedback capacitor value (CF) can be set to control the frequency response. To achieve a maximally flat 2nd-order Butterworth frequency response, set the feedback pole as shown in Equation 1. +5V Power-supply decoupling not shown. 100pF 0.1µF 12kΩ OPA847 VDIS –5V λ 1pF Photodiode RF 12kΩ CF 0.18pF –VB FIGURE 3. Wideband, High Sensitivity, OC-3 Transimpedance Amplifier. 1 GBP = 2 πR F C F 4 πR F C D (1) Adding the common-mode and differential mode input capacitance (1.2 + 2.5)pF to the 1pF diode source capacitance of Figure 3, and targeting a 12kΩ transimpedance gain using the 3900MHz GBP for the OPA847 requires a feedback pole set to 74MHz to get a nominal Butterworth frequency response design. This requires a total feedback capacitance of 0.18pF. That total is shown in Figure 3, but recall that typical surface-mount resistors have a parasitic capacitance of 0.2pF, leaving no external capacitor required for this design. Equation 2 gives the approximate –3dB bandwidth that results if CF is set using Equation 1. f − 3 dB = (2) The example of Figure 3 gives approximately 104MHz flat bandwidth using the 0.18pF feedback compensation capacitor. This bandwidth easily supports an OC-3 receiver with exceptional sensitivity. If the total output noise is bandlimited to a frequency less than the feedback pole frequency, a very simple expression for the equivalent input noise current is shown as Equation 3. iEQ = iN2 + 4kT RF e 2 (e 2πCD F)2 + N + N 3 RF (3) where: iEQ = Equivalent input noise current if the output noise is bandlimited to F < 1/(2πRFCF) iN = Input current noise for the op amp inverting input eN = Input voltage noise for the op amp CD = Total Inverting Node Capacitance f = Bandlimiting frequency in Hz (usually a post filter prior to further signal processing) Evaluating this expression up to the feedback pole frequency at 74MHz for the circuit of Figure 3 gives an equivalent input noise current of 3.0pA/√Hz. This is slightly higher than the 2.5pA/√Hz input current noise for the op amp. This total equivalent input current noise is slightly increased by the last term in the equivalent input noise expression. It is essential in this case to use a low-voltage noise op amp. For example, if a slightly higher input noise voltage, but otherwise identical, op amp were used instead of the OPA847 in this application (say 2.0nV/√Hz), the total input referred current noise would increase to 3.7pA/√Hz. Low input voltage noise is required for the best sensitivity in these wideband transimpedance applications. This is often unspecified for dedicated transimpedance amplifiers with a total output noise for a specified source capacitance given instead. It is the relatively high input voltage noise for those components that cause higher than expected output noise if the source capacitance is higher than specified. The output DC error for the circuit of Figure 3 is minimized by including a 12kΩ to ground on the noninverting input. This reduces the contribution of input bias current errors (for total output offset voltage) to the offset current times the feedback resistor. To minimize the output noise contribution of this resistor, 0.01µF and 100pF capacitors are included in parallel. Worst-case output DC error for the circuit of Figure 3 at 25°C is: Vos = ±0.5mV (input offset voltage) ± 0.6uA (input offset current) • 12kΩ = ±7.2mV Worst-case output offset DC drift (over the 0°C to 70°C span) is: dVos/dT = ±1.5µV/°C (input offset drift) ± 2nA/°C (input offset current drift) • 12kΩ = ±21.5µV/°C. OPA847 SBOS251C GBP (Hz ) 2 πR F C D www.ti.com 11 Even with bias current cancellation, the output DC errors are dominated in this example by the offset current term. Improved output DC precision and drift are possible, particularly at higher transimpedance gains, using the JFET input OPA657. The JFET input removes the input bias current from the error equation (eliminating the need for the resistor to ground on the noninverting input), leaving only the input offset voltage and drift as an output DC error term. Included in the Typical Characteristics are transimpedance frequency response curves for a fixed 20kΩ gain over various detector diode capacitance settings. These curves are repeated in Figure 4, along with the test circuit. As the photodiode capacitance changes, the feedback capacitor must change to maintain a stable and flat frequency response. Using Equation 1, CF is adjusted to give the Butterworth frequency responses shown in Figure 4. Considering only the noise gain (which is the same as the noninverting signal gain) for the circuit of Figure 5, the lowfrequency noise gain (NG1) is set by the resistor ratio, while the high-frequency noise gain (NG2) is set by the capacitor ratio. The capacitor values set both the transition frequencies and the high-frequency noise gain. If the high-frequency noise gain, determined by NG2 = 1 + CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp, and the noise gain pole (set by 1/RFCF) is placed correctly, a very well controlled 2nd-order low-pass frequency response results. +5V VDIS OPA847 PHOTODIODE TRANSIMPEDANCE FREQUENCY RESPONSE Transimpedance Gain (dBΩ) 89 RF = 20kΩ CF Adjusted [20 log(20kΩ)] 86 CD = 10pF VI CS 39pF CF 1.7pF –5V 80 0.01µF 77 FIGURE 5. Broadband, Low-Inverting Gain External Compensation. VO 20kΩ OPA847 20kΩ IO CD 74 CF 71 1 10 100 Frequency (MHz) FIGURE 4. Transimpedance Bandwidth vs CD. LOW-GAIN COMPENSATION FOR IMPROVED SFDR Where a low gain is desired, and inverting operation is acceptable, a new external compensation technique can be used to retain the full slew rate and noise benefits of the OPA847, while giving increased loop gain and the associated distortion improvements offered by a non-unity-gain stable op amp. This technique shapes the loop gain for good stability, while giving an easily controlled 2nd-order low-pass frequency response. This technique is used for the circuit on the front page of this data sheet in a differential configuration to achieve extremely low distortion through high frequencies (< –90dBc through 30MHz). The amplifier portion of this circuit is set up for a differential gain of 8.5V/V from a differential input signal to the output. Using the input transformer shown improves the noise figure and translates from a single-ended to a differential signal. If the source is differential already, it can be fed directly into the gain setting resistors. To set the compensation capacitors (CS and CF), consider the half circuit of Figure 5, where the 50Ω source is reflected through the 1:2 transformer, then cut in half, and grounded to give a total impedance to the AC ground for the circuit on the front page equal to 200Ω. 12 RF 850Ω CD = 20pF CD = 50pF CD = 100pF 83 RG 200Ω VO To choose the values for both CS and CF, two parameters and only three equations need to be solved. The first parameter is the target high-frequency noise gain (NG2), which should be greater than the minimum stable gain for the OPA847. Here, a target of NG2 = 24 is used. The second parameter is the desired low-frequency signal gain, which also sets the low-frequency noise gain (NG1). To simplify this discussion, we will target a maximally flat 2nd-order low-pass Butterworth frequency response (Q = 0.707). The signal gain shown in Figure 5 sets the low-frequency noise gain to NG1 = 1 + RF/RG (= 5.25 in this example). Then, using only these two gains and the GBP for the OPA847 (3900MHz), the key frequency in the compensation is set by Equation 4. ZO= GBP NG 21 NG 1 1− NG 2 NG 1 − 1− 2 NG 2 (4) Physically, this ZO (4.4MHz for the values shown above) is set by 1/(2πRF(CF + CS)) and is the frequency at which the rising portion of the noise gain would intersect the unity gain if projected back to a 0dB gain. The actual zero in the noise gain occurs at NG1 • ZO and the pole in the noise gain occurs at NG2 • ZO. That pole is physically set by 1/(RFCF). Since GBP is expressed in Hz, multiply ZO by 2π and use to get CF by solving Equation 5. CF = 1 (= 1.76pF ) 2πRF Z O NG2 (5) OPA847 www.ti.com SBOS251C Finally, since CS and CF set the high-frequency noise gain, determine CS using Equation 6 (solving for CS by using NG2 = 24): C S = (NG 2 − 1)C F LOW GAIN INVERTING BANDWIDTH 1 (6) 0 Normalized Gain (1dB) which gives CS = 40.6pF. Both of these calculated values have been reduced slightly in Figure 5 to account for parasitics. The resulting closedloop bandwidth is approximately equal to Equation 7. f – 3 dB ≅ Z O •GBP (7) For the values shown in Figure 5, f–3dB is approximately 131MHz. This is less than that predicted by simply dividing the GBP product by NG1. The compensation network controls the bandwidth to a lower value, while providing the full slew rate at the output and an exceptional distortion performance due to increased loop gain at frequencies below NG1 • ZO. –1 –2 G = –8 VO = 0.2VPP –3 –4 G = –1 –5 –6 G = –2 –7 –8 –9 1 10 100 +5V VDIS OPA847 The Typical Characteristics show the exceptional bandwidth control possible using this technique at low inverting gains. Figure 6 repeats the measured results with the test circuit shown. LOW-NOISE FIGURE, HIGH DYNAMIC RANGE AMPLIFIER The low input noise voltage of the OPA847 and its very high 2-tone, 3rd-order intermodulation intercept can be used to good advantage as a fixed-gain amplifier. While input noise 1000 Frequency (MHz) Using this low-gain inverting compensation, along with the differential structure for the circuit shown on the front page of this data sheet, gives a significant reduction in harmonic distortion. The measured distortion at 2VPP output does not rise above –95dB until frequencies > 20MHz are applied. The compensation capacitors, CS and CF, are set by targeting a high-frequency noise gain of 21 and using equations 4 through 6. This approach allows relatively low inverting gain applications to use the full slew rate and low input noise of the OPA847. G = –4 RG –5V VO RF 750Ω VI 0Ω Source CS CF FIGURE 6. Low-Gain Inverting Performance. figures in the 10dB range (for a matched 50Ω input) are easily achieved with just the OPA847, Figure 7 illustrates a technique to reduce the noise figure even further, while providing a broadband, high-gain HF amplifier stage using two stages of the OPA847. 6.19kΩ +5V Input match set by this feedback path +5V –5V 50Ω Source PI 750Ω 1:2 1.5kΩ > 55dBm intercept to 30MHz OPA847 200Ω 4.3dB Noise Figure PO OPA847 10pF 1.6pF –5V 46pF 420Ω 30.1Ω Overall Gain PO PI = 35.6dB FIGURE 7. Very High Dynamic Range HF Amplifier. OPA847 SBOS251C www.ti.com 13 This circuit uses two stages of forward gain with an overall feedback loop to set the input impedance match. The input transformer provides both a noiseless voltage gain and a signal inversion to retain an overall noninverting signal path from PI to PO. The second amplifier stage is inverting to provide the correct feedback polarity through the 6.19kΩ resistor. To achieve a 50Ω input match at the primary of the 1:2 transformer, the secondary must see a 200Ω load impedance. At higher frequencies, the match is provided by the 200Ω resistor in series with 10pF. The low-noise figure (4.3dB) for this circuit is achieved by using the transformer, the low-voltage noise OPA847, and the input match set by the feedback at lower frequencies intended for this HF design. The 1st-stage amplifier provides a gain of +15V/V. The very high SFDR is provided by operating the output stage at a low signal gain of –2 and using the inverting compensation technique to shape the noise gain to hold it stable. This 2nd-stage compensation is set to intentionally bandlimit the overall response to approximately 100MHz. For output loads > 400Ω, this circuit can give a 2-tone SFDR that exceeds 90dB through 30MHz. In narrowband applications, the 3rd-order intercept exceeds 55dBm. Besides offering a very high dynamic range, this circuit improves on standard HF amplifiers by offering a precisely controlled gain and a very flexible output interface capability. +5V VI Figure 8 shows a resistor based compensation technique that allows the flatness at low noninverting signal gains to be controlled separately from the signal gain. This approach retains the full slew rate to the output but gives up some of the low-noise benefit of the OPA847. Including the effect of the total source impedance (25Ω in Figure 8), tuning resistor R1 can be set using Equation 8. R1 = R F + RS AV NG − A V where, AV = desired signal gain (+12V/V in Figure 8) NG = target noise gain (adjusted in Figure 9) RS = total source impedance 14 (8) 50Ω 50Ω R1 50Ω OPA847 VO –5V RF 750Ω RG 66.5Ω FIGURE 8. Low Noninverting Gain Flatness Trim. The effect of this noninverting gain flatness tune is shown in Figure 9. At an NG of 12, R1 is removed and only RF and RG are present in Figure 8. The peaking is typically 4.5dB, as shown in the small-signal frequency response curves versus gain curves at this setting. As R1 is decreased, the operating noise gain (NG) increases, reducing the peaking and bandwidth until the nominal design point of +20 noise gain gives a non-peaked response. NONINVERTING GAIN FLATNESS TUNE NONINVERTING GAIN FLATNESS COMPENSATION 0.5 Deviation from 21.58dB Gain (0.1dB) Decreasing the operating gain from the nominal design point of +20 decreases the phase margin. This increases Q for the closed-loop poles, peaks up the frequency response, and extends the bandwidth. A peaked frequency response shows overshoot and ringing in the pulse response, as well as higher integrated output noise. When operating the OPA847 at a noninverting gain < +12V/V, increased peaking and possible sustained oscillations may result. However, operation at low gains may be desirable to take advantage of the higher slew rate and exceptional DC precision of the OPA847. Numerous external compensation techniques are suggested for operating a high-gain op amp at low gains. Most of these give zero/pole pairs in the closed-loop response that cause long term settling tails in the pulse response and/or phase nonlinearity in the frequency response. VDIS VO = 200mVPP AV = +12V/V NG = Noise Gain 0.4 0.3 NG = 12 NG = 14 NG = 16 0.2 0.1 0 –0.1 NG = 18 –0.2 NG = 20 –0.3 –0.4 –0.5 1 10 100 1000 Frequency (MHz) FIGURE 9. Frequency Response Flatness with External Tuning Resistor. DIFFERENTIAL OPERATION Operating two OPA847 amplifiers in a differential inverting configuration can further suppress even-order harmonic terms. The Typical Characteristics show measured performance for this condition. These measurements were done at the relatively high gain of 40V/V. Even lower distortion is possible operating at lower gains using the external inverting compensation techniques, as discussed previously. For the distortion data presented in Figure 10, the output swing is increased to 4VPP into 400Ω to allow direct comparison to the single-channel data at 2VPP into 200Ω. Comparing the 2nd- and 3rd-harmonics at 20MHz in Figure 10 to the gain of +20, 2VPP, 200Ω data, shows the 2nd-harmonic is reduced to –76dBc (from –67dBc) and the 3rd-harmonic is reduced from –80dBc to –85dBc. Using the two OPA847 www.ti.com SBOS251C Harmonic Distortion (dBc) –65 OPA847 can support this mode of operation down to a single supply of +5V and up to a single supply of +12V. If shutdown is desired for single-supply operation, it is important to realize that the shutdown pin is referenced from the positive supply pin. Open collector (drain) interfaces are suggested for single-supply operation above +5V. GD = 40V/V RL = 400Ω VO = 4VPP –75 2nd-Harmonic –85 DESIGN-IN TOOLS –95 3rd-Harmonic DEMONSTRATION BOARDS –105 –115 1 10 100 Frequency (MHz) FIGURE 10. Differential Distortion vs Frequency. amplifiers in this configuration has significantly reduced the 2nd-harmonic, even after doubling the output voltage swing (to 4VPP) and the gain (to 40V/V). Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA847 in its two package styles. Both of these are available, free, as unpopulated PC boards delivered with descriptive documentation. The summary information for these boards is shown in Table I. Contact your sales representative or go to the TI web site (www.ti.com) to request these evaluation boards. PRODUCT SINGLE-SUPPLY OPERATION The OPA847 can be operated from a single power supply if system constraints require it. Operation from a single +5V to +12V supply is possible with minimal change in AC performance. The Typical Characteristics show the input and output voltage ranges for a bipolar supply range from ±2.5V to ±6.0V. The Common-Mode Input Range and Output Swing vs Supply Voltage curve shows that the required headroom on both the input and output pins remains at approximately 1.5V over this entire range. On a single +5V supply, for instance, this means the noninverting input should remain centered at +2.5V ± 1V, as should the output pin. Figure 11 shows an example application biasing the noninverting input at mid-supply and running an AC-coupled input to the inverting gain path. Since the gain resistor is blocked off for DC, the bias point on the noninverting input appears at the output, centering up the output as well as on the power supply. The OPA847ID OPA847IDBV PACKAGE BOARD PART NUMBER LITERATURE REQUEST NUMBER SO-8 SOT23-6 DEMOPA68XU DEMOPA6XXN SBOU009 SBOU010 TABLE I. Demo Board Part Numbers. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the OPA847 in its intended application. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role in circuit performance. A SPICE model for the OPA847 is available through the TI web site (www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. OPERATING SUGGESTIONS +VCC SETTING RESISTOR VALUES TO MINIMIZE NOISE +5V 2RF 0.01µF 2RF +12V Range Power-supply decoupling not shown. V R VO = CC – VI F OPA847 2 RG VDIS RG RF VI FIGURE 11. Single-Supply Inverting Amplifier. The OPA847 provides a very low input noise voltage while requiring a low 18.1mA of quiescent current. To take full advantage of this low input noise, careful attention to the other possible noise contributors is required. See Figure 12 for the op amp noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise power. This computation adds all the contributing noise powers at the output by superposition, then takes the square OPA847 SBOS251C www.ti.com 15 ENI EO OPA847 RS IBN ERS RF √4kTRS IBI RG 4kT RG √4kTRF 4kT = 1.6E – 20J at 290°K FIGURE 12. Op Amp Noise Analysis Model. root to get back to a spot noise voltage. Equation 9 shows the general form for this output noise voltage using the terms illustrated in Figure 11. (9) EO = (E2NI + (IBNRS)2 + 4kTRS)NG2 + (IBIRF)2 + 4kTRFNG Dividing this expression by the noise gain (NG = 1 + RF/RG) gives the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 10. (10) 2 + (I BN R S )2 + 4 kTR E N = E NI S I R 2 4 kTR + BI F + NG NG F Putting high resistor values into Equation 10 can quickly dominate the total equivalent input referred noise. A 45Ω source impedance on the noninverting input adds a Johnson voltage noise term equal to the amplifier’s voltage noise by itself. As a simplifying constraint, set RG = RS in Equation 10 and assume an RS/2 source impedance at the noninverting input, where RS is the signal source impedance and another matching RS to ground is at the noninverting input. This results in Equation 11, where NG > 12 is assumed to further simplify the expression. EN= 2 E NI + 5 (IB R S )2 + 4 kT 3 R S 4 2 (11) Evaluating this expression for RS = 50Ω gives a total equivalent input noise of 1.4nV/√Hz. Note that at these higher gains, the simplified input referred spot noise expression of Equation 11 does not include the gain. This is a good approximation for NG > 12, as is typically required by stability considerations. FREQUENCY RESPONSE CONTROL Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the Electrical Characteristics. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) predicts the closed-loop bandwidth. In 16 practice, this only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At low gains (increased feedback factors), most high-speed amplifiers exhibit a more complex response with lower phase margin. The OPA847 is compensated to give a maximally flat 2nd-order Butterworth closed-loop response at a noninverting gain of +20 (see Figure 1). This results in a typical gain of +20 bandwidth of 350MHz, far exceeding that predicted by dividing the 3900MHz GBP by 20. Increasing the gain causes the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +50, the OPA847 very nearly matches the 78MHz bandwidth predicted using the simple formula and the typical GBP of 3900MHz. Inverting operation offers some interesting opportunities to increase the available GBP. When the source impedance is matched by the gain resistor (see Figure 2), the signal gain is (1 + RF/RG), while the noise gain for bandwidth purposes is (1 + RF/2RG). This cuts the noise gain almost in half, increasing the minimum operating gain for inverting operation under these condition to –22 and the equivalent gain bandwidth product to > 7.8GHz. DRIVING CAPACITIVE LOADS One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC, including additional external capacitance that may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA847 can be very susceptible to decreased stability and may give closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem are suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics help the designer pick a recommended RS versus capacitive load. The resulting frequency response curves show a flat response for several selected capacitive loads and recommended RS combinations. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA847. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully and add the recommended series resistor as close as possible to the OPA847 output pin (see the Board Layout section). OPA847 www.ti.com SBOS251C The OPA847 has an extremely low 3rd-order harmonic distortion. This also gives a high 2-tone 3rd-order intermodulation intercept, as shown in the Typical Characteristics. This intercept curve is defined at the 50Ω load when driven through a 50Ω matching resistor to allow direct comparisons to RF devices. This matching network attenuates the voltage swing from the output pin to the load by 6dB. If the OPA847 drives directly into the input of a highimpedance device, such as an ADC, this 6dB attenuation is not taken. Under these conditions, the intercept as reported in the Typical Characteristics increases by a minimum of 6dBm. The intercept is used to predict the intermodulation spurious power levels for two closely spaced frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and ∆F = |f2 – f1| /2, the two 3rd-order, close-in spurious tones appear at fO ± 3 • ∆F. The difference between the two equal test-tone power levels and these intermodulation spurious power levels is given by ∆dBc = 2(IM3 – PO), where IM3 is the intercept taken from the Typical Characteristics and PO is the power level in dBm at the 50Ω load for one of the two closely spaced test frequencies. For instance, at 30MHz, the OPA847 at a gain of +20 has an intercept of 34dBm at a matched 50Ω load. The OPA847 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of its low ±0.5mV input offset voltage, careful attention to the input bias current cancellation is also required. The low-noise input stage for the OPA847 has a relatively high input bias current (19µA typical into the pins), but with a very close match between the two input currents—typically ±100nA input offset current. Figures 13 and 14 show typical distributions of input offset voltage and current for the OPA847. 1200 Mean = 48µV Standard Deviation = 110µV Total Count = 4040 1000 800 600 400 200 0 < –600 < –540 < –480 < –420 < –360 < –300 < –240 < –180 < –120 < –60 0 < 60 < 120 < 180 < 240 < 300 < 360 < 420 < 480 < 540 < 600 > 600 Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration this is the sum of RF + RG, while in the inverting configuration this is only RF (see Figure 2). Increasing the output voltage swing increases harmonic distortion directly. A 6dB increase in output swing generally increases the 2ndharmonic 12dB and the 3rd-harmonic 18dB. Increasing the signal gain also increases the 2nd-harmonic distortion. Finally, the distortion increases as the fundamental frequency increases due to the rolloff in the loop gain with frequency. Conversely, the distortion improves going to lower frequencies down to the dominant open-loop pole at approximately 80kHz. DC ACCURACY AND OFFSET CONTROL µV FIGURE 13. Input Offset Voltage Distribution in µV. 900 800 700 Mean = 50nA Standard Deviation = 120nA Total Count = 4040 600 500 400 300 200 100 0 < –600 < –540 < –480 < –420 < –360 < –300 < –240 < –180 < –120 < –60 0 < 60 < 120 < 180 < 240 < 300 < 360 < 420 < 480 < 540 < 600 > 600 The OPA847 is capable of delivering an exceptionally low distortion signal at high frequencies over a wide range of gains. The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions. Most of these plots are limited to a 110dB dynamic range. The OPA847’s distortion driving a 200Ω load does not rise above –90dBc until either the signal level exceeds 2.0VPP and/or the fundamental frequency exceeds 5MHz. Distortion in the audio band is < –130dBc. Count DISTORTION PERFORMANCE If the full envelope of the two frequencies needs to be 2VPP, this requires each tone to be 4dBm. The 3rd-order intermodulation spurious tones will then be 2(34 – 4) = 60dBc below the test-tone power level (–56dBm). If this same 2VPP 2-tone envelope is delivered directly into the input of an ADC without the matching loss or the loading of the 50Ω network, the intercept would increase to at least 40dBm. With the same signal and gain conditions, but now driving directly into a light load, the spurious tones will then be at least 2(40 – 4) = 72dBc below the 4dBm test-tone power levels centered on 30MHz. Tests have shown that they are in fact much lower due to the lighter loading presented by most ADCs. Count The criterion for setting the RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA847 operating in a gain of +20, the frequency response at the output pin is very flat to begin with, allowing relatively small values of RS to be used for low capacitive loads. As the signal gain is increased, the unloaded phase margin also increases. Driving capacitive loads at higher gains requires lower RS values than those shown for a gain of +20. nA FIGURE 14. Input Offset Current Distribution in nA. OPA847 SBOS251C www.ti.com 17 The total output offset voltage can be considerably reduced by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 is to insert a 12.1Ω series resistor into the noninverting input from the 50Ω terminating resistor. When the 50Ω source resistor is DC coupled, this increases the source impedance for the noninverting input bias current to 37.1Ω. Since this is now equal to the impedance looking out of the inverting input (RF || RG) for Figure 1, the circuit cancels the gains for the bias currents to the output, leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using the 750Ω feedback resistor, this output error is now less than ±0.85µA • 750Ω = ±640µV over the full temperature range for the circuit of Figure 1, with a 12.1Ω resistor added as described. The output DC offset is then dominated by the input offset voltage multiplied by the signal gain. For the circuit of Figure 1, this is a worst-case output DC offset of ±0.6mV • 20 = ±12mV over the full temperature range. A fine-scale output offset null, or DC operating point adjustment, is sometimes required. Numerous techniques are available for introducing a DC offset control into an op amp circuit. Most of these techniques eventually reduce to setting up a DC current through the feedback resistor. One key consideration to selecting a technique is to ensure that it has a minimal impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input can be considered. For a DC-coupled inverting input signal, this DC offset signal sets up a DC current back into the source that must be considered. An offset adjustment placed on the inverting op amp input can also change the noise gain and frequency response flatness. Figure 15 shows one example of an offset adjustment for a DC-coupled signal path that has minimum impact on the signal frequency response. In this case, the input is brought into an inverting gain resistor with the DC adjustment as an additional current summed into the inverting node. The resistor values setting this offset adjustment are much larger than the signal path resistors. This ensures that this adjustment has minimal impact on the loop gain and, hence, the frequency response. POWER SHUTDOWN OPERATION The OPA847 provides an optional power shutdown feature that can be used to reduce system power. If the V DIS control pin is left unconnected, the OPA847 operates normally. This shutdown is intended only as a power saving feature. Forward path isolation is very good for small signals. Large signal isolation is not ensured. Using this feature to multiplex two or more outputs together is not recommended. Large signals applied to the shutdown output stages can turn on parasitic devices, degrading signal linearity for the desired channel. Turn-on time is very quick from the shutdown condition, typically < 60ns. Turn-off time is strongly dependent on the external circuit configuration, but is typically 200ns for the circuit of Figure 1. Using the OPA847 with higher external resistor values, such has high-gain transimpedance circuits, slows the shutdown time since the time constants for the internal nodes to discharge are longer. To shutdown, the control pin must be asserted low. This logic control is referenced to the positive supply, as shown in the simplified circuit of Figure 16. +VS 8kΩ Q1 +5V VCC Power-supply decoupling not shown. 48Ω 0.1µF OPA847 17kΩ VDIS VEE –5V +5V RG 50Ω VI ±200mV Output Adjustment 100Ω 0.1µF 5kΩ VO VI =– RF RG = –20V/V –5V FIGURE 15. DC-Coupled, Inverting Gain of –20 with Output Offset Adjustment. 18 IS Control –VS FIGURE 16. Simplified Shutdown Control Circuit. RF 1kΩ 5kΩ 20kΩ 120kΩ VO In normal operation, base current to Q1 is provided through the 120kΩ resistor, while the emitter current through the 8kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As V DIS is pulled low, additional current is pulled through the 8kΩ resistor, eventually turning on these two diodes ( ≈180µA). At this point, any further current pulled out of V DIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the shutdown mode is only that required to operate the circuit of Figure 16. OPA847 www.ti.com SBOS251C The shutdown feature for the OPA847 is a positive-supply referenced, current-controlled interface. Open-collector (or drain) interfaces are most effective, as long as the controlling logic can sustain the resulting voltage (in open mode) that appears at the V DIS pin. The V DIS pin voltage is one diode below the positive supply voltage applied to the OPA847 if the logic voltage is open. For voltage output logic interfaces, the on/off voltage levels described in the Electrical Characteristics apply only for a +5V supply. An open-drain interface is recommended for a shutdown operation using a higher positive supply and/or logic families with inadequate highlevel voltage swings. THERMAL ANALYSIS The OPA847 does not require heatsinking or airflow in most applications. Maximum desired junction temperature sets the maximum allowed internal power dissipation, as described here. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to half either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 • RL), where RL includes feedback network loading. This is the absolute highest power that can be dissipated for a given RL. All actual applications dissipate less power in the output stage. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA847IDBV (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 100Ω load. Maximum internal power is: PD = 10V • 18.9mA + 52/(4(100Ω || 789Ω)) = 259mW Maximum TJ = +85°C + (0.26W • 150°C/W) = 124°C All actual applications will operate at a lower junction temperature than the 124°C computed above. Compute your actual output stage power to get an accurate estimate of maximum junction temperature, or use the results shown here as an absolute maximum. BOARD LAYOUT Achieving optimum performance with a high-frequency amplifier like the OPA847 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, create a window around the signal I/O pins in all of the ground and power planes around these pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These can be placed somewhat further from the device and can be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components preserves the high-frequency performance of the OPA847. Use resistors that have low reactance at high frequencies. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 2.0kΩ, this parasitic capacitance can add a pole and/or zero below 400MHz that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. It has been suggested here that a good starting point for design would be to set RG to 39.2Ω. Doing this automatically keeps the resistor noise terms low, and minimizes the effect of their parasitic capacitance. Transimpedance applications can use much higher resistor values. The compensation techniques described in this data sheet allow excellent frequency response control, even with very high feedback resistor values. d) Connections to other wideband devices on the board can be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the OPA847 SBOS251C www.ti.com 19 plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 4pF) may not need an RS, since the OPA847 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases from +20V/V (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doublyterminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary onboard and, in fact, a higher impedance environment improves distortion, as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA847 is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source-end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA847 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an ex- 20 tremely troublesome parasitic network that can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA847 onto the board. INPUT AND ESD PROTECTION The OPA847 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protec- +VCC External Pin Internal Circuitry –VCC FIGURE 17. Internal ESD Protection. tion diodes to the power supplies, as shown in Figure 17. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA847), current limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and frequency response. OPA847 www.ti.com SBOS251C PACKAGE DRAWINGS D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 OPA847 SBOS251C www.ti.com 21 PACKAGE DRAWINGS (Cont.) DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE 0,95 6X 6 0,50 0,25 0,20 M 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0 –8 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-5/G 01/02 NOTES: A. B. C. D. 22 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation. OPA847 www.ti.com SBOS251C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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