® OPA2686 OPA 268 6 Dual, Wideband, Low Noise, Voltage Feedback OPERATIONAL AMPLIFIER TM FEATURES APPLICATIONS ● HIGH GAIN BANDWIDTH: 1.6GHz ● LOW NOISE, DIFFERENTIAL AMPLIFIERS ● LOW INPUT VOLTAGE NOISE: 1.4nV/√Hz ● VERY LOW DISTORTION: –90dBc (5MHz) ● xDSL RECEIVER AMPLIFIER ● ULTRASOUND HIGH GAIN PREAMP ● LOW SUPPLY CURRENT: 12mA/chan. ● HIGH CHANNEL ISOLATION: 70dB ● DIFFERENTIAL ADC PREAMP ● MATCHED I AND Q CHANNEL AMPLIFIERS ● ±5V OPERATION ● STABLE FOR GAINS ≥ +7 ● MATCHED TRANSIMPEDANCE AMPLIFIERS ● PROFESSIONAL AUDIO DUAL TRANSIMPEDANCE DESCRIPTION The OPA2686 provides two very low noise, high gain bandwidth, voltage feedback op amps in a single package. Operating from a low 12mA/channel quiescent current, each channel provides a 1.4nV/√Hz input voltage noise with a 1.6GHz gain bandwidth product. Minimum stable gain is specified at +7V/V while exceptional flatness is guaranteed at a gain of +10. The combination of low noise, high slew rate (600V/µs), and broad bandwidth allow exceptional xDSL differential receivers to be implemented. Additionally, de-compensated, low-noise voltage-feedback op amps are ideal for broadband transimpedance requirements. The dual channel OPA2686 provides matched channels for high speed differencing transimpedance requirements. With over 200MHz bandwidth at a gain of 20dB, excellent gain and phase matching is provided at IF frequencies for matched I and Q channel amplifiers. OPA2686 RELATED PRODUCTS SINGLES INPUT NOISE VOLTAGE (nV/√Hz) GAIN BANDWIDTH PRODUCT (MHz) OPA643 2.3 800 OPA686 1.3 1600 OPA687 0.95 3600 1/2 OPA2686 RG RF RG RF Passive Filter Analog Front End Diplexer 1/2 OPA2686 Driver Low Noise VDSL Receiver International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1998 Burr-Brown Corporation SBOS064 1 PDS-1371B OPA2686 Printed in U.S.A. May, 2000 SPECIFICATIONS: VS = ±5V RF = 453Ω, RL = 100Ω, and G =+10, unless otherwise noted. Figure 1 for AC performance. OPA2686U TYP PARAMETER AC PERFORMANCE (Figure 1) Closed-Loop Bandwidth Gain Bandwidth Product (GBP) Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +7 Harmonic Distortion 2nd Harmonic GUARANTEED CONDITIONS +25°C +25°C(2) 0°C to 70°C (3) –40°C to +85°C (3) G = +7, RG = 50Ω, VO = 200mVp-p G = +10, RG = 50Ω, VO = 200mVp-p G = +20, RG = 50Ω, VO = 200mVp-p G ≥ +40 G = +10, RL = 100Ω, VO = 200mVp-p 425 250 100 1600 40 2 200 80 1250 35 170 65 1100 30 140 55 1000 25 –67 –85 –90 –105 40 1.6 2.3 1.75 500 –65 –80 –85 –100 39 1.7 2.4 2 400 –60 –75 –80 –95 37 1.8 2.5 2.5 310 14 12 21 14 25 18 Two-Tone, 3rd-Order Intercept Input Voltage Noise Input Current Noise Rise/Fall Time Slew Rate Settling Time to 0.01% 0.1% 1% G = +10, f = 5MHz, VO = 2Vp-p R L = 100Ω R L = 500Ω R L = 100Ω R L = 500Ω G = +10, f = 10MHz f > 1MHz f > 1MHz 0.2V Step 2V Step 2V Step 2V Step 2V Step –72 –90 –95 –110 43 1.4 1.8 1.4 600 18 16 11 Differential Gain Differential Phase Channel-to-Channel Crosstalk G = +10, NTSC, RL = 150Ω G = +10, NTSC, RL = 150Ω Input Referred, f = 5MHz 0.02 0.02 –70 DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift VO = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V 80 ±0.35 ±1.0 –10 –17 ±0.5 ±1.0 ±3.2 100 ±3.0 VCM = 0V, Input Referred VCM = 0V VCM = 0V 6 || 2 2.9 || 1 ≥ 400Ω Load 100Ω Load VO = 0V VO = 0V G = +10, f = 100kHz ±3.5 ±3.3 80 –80 0.008 3rd Harmonic INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection (CMR) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio +PSRR, –PSRR THERMAL CHARACTERISTICS Specified Operating Range: U, N Package Thermal Resistance, θJA 75 90 ±3.2 ±3.0 UNITS MIN/ TEST MAX LEVEL(1) MHz MHz MHz MHz MHz dB typ min min min min typ C B B B B C dBc dBc dBc dBc dBm nV/√Hz pA/√Hz ns V/µs ns ns ns max max max max min max max max min typ max max B B B B B B B B B C B B % deg dBc typ typ typ C C C 70 ±1.2 5 –18 50 ±1.5 5 70 ±1.5 10 –20 100 ±1.8 10 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B ±2.9 85 ±2.8 75 V dB min min A A kΩ || pF MΩ || pF typ typ C C V V mA mA Ω min min min min typ A A A A C ±3.1 ±2.8 55 –55 ±3.0 ±2.8 50 –40 ±6 27.8 22 V V mA mA typ max max min C A A A 65 dB min A –40 to +85 °C typ C 125 °C/W typ C ±5 60 –60 ±6 VS = ±5V VS = ±5V 24.8 24.8 25.8 23.8 ±6 26 23.8 |VS| = 4.5 to 5.5, Input Referred 78 70 70 Junction-to-Ambient U SO-8 Surface Mount NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ±CMIR limits. ® OPA2686 2 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation ...................................... See Thermal Analysis Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: U ..................................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C Top View SO-8 OPA2686 ELECTROSTATIC DISCHARGE SENSITIVITY Out A 1 8 V+ –In A 2 7 Out B +In A 3 6 –In B V– 4 5 +In B This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPA2686U " SO-8 Surface Mount " 182 " TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA –40°C to +85°C " OPA2686U " OPA2686U OPA2686U/2K5 Rails Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA2686U/2K5” will get a single 2500-piece Tape and Reel. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA2686 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +10, RF = 453Ω, and RL = 100Ω, unless otherwise noted. NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 RG = 50Ω VO = 0.2Vp-p 6 Normalized Gain (3dB/div) –3 G = +10 –6 –9 G = +50 –12 G = +20 –15 –18 –21 0 –6 –12 –15 –18 –21 100 0.5 100 Frequency (MHz) NON-INVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 500 30 26 17 23 Gain (3dB/div) 20 14 VO = 1Vp-p 11 8 VO = 2Vp-p 5 VO = 5Vp-p RG = RS = 50Ω G = –20V/V 29 VO = 0.2Vp-p VO = 0.2Vp-p 20 VO = 1Vp-p 17 VO = 2Vp-p 14 VO = 5Vp-p 11 8 2 5 See Figure 1 See Figure 2 2 –4 0.5 10 100 0.1 500 10 100 Frequency (MHz) Frequency (MHz) NON-INVERTING PULSE RESPONSE INVERTING PULSE RESPONSE Right Scale Small Signal ±100mV 0 Left Scale 1.5 1.0 0.5 0 –0.5 –100 –1.0 –1.5 Output Voltage (100mV/div) Large Signal ±1V 100 500 G = –20V/V Output Voltage (500mV/div) G = +10V/V Output Voltage (100mV/div) 10 Frequency (MHz) RG = 50Ω G = +10V/V 23 Gain (3dB/div) See Figure 2 –24 500 26 –1 G = –20 G = –50 –9 –24 10 G = –12 –3 See Figure 1 0.5 RG = RS = 50Ω VO = 0.2Vp-p 3 0 Large Signal ±1V Right Scale 100 Small Signal ±100mV 0 Left Scale Time (5ns/div) OPA2686 4 0.5 0 –1.0 –1.5 Time (5ns/div) ® 1.0 –0.5 –100 See Figure 2 See Figure 1 1.5 Output Voltage (500mV/div) Normalized Gain (3dB/div) 3 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE G = +7 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +10, RF = 453Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. 5MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE 5MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 RL = 100Ω 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –60 –70 –80 –90 RL = 500Ω RL = 200Ω –100 –70 –80 RL = 100Ω –90 RL = 200Ω –100 RL = 500Ω –110 –110 0.1 1 10 0.1 10MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE 10MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –55 –60 –60 RL = 100Ω 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) 10 Output Voltage (Vp-p) –55 –65 –70 –75 –80 –85 RL = 500Ω RL = 200Ω –90 –95 –100 –65 –70 –75 RL = 100Ω –80 –85 RL = 200Ω RL = 500Ω –90 –95 –100 –105 –105 0.1 1 10 0.1 1 10 Output Voltage (Vp-p) Output Voltage (Vp-p) 20MHz 2nd HARMONIC DISTORTION vs OUTPUT VOLTAGE 20MHz 3rd HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 –50 –55 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) 1 Output Voltage (Vp-p) RL = 100Ω –60 –65 –70 –75 RL = 500Ω –80 –85 RL = 200Ω –55 –60 RL = 100Ω –65 –70 RL = 500Ω –75 –80 RL = 200Ω –85 –90 –90 –95 –95 0.1 1 0.1 10 1 10 Output Voltage (Vp-p) Output Voltage (Vp-p) ® 5 OPA2686 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +10, RF = 453Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. 3rd HARMONIC DISTORTION vs FREQUENCY 2nd HARMONIC DISTORTION vs FREQUENCY –45 VO = 2Vp-p RL = 100Ω –55 G = +50V –65 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –45 G = +20 –75 G = +10 –85 –95 VO = 2Vp-p RL = 100Ω –55 G = +50 –65 G = +20 –75 –85 G = +10 –95 –105 –105 1 10 1 20 10 20 Frequency (MHz) Frequency (MHz) INPUT VOLTAGE and CURRENT NOISE DENSITY TWO-TONE, 3rd-0RDER INTERMODULATION INTERCEPT vs FREQUENCY 50 10 Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) 45 Intercept (dBm) 40 Current Noise 1.8pA/√Hz 35 30 PI 50Ω PO OPA2686 50Ω 25 50Ω 453Ω 20 1.4nV/√Hz 50Ω 15 Voltage Noise 0 1 100 1k 10k 100k 1M 10M 0 5 10 15 Frequency (Hz) RS vs CAPACITIVE LOAD 25 30 35 40 45 50 FREQUENCY RESPONSE vs CAPACITIVE LOAD 22 Gain to Capacitive Load (1dB/div) 60 50 40 RS (Ω) 20 Frequency (MHz) 30 20 10 CL = 10pF 21 20 CL = 20pF 19 CL = 50pF 18 17 CL = 100pF VIN 16 RS VO OPA2686 15 453Ω CL 1kΩ 14 50Ω 13 1kΩ is optional 12 0 1 10 1 100 Capacitive Load (pF) Frequency (MHz) ® OPA2686 10 6 100 500 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +10, RF = 453Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. POWER SUPPLY and OUTPUT CURRENT vs TEMPERATURE 80 –30 | AOL| 70 –60 ∠ AOL 60 –90 50 –120 40 –150 30 –180 20 –210 10 0 1k 10k 100k 1M 10M 100M 120 24 Output Current Sourcing 100 20 16 12 60 8 40 –240 4 20 –270 0 1G 0 –50 –25 0 25 50 75 100 125 Temperature (°C) INPUT DC ERRORS vs TEMPERATURE CMRR and PSRR 13 1.3 110 CMRR 100 Input Bias Current 1.1 11 +PSRR 90 80 –PSRR 70 VOS (mV) Power Supply Rejection Ratio (dB) 80 Output Current Sinking Frequency (Hz) 60 50 0.9 9 0.7 7 5 0.5 Offset Voltage 40 3 0.3 30 0.1 20 1 Input Offset Current –1 –0.1 10 100 1k 10k 100k 1M 10M –50 100M 25 50 75 100 CLOSED-LOOP OUTPUT IMPEDANCE DIFFERENTIAL and COMMON-MODE INPUT IMPEDANCE 107 50Ω OPA2686 ZO 453Ω 0.1 50Ω 0.01 0.001 10k 0 Temperature (°C) Input Impedance (Ω) 1.0 –25 Frequency (Hz) 10 Output Impedance (Ω) 140 Power Supply Current Input Bias and Input Offset Current (µA) 100 28 Output Current (mA) 0 Power Supply Current (mA) 90 Open-Loop Phase (30°/div) Open-Loop Gain (10dB/div) OPEN-LOOP GAIN and PHASE 125 Common-Mode 106 105 Differential 104 103 100k 1M 10M 100 100M 1k 10k 100k 1M 10M 10M Frequency (Hz) Frequency (Hz) ® 7 OPA2686 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +10, RF = 453Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. CHANNEL-TO-CHANNEL CROSSTALK –25 Input Referred G = +10, Both Channels RL = 100Ω Crosstalk (10dB/div) –35 –45 –55 –65 –75 –85 –95 –105 1 10 Frequency (MHz) ® OPA2686 8 100 APPLICATIONS INFORMATION WIDEBAND, INVERTING GAIN OPERATION Operating the OPA2686 as an inverting amplifier has several benefits and is particularly appropriate when a matched input impedance is required. Figure 2 shows the inverting gain circuit used as the basis of the inverting mode Typical Performance Curves. WIDEBAND, NON-INVERTING OPERATION The OPA2686 provides a unique combination of features— low input voltage noise along with a very low distortion output stage—to give one of the highest, dynamic range dual op amps available. Its very high Gain Bandwidth Product (GBP) can be used either to deliver high signal bandwidths at high gains, or to deliver very low distortion signals at moderate frequencies and lower gains. To achieve the full performance of the OPA2686, careful attention to PC board layout and component selection is required as discussed in the remaining sections of this data sheet. +5V +VS 0.1µF Figure 1 shows the non-inverting gain of +10 circuit used as the basis of the Electrical Specifications and most of the Typical Performance Curves. Most of the curves were characterized using signal sources with 50Ω driving impedance, and with measurement equipment presenting a 50Ω load impedance. In Figure 1, the 50Ω shunt resistor at the VI terminal matches the source impedance of the test generator, while the 50Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet voltage swing specifications are at the output pin (VO in Figure 1), while output power (dBm) specifications are at the matched 50Ω load. The total 100Ω load at the output, combined with the 503Ω total feedback network load, presents the OPA2686 with an effective output load of 83Ω for the circuit of Figure 1. 0.1µF 50Ω Source 50Ω Load 50Ω RF 453Ω RG 50Ω + 6.8µF 6.8µF Driving this circuit from a 50Ω source, and constraining the gain resistor (RG) to equal 50Ω, will give both a signal bandwidth and noise advantage. R G acts as both the input termination resistor and the gain setting resistor for the circuit. Although the signal gain (VO/VI) for the circuit of Figure 2 is double that for Figure 1, the noise gains are in fact equal when the 50Ω source resistor is included. This has the interesting effect of doubling the equivalent GBP of the amplifier. This can be seen in comparing the G = +10 and G = –20 small-signal frequency response curves. Both show approximately 250MHz bandwidth, but the inverting configuration of Figure 2 gives 6dB higher signal gain. If the signal source is actually the low impedance output of another amplifier, RG should be increased to the minimum load resistance value allowed for that amplifier and RF should be adjusted to achieve the desired gain. For stable operation of the OPA2686, it is critical that this driving amplifier show a very low output impedance at frequencies beyond the expected closed-loop bandwidth for the OPA2686. 6.8µF + 1/2 OPA2686 + FIGURE 2. Inverting, G = –20 Characterization Circuit. 50Ω Source 50Ω 50Ω Load –VS –5V +VS VO 50Ω RF 1kΩ 0.1µF +5V VI VO 1/2 OPA2686 6.8µF VI Voltage feedback op amps, unlike current feedback designs, can use a wide range of resistor values to set their gains. The circuit of Figure 1, and the specifications at other gains, use the constraint that RG should always be set to 50Ω and RF adjusted to get the desired gain. Observing this guideline will ensure that the thermal noise constribution of the feedback network is insignificant compared to the 1.4nV/√Hz input voltage noise for the op amp itself. 0.1µF RG 50Ω 91Ω + LOW NOISE VDSL RECEIVER Most xDSL transceiver channels are differential for both the driver and the receiver. The low noise, high gain bandwidth and low distortion for the dual OPA2686 make it an ideal receiver channel element for the demanding requirements emerging in VDSL. One possible implementation is shown on the front page of this data sheet. This circuit is assuming full duplex communication using frequency division multiplexing with send-and-receive isola- 0.1µF –VS –5V FIGURE 1. Non-Inverting, G = +10 Specification and Test Circuit. ® 9 OPA2686 tion improved through the use of a diplexer line interface. The differential receive signal is brought into the inverting channel gain resistors to get both noise and distortion improvement for a given desired gain setting. To get impedance matching, set 2R G equal to the required load looking out of the diplexer. The signal gain is then set by adjusting feedback resistors, RF. Using the OPA2686 in the inverting mode will give you a reduced noise gain as described in the “Wideband, Inverting Gain Operation” section of this data sheet. This will improve both the SNR and distortion performance. If the noise gain for a particular application drops below the minimum recommended stable gain (+7), consider using the Low Gain Compensation technique described later in this data sheet. a parasitic capacitance of 0.2pF, leaving the required 0.3pF value shown in Figure 3 to get the required feedback pole. This will give a –3dB bandwidth approximately equal to: f–3dB = √(GBP/2πRFCD)Hz Eq. 2 The example of Figure 3 will give approximately 44MHz flat bandwidth using the 0.3pF feedback compensation. If the total output noise is bandlimited to a frequency less than the feedback pole frequency, a very simple expression for the equivalent input noise current can be derived as: (E N 2 πC D F) 4 kT E N + + RF RF 3 2 I EQ = I 2N + SINGLE-STAGE TRANSIMPEDANCE DESIGN When setting up either one or both stages as a broadband photodiode amplifier, the key elements in the design are the expected diode capacitance (CD) with the reverse bias voltage (–VB) applied, the desired transimpedance gain RF, and the GBP of the OPA2686 (1600MHz). Figure 3 shows a design using a 10pF source capacitance diode and a 10kΩ transimpedance gain. With these three variables set (and including the parasitic input capacitance for the OPA2686 added to CD), the feedback capacitor value (CF) may be set to control the frequency response. 2 Eq. 3 Where: IEQ = Equivalent input noise current if the output noise is bandlimited to F < 1/(2πRFCD) IN = Input current noise for the op amp inverting input EN = Input voltage noise for the op amp CD = Diode capacitance F = Bandlimiting frequency in Hz (usually a post filter prior to further signal processing) Evaluating this expression up to the feedback pole frequency at 31MHz for the circuit of Figure 3 gives an equivalent input noise current of 2.6pA/√Hz. This is only slightly higher than the current noise of the op amp itself. +5V Supply Decoupling Not Shown 1/2 OPA2686 TWO-STAGE TRANSIMPEDANCE DESIGN VO = ID RF The dual OPA2686 may be used as either a dual transimpedance channel from two photodectors or as a very high gain stage by using one amplifier as the transimpedance stage with the second used as a post gain amplifier. Figure 4 shows an example of using one channel as a transimpedance front end from a large area detector, with the second amplifier used as a voltage gain stage to get a 100kΩ total gain (ZT) from a large 50pF detector, (CD in Figure 4). RF 10kΩ λ ID CD 10pF –5V CF 0.3pF –VB One key question in this design is how best to split up the first and second stage gains. If bandwidth optimization from a given photodetector capacitance (CD in Figure 4) is the FIGURE 3. Wideband, Low Noise, Transimpedance Amplifier. To achieve a maximally flat 2nd-order Butterworth frequency response, the feedback pole should be set to: 1/(2πRFCF) = √(GBP/(4πRFCD)) Eq. 1 0.1µF Adding the common-mode and differential mode input capacitance (1.0 + 2.0)pF to the 10pF diode source capacitance of Figure 3, and targeting a 10kΩ transimpedance gain using the 1600MHz GBP for the OPA2686, will require a feedback pole set to 31MHz. This will require a total feedback capacitance of 0.5pF. Typical surface-mount resistors have 2.67kΩ 1/2 OPA2686 20Ω 1/2 OPA2686 2.67kΩ λ CD 50pF 732Ω 20Ω 1.9pF –VB FIGURE 4. High Gain, Wideband Transimpedance Amplifier. ® OPA2686 10 primary goal, Equation 4 gives a solution for RF in the input stage that will provide an equal bandwidth in the first and second stages, giving the maximum overall channel bandwidth. Z 2T RF = 2 π C D GBP 1/ 3 the resistor ratios while the high frequency noise gain (NG2) will be set by the capacitor ratios. The capacitor values set both the transition frequencies and the high frequency noise gain. If this noise gain, determined by NG2 = 1+CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp and the noise gain pole, set by 1/RFCF, is placed correctly, a very well controlled 2nd-order low pass frequency response will result. Eq. 4 Where: ZT = Desired total transimpedance gain CD = Diode capacitance at reverse bias To choose the values for both CS and CF, two parameters and only three equations need to be solved. The first parameter is the target high frequency noise gain NG2, which should be greater than the minimum stable gain for the OPA2686. Here, a target NG2 of 10.5 will be used. The second parameter is the desired low frequency signal gain, which also sets the low frequency noise gain NG1. To simplify this discussion, we will target a maximally flat second-order low pass Butterworth frequency response (Q = 0.707). The signal gain of –2 shown in Figure 5 will set the low frequency noise gain to NG1 = 1 + RF/RG (NG1= 3 in this example). Then, using only these two gains and the GBP for the OPA2686 (1600MHz), the key frequency in the compensation can be determined as: GBP = Amplifier Gain Bandwidth Product (MHz) This equation is used to calculate the required input stage feedback resistor in Figure 4. The remaining total signal gain is provided by the second stage; in the example of Figure 4, setting G = 37.5 gives the same bandwidth (approximately 42MHz) as the bandwidth achieved by the input stage. To set this first stage bandwidth to its maximally flat values, use Equation 5 to set the feedback capacitor value: Eq. 5 CD CF = π R F GBP f–3dB = 1 2 (GBP) ZO = Eq. 6 2/3 (2 π C D )1 / 3 (Z T )1 / 3 GBP NG12 NG1 NG1 1 – – 1– 2 NG 2 NG 2 Eq. 7 Physically, this Z0 (10.6MHz for the values shown above) is set by 1/(2π • RF(CF + CS)) and is the frequency at which the rising portion of the noise gain would intersect unity gain if projected back to 0dB gain. The actual zero in the noise gain occurs at NG1 • Z0 and the pole in the noise gain occurs at NG2 • Z0. Since GBP is expressed in Hz, multiply Z0 by 2π and use this to get CF by solving: The approximate achievable bandwidth in the two stages is given by Equation 6 which gives approximately 30MHz for Figure 4. LOW GAIN COMPENSATION FOR IMPROVED SFDR Where a low gain is desired, and inverting operation is acceptable, a new external compensation technique may be used to retain the full slew rate and noise benefits of the OPA2686 while giving increased loop gain and the associated improvement in distortion offered by the decompensated architecture. This technique shapes the loop gain for good stability while giving an easily controlled secondorder low pass frequency response. Considering only the noise gain (non-inverting signal gain) for the circuit of Figure 5, the low frequency noise gain, (NG1) will be set by CF = 1 (= 2.86pF) 2π • R F Z O NG 2 Eq. 8 Finally, since CS and CF set the high frequency noise gain, determine CS by: C S = ( NG 2 – 1) C F (= 27.2pF) Eq. 9 The resulting closed-loop bandwidth will be approximately equal to: +5V f –3dB ≅ Z O GBP 1/2 OPA2686 RG 250Ω Eq. 10 For the values shown in Figure 5, the f –3dB will be approximately 130MHz. This is less than that predicted by simply dividing the GBP product by NG1. The compensation network controls the bandwidth to a lower value while providing the full slew rate at the output and an exceptional distortion performance due to increased loop gain at frequencies below NG1 • Z0. The capacitor values shown in Figure 5 are calculated for NG1 = 3 and NG2 = 10.5 with no adjustment for parasitics. VO RF 500Ω VI CS 27pF (= 130MHz) CF 2.9pF –5V FIGURE 5. Broadband Low Gain Inverting External Compensation. ® 11 OPA2686 DC-COUPLED, SINGLE-TO-DIFFERENTIAL ADC DRIVER Figure 6 shows the measured frequency response for the circuit of Figure 5. This shows the expected gain of –2 (6dB) with exceptional flatness through 70MHz and a –3dB bandwidth of 170MHz. Measured distortion into a 100Ω load shows > 5dB improvement through 20MHz over the performance shown in the Typical Performance Curves. Into a 500Ω load, the 5MHz, 2Vp-p, 2nd harmonic improves from –85dBc to –92dBc. Many very high performance CMOS ADCs are intended to operate with a differential input signal. Translating a single-ended source to this differential input while controlling the common-mode operating voltage can present a considerable challenge where high SFDR is required. Figure 7 shows one way to do this where very low harmonic distortion is required and good common-mode control is desired. 12 This particular example is set for a signal gain of 4 from the single-ended input to the differential output voltage. Since the common-mode control signal (from the output of the OPA680) is fed into the midpoint of the two gain resistors (124Ω), this DC control path requires a very low source impedance through high frequencies to maintain the desired signal path gain. A wideband, unity gain stable, voltage-feedback op amp like the OPA680 makes an ideal choice to provide this low output impedance DC control signal. This op amp also compares the output common-mode voltage to the desired V CM, and servos the OPA2686 common-mode output voltage to that value using an integrator loop. This holds the output commonmode voltage precisely at VCM while giving the low output impedance required of the circuit. 9 Gain (3dB/div) 6 3 0 170MHz –3 –6 –9 –12 –15 –18 1 10 100 500 Frequency (MHz) FIGURE 6. Low Noise Figure IF Amplifier. Power Supply De-Coupling Not Shown +5V +5V 130Ω 357Ω VI 78.7Ω 100Ω Input Impedance 20Ω +2.5V ±2VI 1/2 OPA2686 V+ 80pF 24pF 357Ω 10kΩ 14-Bit 10MSPS +5V 2.2pF 124Ω 100Ω 0.1µF 25.5Ω OPA680 5kΩ +5V VCM 1µF 357Ω 124Ω 2.2pF –5V 0.1µF 10kΩ 357Ω 191Ω 20Ω 1/2 OPA2686 24pF 49.9Ω +2.5V ±2V –5V FIGURE 7. DC-Coupled, Single-to-Differential High SFDR ADC Driver. ® OPA2686 12 V– 80pF Each side of the OPA2686 in this circuit is operating at a relatively low noise gain. To hold excellent frequency response flatness, the inverting gain compensation capacitors are included at the inverting nodes and across the feedback resistors, as described in the “Low Gain Compensation for Improved SFDR” section in this data sheet. Operating at +2.5V common-mode requires a DC level shifting current through the feedback resistors. Since this current is to the supply midpoint, pull-up resistors equal to the feedback resistors are connected to the positive supply to keep the output stage signal currents equal and bipolar. This significantly improves 2nd harmonic distortion. In this case, the 2nd harmonic distortion is still dominant due to slight signal path imbalances—even though this circuit does provide matched noise gain. The distortion levels, however, are very low. Thus, narrowband applications which are impacted by only 3rd-order terms will see very low single- and two-tone distortion levels. AC-COUPLED, SINGLE-TO-DIFFERENTIAL ADC DRIVER Where the signal path may be AC-coupled, a very balanced, high SFDR dual op amp interface circuit can easily be provided by the OPA2686. Figure 9 shows a specific example of this application where the input single-to-differential conversion is provided by an input transformer. Once the signal source is purely differential, the circuit of Figure 9 provides low harmonic distortion with a common-mode control path that does not interact with the signal path gain. If the source is already differential, such as at the output of a balanced mixer, the input transformer could be replaced by blocking capacitors. To deliver a 2Vp-p differential input signal on a 2.5V common-mode voltage, each output must swing between 2.0V and 3.0V. Tested harmonic distortion performance for this condition from 1MHz to 10MHz is shown in Figure 8. Harmonic Distortion (dBc) –70 –75 In the example of Figure 9, the secondary of the transformer is connected into the two inverting path gain resistors (100Ω). These resistors provide both an input impedance match (assuming a 50Ω source on the primary of this 1:2 step-up transformer) and set the signal gain for each amplifier along with the 500Ω feedback resistors. Although relatively high signal gain is provided by this circuit (10 in this case), each amplifier is operating at a relatively low noise gain (3.5 at DC). This low noise gain at low frequencies gives high loop gain for distortion suppression in the baseband. External compensation capacitors (18pF and 2.1pF) are included to hold the frequency response flat, as described in the “Low Gain 2nd Harmonic –80 3rd Harmonic –85 –90 –95 1 10 Frequency (MHz) FIGURE 8. Harmonic Distortion vs Frequency for the Circuit of Figure 7. Power Supply De-Coupling Not Shown VCM 1000pF +5V 20Ω 1/2 OPA2686 V+ 80pF 18pF 2.1pF 14-Bit 10MSPS 500Ω 1:2 100Ω 500Ω VI 2.5V 50Ω VCM VCM +10VI 100Ω 500Ω 1µF 2.1pF 500Ω Single-to-Differential Gain of 10 18pF VCM 20Ω 1/2 OPA2686 V– 80pF 1000pF –5V FIGURE 9. AC-Coupled, Single-to-Differential High SFDR ADC Driver. ® 13 OPA2686 Compensation For Improved SFDR” section of this data sheet. The common-mode operating voltage is fed into each amplifier’s non-inverting input. Since these are equal, and will appear at each inverting input as well, no DC current is produced through the transformer secondary due to this common-mode operating voltage. Since no current flows due to VCM, the output will operate at VCM as well. This is one of the few common-mode operating point control techniques that requires no current to flow. This makes the common-mode control aspect of this circuit essentially non-interactive with the signal path. To provide a 2Vp-p differential signal operating at a 2.5V output common-mode requires a 2.0V to 3.0V output swing on each output. Tested performance over frequency for the circuit of Figure 9 is shown in Figure 10. centered output swing, but increases as the output is shifted to a +2.5V DC output. Narrowband systems, where a bandpass filter less than an octave wide can be inserted between the amplifier and the converter, will only be concerned about two-tone, 3rd-order intermodulation distortion. Since this bandpass filter is also AC-coupled, the outputs of Figure 9 may be operated ground centered, giving the extremely low 3rd-order distortions shown in Figure 10. DESIGN-IN TOOLS DEMONSTRATION BOARDS A PC board is available to assist in the initial evaluation of circuit performance using the OPA2686. It is available free as an unpopulated PC board delivered with descriptive documentation. The summary information for this board is shown in the table below. –70 Harmonic Distortion (dBc) VO = 2Vp-p Differential 2nd Harmonic 0V and +2.5V DC –80 –90 PRODUCT PACKAGE BOARD PART NUMBER OPA2686U SO-8 Surface Mount DEM-OPA268xU LITERATURE REQUEST NUMBER MKT-352 +2.5V DC 3rd Harmonic –100 Contact the Burr-Brown applications support line to request this board. 0V DC –110 1 MACROMODELS AND APPLICATIONS SUPPORT 10 Frequency (MHz) Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2686 is available through either the Burr-Brown Internet web page (http://www.burrbrown.com) or as one model on a disk from the Burr-Brown Applications department (1-800-548-6132). The Applications department is also available for design assistance at this number. These models do a good job of predicting smallsignal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. FIGURE 10. Harmonic Distortion for Figure 9. Figure 10 shows 2nd and 3rd harmonic distortion for a 2Vp-p differential output swing at both 0V output common-mode voltage and +2.5V common-mode voltage. Since there is no DC current required from the output to level shift to +2.5V in this circuit, no pull-up resistors to the power supply were used as in the circuit of Figure 7. The 2nd harmonic remains the dominant distortion mechanism, but shows little sensitivity to the common-mode operating voltage (improved 2nd harmonic distortion results were achieved with this circuit using two individual OPA686N’s with an extremely symmetrical layout). The 3rd harmonic is essentially unmeasureable for the ground ® OPA2686 14 OPERATING SUGGESTIONS 12 and assume an RS/2 source impedance at the noninverting input (where RS is the signal’s source impedance with another matching RS to ground on the non-inverting input). This results in Equation 13, where NG > 10 has been assumed to further simplify the expression. SETTING RESISTOR VALUES TO MINIMIZE NOISE The OPA2686 provides a very low input noise voltage while requiring a low 12mA/channel quiescent current. To take full advantage of this low input noise, careful attention to the other possible noise contributors is required. Figure 11 shows the op amp noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. EN = 1/2 OPA2686 RF IBI RG √ 4kTRF 4kT = 1.6E –20J at 290°K FIGURE 11. Op Amp Noise Analysis Model. The total output spot noise voltage can be computed as the square root of the squared contributing terms to the output noise voltage. This computation adds all the contributing noise powers at the output by superposition, then takes the square root to get back to a spot noise voltage. Equation 11 shows the general form for this output noise voltage using the terms shown in Figure 11. Eq. 11 EO = (E 2 NI ) Inverting operation offers some interesting opportunities to increase the available GBP. When the source impedance is matched by the gain resistor (Figure 2), the signal gain is (1+RF /RG) while the noise gain for bandwidth purposes is (1 + RF /2RG). This cuts the noise gain almost in half, increasing the minimum stable gain for inverting operation under these condition to –12 and the equivalent GBP to 3.2GHz. + (I BN R S ) + 4 kTR S NG 2 + (I BI R F ) + 4 kTR F NG 2 Eq. 13 Voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the GBP shown in the specifications. Ideally, dividing GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factor), most high speed amplifiers will exhibit a more complex response with lower phase margin. The OPA2686 is compensated to give a maximally flat 2nd-order Butterworth closed-loop response at a non-inverting gain of +10 (Figure 1). This results in a typical gain of +10 bandwidth of 250MHz, far exceeding that predicted by dividing the 1600MHz GBP by 10. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +40, the OPA2686 will show the 40MHz bandwidth predicted using the simple formula and the typical GBP of 1600MHz. ERS 4kT RG 3R S 2 FREQUENCY RESPONSE CONTROL EO IBN √ 4kTRS 5 Evaluating this expression for RS = 50Ω will give a total equivalent input noise of 1.7nV/√Hz. Note that the NG has dropped out of this expression. This is valid only for NG > 10. ENI RS (E NI )2 + 4 (I BR S )2 + 4 kT 2 Dividing this expression by the noise gain (NG = 1+RF/RG) will give the equivalent input-referred spot noise voltage at the non-inverting input as shown in Equation 12. Eq. 12 2 I R 4 kTR F 2 E N = E NI 2 + (I BN R S ) + 4 kTR S + BI F + NG NG DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance which may be recommended to improve A/D linearity. A high speed, high open-loop gain amplifier like the OPA2686 can be very susceptible to decreased stability and closed-loop response peaking when Inserting high resistor values into Equation 12 can quickly dominate the total equivalent input referred noise. A 105Ω source impedance on the non-inverting input will add a thermal voltage noise term equal to that of the amplifier itself. As a simplifying constraint, set RG = RS in Equation ® 15 OPA2686 a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. improve going to lower frequencies down to the dominant open-loop pole at approximately 100kHz. Starting from the –82dBc 2nd harmonic for a 5MHz, 2Vp-p fundamental into a 200Ω load at G = +10 (from the Typical Performance Curves), the 2nd harmonic distortion for frequencies lower than 100kHz will be approximately –82dBc – 20log(5MHz/ 100kHz) = –116dBc. The OPA2686 has extremely low 3rd-order harmonic distortion. This also gives a high two-tone, 3rd-order intermodulation intercept as shown in the Typical Performance Curves. This intercept curve is defined at the 50Ω load when driven through a 50Ω matching resistor to allow direct comparisons to RF MMIC devices. This matching network attenuates the voltage swing from the output pin to the load by 6dB. If the OPA2686 drives directly into the input of a high impedance device, such as an ADC, the 6dB attenuation is not taken. Under these conditions, the intercept will increase by a minimum 6dBm. The intercept is used to predict the intermodulation spurious for two, closelyspaced frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, f O = (f1 + f2)/2 and ∆f = |f2 – f1|/2, the two 3rd-order, close-in spurious tones will appear at fO ±3 • ∆f. The difference between two equal test-tone power levels and these intermodulation spurious power levels is given by ∆dBc = 2 • (IM3 – PO) where IM3 is the intercept taken from the Typical Performance Curve and PO is the power level in dBm at the 50Ω load for one of the two closelyspaced test frequencies. For instance, at 5MHz the OPA2686 at a gain of +10 has an intercept of 48dBm at a matched 50Ω load. If the full envelope of the two frequencies needs to be 2Vp-p, this requires each tone to be 4dBm. The 3rd-order intermodulation spurious tones will then be 2 • (48 – 4) = 88dBc below the test-tone power level (–84dBm). If this same 2Vp-p, two-tone envelope were delivered directly into the input of an ADC—without the matching loss or the loading of the 50Ω network—the intercept would increase to at least 54dBm. With the same signal and gain conditions, but now driving directly into a light load, the spurious tones will then be at least 2 • (54 – 4) = 100dBc below the 4dBm test-tone power levels centered on 5MHz. The Typical Performance Curves show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2686. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2686 output pin (see Board Layout Guidelines). The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA2686 operating in a gain of +10, the frequency response at the output pin is very flat to begin with, allowing relatively small values of RS to be used for low capacitive loads. As the signal gain is increased, the unloaded phase margin will also increase. Driving capacitive loads at higher gains will require lower RS values than those shown for a gain of +10. DISTORTION PERFORMANCE The OPA2686 is capable of delivering an exceptionally low distortion signal at high frequencies over a wide range of gains. The distortion plots in the Typical Performance Curves show the typical distortion under a wide variety of conditions. Most of these plots are limited to 110dB dynamic range. Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd harmonic will dominate the distortion with negligible a 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the non-inverting configuration, this is sum of RF + RG, while in the inverting configuration, it is just RF (Figures 1 and 2). Increasing output voltage swing increases harmonic distortion directly. A 6dB increase in output swing will generally increase the 2nd harmonic 12dB and the 3rd harmonic 18dB. Increasing the signal gain will also increase the 2nd harmonic distortion. Again, a 6dB increase in gain will increase the 2nd and 3rd harmonic by approximately 6dB even with constant output power and frequency. Finally, the distortion increases as the fundamental frequency increases due to the rolloff in the loop gain with frequency. Conversely, the distortion will DC ACCURACY AND OFFSET CONTROL The OPA2686 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of its low ±1.5mV input offset voltage, careful attention to input bias current cancellation is also required. The low noise input stage of the OPA2686 has a relatively high input bias current (10µA typical into the pins) but with a very close match between the two input currents—typically ±100nA input offset current. The total output offset voltage may be reduced considerably by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 20Ω series resistor into the noninverting input from the 50Ω terminating resistor. When the ® OPA2686 16 THERMAL ANALYSIS 50Ω source resistor is DC-coupled, this will increase the source resistances for the non-inverting input bias current to 45Ω. Since this is now equal to the resistance looking out of the inverting input (RF || RG), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using the 453Ω feedback resistor, this output error will now be less than ±0.9µA • 453Ω = ±0.4mV over the full temperature range. The OPA2686 will not require heatsinking or airflow in most applications. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +175°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 • RL) where RL includes feedback network loading. A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing a DC offset control into an op amp circuit. Most of these techniques eventually reduce to setting up a DC current through the feedback resistor. One key consideration to selecting a technique is to insure that it has a minimal impact on the desired signal path frequency response. If the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the non-inverting input can be considered. For a DC-coupled inverting input signal, this DC offset signal will set up a DC current back into the source that must be considered. An offset adjustment placed on the inverting op amp input can also change the noise gain and frequency response flatness. Figure 12 shows one example of an offset adjustment for a DC-coupled signal path that will have minimum impact on the signal frequency response. In this case, the input is brought into an inverting gain resistor with the DC adjustment an additional current summed into the inverting node. The resistor values setting this offset adjustment are much larger than the signal path resistors. This will insure that this adjustment has minimal impact on the loop gain and hence, the frequency response. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using both channels of the OPA2686U in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 100Ω load at +2.5VDC: PD = 10V • (27.8mA) + 2 • [52/(4 • (100Ω || 500Ω))] = 428mW Maximum TJ = +85°C + (0.428W • 125°C/W) = 139°C This absolute worst-case example will never be encountered in practice. Therefore, 139°C sets an upper limit to maximum junction temperature. BOARD LAYOUT Achieving optimum performance with a high frequency amplifier like the OPA2686 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: +5V Supply Decoupling Not Shown 0.1µF 48Ω 1/2 OPA2686 a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the non-inverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. VO –5V +5V RG 50Ω RF 1kΩ VI 5kΩ 20kΩ ±200mV Output Adjustment b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. 10kΩ 0.1µF 5kΩ VO VI =– RF RG = –20 –5V FIGURE 12. DC-Coupled, Inverting Gain of –20, with Output Offset Adjustment. ® 17 OPA2686 c) Careful selection and placement of external components will preserve the high frequency performance of the OPA2686. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axiallyleaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or a zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. It has been suggested here that a good starting point for design would be to set RG to 50Ω. Doing this will automatically keep the resistor noise terms low, and minimize the effect of their parasitic capacitance. terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high speed part like the OPA2686 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2686 onto the board. INPUT AND ESD PROTECTION The OPA2686 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies as shown in Figure 13. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA2686 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doublyterminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA2686 is used as well as a +V CC External Pin –V CC FIGURE 13. Internal ESD Protection. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA2686), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. ® OPA2686 Internal Circuitry 18 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated