CADEKA SPT7734SCS

SPT7734
8-BIT, 40 MSPS,175 mW A/D CONVERTER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
• All High-Speed Applications Where
Low Power Dissipation is Required
• Video Imaging
• Medical Imaging
• Radar Receivers
• IR Imaging
• Digital Communications
Monolithic 40 MSPS Converter
175 mW Power Dissipation
On-Chip Track-and-Hold
Single +5 V Power Supply
TTL/CMOS Outputs
5 pF Input Capacitance
Low Cost
Tri-State Output Buffers
High ESD Protection: 3,500 V Minimum
Selectable +3 V or +5 V Logic I/O
GENERAL DESCRIPTION
The SPT7734 is a 8-bit monolithic, low cost, ultralow power
analog-to-digital converter capable of minimum word rates
of 40 MSPS. The on-chip track-and-hold function assures
very good dynamic performance without the need for external components. The input drive requirements are minimized due to the SPT7734's low input capacitance of only
5 pF.
Power dissipation is extremely low at only 175 mW typical at
40 MSPS with a power supply of +5.0 V. The digital outputs
BLOCK DIAGRAM
AAA AAA
AAA
AAA
AAA AAA
are +3 V or +5 V, and are user selectable. The SPT7734 has
incorporated proprietary circuit design and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS compatible to interface with
TTL/CMOS logic systems. Output data format is straight
binary.
The SPT7734 is available in 28-lead SOIC and 32-lead small
(7 mm square) TQFP packages over the commercial temperature range.
ADC Section 1
AIN
1:16
Mux
P1
AutoZero
CMP
T/H
9-Bit
SAR
9
D8 Overrange
9
D7 (MSB)
DAC
D6
P2
CLK In
Enable
..
Timing .
P15
and
Control
P16
.
.
.
.
.
.
.
.
.
ADC Section 15
AAA AAA
AAA
AAA
AAA AAA
ADC Section 16
T/H
Data
Vali
d
9
ADC Section 2
AutoZero
CMP
9
9-Bit
SAR
9
9-Bit
16:1
Mux/
Error
Correction
D5
D4
D3
D2
9
D1
DAC
DØ (LSB)
Ref
In
Reference Ladder
VREF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD ......................................................................... +6 V
DVDD ........................................................................ +6 V
Output
Digital Outputs ....................................................... 10 mA
Temperature
Operating Temperature ................................. 0 to +70 °C
Junction Temperature ......................................... +175 °C
Lead Temperature, (soldering 10 seconds) ........ +300 °C
Storage Temperature ................................ -65 to +150 °C
Input Voltages
Analog Input .................................. -0.5 V to AVDD +0.5 V
VREF ............................................................................ 0 to AVDD
CLK Input .................................................................. VDD
AVDD - DVDD ............................................................... ±100 mV
AGND - DGND ................................................... ±100 mV
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T A=TMAX to TMAX, AV DD =DV DD =+5.0 V, V IN =0 to 4 V, f S=40 MSPS, V RHS =4.0 V, V RLS =0.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
Resolution
MIN
SPT7734
TYP
MAX
8
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
IV
IV
VI
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
Gain Error
VI
IV
V
V
V
V
VRLS
50
(Small Signal)
Bits
±1.0
±0.5
Guaranteed
LSB
LSB
VRHS
V
kΩ
pF
MHz
LSB
LSB
Ω
MHz
5.0
250
UNITS
±2.0
±2.0
Reference Input
Resistance
Bandwidth
Voltage Range
VRLS
VRHS
VRHS - VRLS
∆(VRHF - VRHS)
∆(VRLS - VRLF)
VI
V
300
100
500
150
600
IV
IV
V
V
V
0
3.0
1.0
4.0
90
75
2.0
AVDD
5.0
Reference Settling Time
VRHS
VRLS
V
V
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
VI
IV
IV
V
V
40
2
Dynamic Performance
Effective Number of Bits
fIN=3.58 MHz
fIN=10.3 MHz
VI
VI
7.3
7.2
15
20
V
V
V
mV
mV
Clock Cycles
Clock Cycles
MHz
MHz
12
Clock Cycles
4.0
30
ns
ps(p-p)
7.8
7.7
Bits
Bits
SPT7734
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ELECTRICAL SPECIFICATIONS
T A=TMAX to TMAX, AV DD =DV DD =+5.0 V, V IN =0 to 4 V, f S=40 MSPS, V RHS =4.0 V, V RLS =0.0 V, unless otherwise specified.
PARAMETERS
Dynamic Performance
Signal-to-Noise Ratio
(without Harmonics)
fIN=3.58 MHz
fIN=10.3 MHz
Harmonic Distortion
fIN=3.58 MHz
fIN=10.3 MHz
Signal-to-Noise and Distortion
(SINAD)
fIN=3.58 MHz
fIN=10.3 MHz
Spurious Free Dynamic Range
Differential Phase
Differential Gain
Intermodulation Distortion
TEST
CONDITIONS
TEST
LEVEL
9 Distortion bins from
1024 pt FFT
fIN=1.0 MHz
IOH = 0.5 mA
IOL = 1.6 mA
15 pF load
15 pF load
20 pF load, TA = +25 °C
50 pF load over temp.
Power Supply Requirements
Voltages
OVDD
DVDD
AVDD
Currents
AIDD
DIDD
Power Dissipation
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
MAX
UNITS
VI
VI
46
45
49
48
dB
dB
VI
VI
53
53
57
56
dB
dB
VI
VI
46
45
49
48
dB
dB
VI
VI
VI
VI
V
TEST LEVEL CODES
SPT7734
TYP
V
V
V
Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
tRISE
tFALL
Output Enable to Data Output Delay
MIN
63
±0.3
±0.3
TBD
dB
Degree
%
dB
2.0
0.8
+10
+10
-10
-10
+5
VI
VI
V
V
V
V
3.5
IV
IV
IV
VI
VI
VI
3.0
4.75
4.75
0.4
10
10
10
22
5.0
5.0
17
18
175
5.0
5.25
5.25
22
23
225
V
V
µA
µA
pF
V
V
ns
ns
ns
ns
V
V
V
mA
mA
mW
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
SPT7734
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Figure 1A: Timing Diagram 1
AAA
A
A
A
A
A
A
A
A
A
A
A
A
AAA
A
A
A
A
A
A
A
A
A
A
A
A
AAA
A
A
A
A
AA
AA
A
1
ANALOG IN
CLOCK IN
SAMPLING
CLOCK
(Internal)
DATA OUTPUT
DATA VALID
A
A
A
A
A
A
A
AA
A
A
A
A
A
A
A
A
AA
A
A
A
AA
A
AAA
AAAAAA
AAAAAA
AAA
AAAAAA
AAAAAA
AAA
AAAAAA
AAA
11
A
A
A
A
A
A
A
AA
A
A
A
A
A
A
A
A
AA
A
A
A
AA
A
A
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AA
9
3
AAAAAA
AAA
AAAAAA
AAAAAA
AAA
AAAAAA
AAA
7
5
INVALID
AA
AAAAAAAAA
A
AA
A
A
AAAAAAA
A
AA
A
A
AAAAAAA
A
AA
A
A
AAAAAA
AAAAAAA
A
AA
A
A
AAAAAA
AAAAA
13
17
15
VALID
1
2
3
4
5
Figure 1B: Timing Diagram 2
tCLK
tC
tCH
tCL
CLOCK IN
DATA
OUTPUT
Data Ø
Data 1
Data 2
Data 3
tOD
tS
DATA
VALID
tCH
tCL
tS
Table I - Timing Parameters
DESCRIPTION
PARAMETERS
MIN
tC
tCLK
ns
tCLK
25
ns
Clock High Duty Cycle
tCH
40
50
60
%
Clock Low Duty Cycle
tCL
40
50
60
%
Clock to Output Delay (15 pF Load)
tOD
17
ns
Clock to DAV
tS
10
ns
Conversion Time
Clock Period
TYP
MAX
UNITS
SPT7734
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The high sample rate is achieved by using multiple SAR ADC
sections in parallel, each of which samples the input signal in
sequence. Each ADC uses 16 clock cycles to complete a
conversion. The clock cycles are allocated as follows:
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 1 shows the typical interface requirements when using the SPT7734 in normal circuit
operation. The following sections provide descriptions of the
major functions and outline critical performance criteria to
consider for achieving the optimal device performance.
Table II - Clock Cycles
Clock
1
2
3
4
5-15
16
Figure 1 - Typical Interface Circuit
Ref In
(+4 V)
VRHF
D8
VRHS
VRLS
VRLF
VIN
VIN
SPT7734
D0
VCAL
CLK
CLK IN
The 16 phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADC sections are shifted by one clock cycle so that the analog
input is sampled on every cycle of the input clock by exactly
one ADC section. After 16 clock periods, the timing cycle
repeats. The latency from analog input sample to the corresponding digital output is 12 clock cycles.
Interfacing
Logics
EN
DAV
AVDD
AGND
DGND* DVDD
• Since only 16 comparators are used, a huge power savings
is realized.
FB1
+D5
FB2
• The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparators
response to a reference zero.
Enable/Tri-State
(Enable = Active Low)
+A5
FB3
AGND
+A5
DGND
+
10 µF
+5 V
Analog
+5 V
Analog
RTN
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
Operation
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
9-bit SAR conversion
Data transfer
• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of the
gain error are integrated to produce a calibration voltage for
each ADC section.
+D5
+
10 µF
+5 V
Digital
RTN
+5 V
Digital
• Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator
samples the input during a clock cycle.
NOTES: 1) FB3 is to be located as closely to the device as possible.
2) There should be no additional connections to the right of FB1 and FB2.
3) All capacitors are 0.1 µF surface-mount unless otherwise specified.
4) FB1, FB2 and FB3 are 10 µH inductors or ferrite beads.
• The total input capacitance is very low since sections of the
converter which are not sampling the signal are isolated
from the input by transmission gates.
POWER SUPPLIES AND GROUNDING
CADEKA suggests that both the digital and the analog supply
voltages on the SPT7734 be derived from a single analog
supply as shown in figure 1. A separate digital supply should
be used for all interface circuitry. CADEKA suggests using
this power supply configuration to prevent a possible latchup condition on power up.
VOLTAGE REFERENCE
The SPT7734 requires the use of a single external voltage
reference for driving the high side of the reference ladder. It
must be within the range of 3 V to 5 V. The lower side of the
ladder is typically tied to AGND (0.0 V), but can be run up to
2.0 V with a second reference. The analog input voltage
range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in the
block diagram. The design contains 16 identical successive
approximation ADC sections, all operating in parallel, a 16phase clock generator, an 9-bit 16:1 digital output multiplexer, correction logic, and a voltage reference generator
which provides common reference levels for each ADC section.
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations. By
using the configuration shown in figure 2, offset and gain
errors of less than ±2 LSB can be obtained.
SPT7734
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Figure 2 - Ladder Force/Sense Circuit
1
+
-
2
3
4
5
+
Figure 3 - Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
AGND
+4.0 V
External
Reference
VRHF
90 mV
VRHS
(+3.91 V)
R/2
R
VRHS
R
N/C
R
R=30 Ω (typ)
All capacitors are 0.01 µF
R
VRLS
R
6
7
VRLF
R
VRLS
(0.075 V)
VIN
75 mV
R/2
VRLF (AGND)
0.0 V
All capacitors are 0.01 µF
In cases where wider variations in offset and gain can be
tolerated, VRef can be tied directly to VRHF and AGND can be
tied directly to VRLF as shown in figure 3. Decouple force and
sense lines to AGND with a .01 µF capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
The drive requirements for the analog inputs are very minimal
when compared to most other converters due to the SPT7734's
extremely low input capacitance of only 5 pF and very high
input resistance in excess of 50 kΩ.
The reference ladder circuit shown in figure 3 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
ladder, the voltage drop from VRHF to VRHS is not equivalent
to the voltage drop from VRLF to VRLS.
CALIBRATION
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 4.
The SPT7734 uses an auto calibration scheme to ensure 8-bit accuracy over time and temperature. Gain and
offset errors are continually adjusted to 8-bit accuracy during
device operation. This process is completely transparent to
the user.
Typically, the top side voltage drop for VRHF to VRHS will
equal:
Upon power-up, the SPT7734 begins its calibration algorithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 8bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10,000 clock cycles are required.
This results in a minimum calibration time upon power-up
of 250 µsec (for a 40 MHz clock). Once calibrated, the
SPT7734 remains calibrated over time and temperature.
VRHF - VRHS = 2.25 % of (VRHF - VRLF) (typical),
and the bottom side voltage drop for VRLS to VRLF will equal:
VRLS - VRLF = 1.9 % of (VRHF - VRLF) (typical).
Figure 3 shows an example of expected voltage drops for a
specific case. Vref of 4.0 V is applied to VRHF and VRLF is tied
to AGND. A 90 mV drop is seen at VRHS (= 3.91 V) and a
75 mV increase is seen at VRLS (= 0.075 V).
Since the calibration cycles are initiated on the rising edge of
the clock, the clock must be continuously applied for the
SPT7734 to remain in calibration.
ANALOG INPUT
VIN is the analog input. The input voltage range is from VRLS
to VRHS (typically 4.0 V) and will scale proportionally with
respect to the voltage reference. (See voltage reference
section.)
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 5. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times.
SPT7734
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CLOCK INPUT
Figure 4 - Recommended Input Protection Circuit
+V
The SPT7734 is driven from a single-ended TTL-input clock.
Because the pipelined architecture operates on the rising edge of
the clock input, the device can operate over a wide range of input
clock duty cycles without degrading the dynamic performance.
AVDD
DIGITAL OUTPUTS
D1
Buffer
The digital outputs (D0-D8) are driven by a separate supply
(OVDD) ranging from +3 V to +5 V. This feature makes it
possible to drive the SPT7734's TTL/CMOS-compatible outputs with the user's logic system supply. The format of the
output data (D0-D7) is straight binary. (See table III.) The
outputs are latched on the rising edge of CLK. These outputs
can be switched into a tri-state mode by bringing EN high.
ADC
47 Ω
D2
-V
Table III - Output Data Information
D1 = D2 = Hewlett Packard HP5712 or equivalent
Figure 5 - On-Chip Protection Circuit
VDD
120 Ω
ANALOG INPUT
OVERRANGE
D8
OUTPUT CODE
D7-D0
+F.S. + 1/2 LSB
1
1111
1111
+F.S. -1/2 LSB
O
1111
111Ø
+1/2 F.S.
O
ØØØØ ØØØØ
+1/2 LSB
O
OOOO OOOØ
0.0 V
O
OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
Analog
DO NOT CONNECT PINS (DNC)
There are two pins designated as Do Not Connect (DNC).
These pins must be left floating for proper operation of the
device.
120 Ω
Pad
OVERRANGE OUTPUT
The OVERRANGE OUTPUT (D8) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D8 will switch
to logic 1. All other data outputs (D0 to D7) will remain at
logic 1 as long as D8 remains at logic 1. This feature makes
it possible to include the SPT7734 into higher resolution
systems.
SPT7734
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PACKAGE OUTLINES
32-Lead TQFP
INCHES
A
SYMBOL
G H
B
C
D
I
E
MIN
MILLIMETERS
MAX
MIN
MAX
A
0.347
0.355
8.90
9.10
B
0.269
0.277
6.90
7.10
C
0.347
0.355
8.90
9.10
D
0.269
0.277
6.90
7.10
E
0.027
0.035
0.68
0.89
F
0.012
0.018
0.30
0.45
G
0.053
0.057
1.35
1.45
H
0.002
0.006
0.05
0.15
I
0.039 typ
1.00 typ
J
0.004
0.008
0.09
K
0°
7°
0°
0.20
7°
L
0.018
0.029
0.45
0.75
J
F
K
L
28-Lead SOIC
SYMBOL
A
B
C
D
E
F
G
H
I
28
I H
1
A
MIN
INCHES
MAX
0.696
0.004
0.712
0.012
.050 typ
0.019
0.012
0.100
0.050
0.419
0.299
0.014
0.009
0.080
0.016
0.394
0.291
MILLIMETERS
MIN
MAX
17.68
0.10
0.00
0.36
0.23
2.03
0.41
10.01
7.39
18.08
0.30
1.27
0.48
0.30
2.54
1.27
10.64
7.59
H
F
B
C
D
G
E
SPT7734
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1/27/98
PIN ASSIGNMENTS
PIN FUNCTIONS
Name
Function
AGND
Analog Ground
VRHF
Reference High Force
VRHS
Reference High Sense
VRLS
Reference Low Sense
VRLF
Reference Low Force
VCAL
Calibration Reference
VIN
Analog Input
AVDD
Analog VDD
DVDD
Digital VDD
DGND
Digital Ground
CLK
Input Clock fCLK =fs (TTL)
D6
EN
Output Enable
25
D0-7
Tri-State Data Output, (DØ=LSB)
D8
Tri-State Output Overrange
DAV
Data Valid Output
AGND 1
28
D8
2
27
D7
VRHS 3
26
D6
4
25
D5
VRLS 5
24
D4
VRLF
6
23
D3
VIN
7
22
OVDD
AGND 8
21
OGND
VCAL
9
20
D2
AVDD 10
19
D1
1
1
18
D0
DGND 12
17
DNC
CLK 13
16
DNC
DAV 14
15
EN
VRHF
N/C
DVDD
SOIC
D7
D8
AGND
AGND
VRHF
VRHS
VRLS
26
27
28
29
31
30
32
VRLF
1
24
D5
VIN
2
23
D4
AGND
3
22
D3
AGND
4
21
OVDD
OVDD
Digital Output Supply
OGND
Digital Output Ground
DNC
Do Not Connect
VCAL
AVD
D
AVD
D
DVDD
TQFP
20
OGND
6
19
D2
7
18
D1
8
17
D0
5
15
DAV
EN
DNC
DNC
14
CLK
16
13
DGND
DGND
12
10
DVDD
1
1
9
ORDERING INFORMATION
PART NUMBER
SPT7734SCS
SPT7734SCT
TEMPERATURE RANGE
0 to +70 °C
0 to +70 °C
PACKAGE TYPE
28L SOIC
32L TQFP
SPT7734
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