SPT7937 12-BIT, 28 MSPS, 170 mW A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • All High-Speed Applications Where Low Power Dissipation Is Required • Video Imaging • Medical Imaging • IR Imaging • Digital Communications Monolithic 28 MSPS Analog-to-Digital Converter 170 mW Power Dissipation On-Chip Track-and-Hold Single +5 V Power Supply TTL/CMOS Outputs 5 pF Input Capacitance Selectable +3 V or +5 V Logic I/O GENERAL DESCRIPTION The SPT7937 is a 12-bit monolithic, low-cost, low-power analog-to-digital converter capable of minimum sample rates of 28 MSPS. The SPT7937 has incorporated proprietary parallel SAR circuit design and CMOS processing technologies to achieve its advanced performance.The onchip track-and-hold function assures very good dynamic performance without the need for external components. Power dissipation is extremely low at only 170 mW typical at 28 MSPS with a power supply of +5.0 V. The digital outputs are +3 V or +5 V, and are user selectable. Inputs and outputs are TTL/CMOS compatible to interface with TTL/ CMOS logic systems. Output data format is straight binary. The SPT7937 is available in a 28-lead SSOP package over the industrial temperature range. BLOCK DIAGRAM ADC Section 1 AIN 1:18 Mux AutoZero CMP T/H 13-Bit SAR D12 Out of Range 13 D11 (MSB) 13 D10 DAC P1 D9 P2 CLK In .. . Timing P17 and Control P18 ADC Section 2 . . . . . . . . . ADC Section 17 ADC Section 18 AutoZero CMP T/H 13-Bit SAR D8 13 13 13-Bit 18:1 Mux/ Error Correction 13 13 DAC D7 D6 D5 D4 D3 D2 D1 DØ (LSB) Reference Ladder VRHF VRHS VRLS VRLF Signal Processing Technologies, Inc. 4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: [email protected] ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages AVDD ......................................................................... +6 V DVDD ......................................................................... +6 V OVDD ......................................................................... +6 V Output Digital Outputs ....................................................... 10 mA Temperature Operating Temperature ............................. –40 to +85 °C Junction Temperature ......................................... +175 °C Lead Temperature, (soldering 10 seconds) ........ +300 °C Storage Temperature ............................... –65 to +150 °C Input Voltages Analog Input .................................... –0.7 V to VDD +0.7 V CLK Input ................................................................... VDD AVDD – DVDD ...................................................... ±100 mV AGND – DGND .................................................. ±100 mV Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS T A=TMIN to TMAX, V DD =+5.0 V, ƒS=28 MSPS, V IN =0 to 4 V, V RHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL Resolution MIN SPT7937 TYP MAX 12 DC Accuracy Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Capacitance Input Bandwidth Input Impedance –Full-Scale Error1 +Full-Scale Error1 VI V V VI V IV V V V Dynamic Performance Effective Number of Bits ƒIN = 3.58 MHz ƒIN = 10 MHz 5.0 250 35 1.0 0.12 28 1 40 14 Clock Cycles 60 36 ns ps (RMS) % ns 10.3 10.0 VI 350 IV IV V 3.0 0.0 1.0 V pF MHz kΩ LSB %FS MHz MHz 1.0 5.0 V VI Reference Input Resistance Voltage Range3 VRHS VRLS VRHS – VRLS LSB LSB VRHS VRLS V V Conversion Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Aperture Delay Time (TAP) Aperture Jitter Time Clock Duty Cycle Over-Voltage Recovery Time2 Bits ±1.75 ±0.9 Guaranteed V V VI UNITS Bits Bits 500 650 Ω 4.0 VDD 2.0 5.0 V V V 1 The full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion. to internal architecture, over-voltage recovery time is less than one clock cycle (i.e., 25 ns at ƒCLK = 40 MHz). 3 For optimum performance, the full-scale voltage range (VRHS–VRLS) should be between 3 V to 5 V. 2 Due SPT SPT7937 2 1/14/00 ELECTRICAL SPECIFICATIONS T A =TMIN to TMAX, V DD =+5.0 V, ƒS=28 MSPS, V IN =0 to 4 V, V RHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL Dynamic Performance Signal-to-Noise Ratio (without Harmonics) ƒIN = 3.58 MHz ƒIN = 10 MHz Harmonic Distortion ƒIN = 3.58 MHz ƒIN = 10 MHz Signal-to-Noise and Distortion (SINAD) ƒ IN = 3.58 MHz ƒ IN = 10 MHz Spurious Free Dynamic Range ƒIN = 10 MHz Differential Phase Differential Gain V VI V VI 61 60 VI VI VI VI V IOH = 0.5 mA IOL = 1.6 mA TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II MAX 65 63 –73 –72 V V V Power Supply Requirements Voltages OVDD VDD Currents IDD Power Dissipation Power Supply Rejection Ratio dB dB –63.5 dB dB 73 0.6 0.5 dB Degree % –10 –10 0.8 +10 +10 V V µA µA pF 0.4 V V ns 5 VDD – 0.5 IV IV VI VI V 3.0 4.75 dB dB 64 62 2.0 VI VI IV UNITS 15 5.0 34 170 60 5.0 5.25 40 200 V V mA mW dB TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. III IV V VI SPT SPT7937 TYP V VI Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage CLK to Output Delay Time (tD) MIN SPT7937 3 1/14/00 Figure 1a – Timing Diagram 1 10 2 8 4 5 6 12 13 9 3 ANALOG IN 11 17 14 7 15 16 CLOCK IN INVALID VALID DATA OUTPUT 1 2 3 Figure 1b – Timing Diagram tCLK tC tCH tCL CLOCK IN DATA OUTPUT Data Ø Data 1 Data 2 Data 3 tD SPT SPT7937 4 1/14/00 TYPICAL PERFORMANCE CHARACTERISTICS THD, SNR, SINAD vs Input Frequency THD, SNR, SINAD vs Sample Rate 75 90 80 THD, SNR, SINAD (dB) THD, SNR, SINAD (dB) 70 THD 65 SNR 60 SINAD 55 50 SNR 60 SINAD 50 40 45 30 0 5 10 15 20 0 1 5 10 20 30 40 Input Frequency (MHz) Sample Rate (MSPS) THD, SNR, SINAD vs Temperature SFDR vs Temperature 50 85 85 80 80 75 75 SFDR (dB) THD, SNR, SINAD (dB) THD 70 THD 70 70 65 65 SNR 60 60 SINAD 55 55 –55 –40 0 25 70 85 –55 125 –40 0 Temperature (°C) 30 –5 25 –10 20 IDD (mA) Output Fundamental (dBm) 0 –15 85 125 15 –20 10 –25 5 0 200 300 400 500 10–1 1000 100 101 102 Sample Rate (MSPS) Frequency (MHz) SPT 70 IDD vs Sample Rate Input Bandwidth –30 100 25 Temperature (°C) SPT7937 5 1/14/00 Figure 2 – Typical Interface Circuit CLK IN + DGND D11 CLK D10 DVDD D9 AVDD D8 U1 DGND (DUT) VINR AIN VIN +A5 U1 TK11240B + Ext VREF (+4 V) D7 D6 D5 RGND D4 VRHS D3 VRHF D2 VRLF D1 VRLS D0 DVDD2 MSB OVDD LSB 1 + 28 Out of Range Bit Interfacing Logic +A5 OTR SPT7937 + OGND FB +D3/5V +A5 +D3/5V +D3/5 + + 10 µF 10 µF +A5 AGND +D3/5 DGND Notes: 1) Unless otherwise specified, all non-polarized capacitors are 0.01 microfarad surface-mount chip capacitors. They need to be placed as close to the pin as possible 2) All polarized capacitors are 4.7 to 10 microfarad tantalum surface-mount capacitors 3) FB is a ferrite bead. Place FB as close to the DUT as possible 4) U1 is TOKO regulator TK11240B (4.0 V) TYPICAL INTERFACE CIRCUIT POWER SUPPLIES AND GROUNDING Very few external components are required to achieve the stated device performance. Figure 2 shows the typical interface requirements when using the SPT7937 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. SPT suggests that both the digital (DVDD) and the analog (AVDD) supply voltages on the SPT7937 be derived from a single analog supply as shown in figure 2. A separate digital supply should be used for the digital output driver supply (OVDD) and all interface circuitry. SPT suggests using this power supply configuration to prevent a possible latch-up condition on power up. In addition, the power supplies must be powered up before the analog input is applied. SPT SPT7937 6 1/14/00 OPERATING DESCRIPTION VOLTAGE REFERENCE The general architecture for the CMOS ADC is shown in the block diagram. The design contains 18 identical successive approximation ADC sections (all operating in parallel), an 18-phase clock generator, a 13-bit 18:1 digital output multiplexer, correction logic, and a voltage reference generator which provides common reference levels for each ADC section. The SPT7937 requires the use of a single external voltage reference for driving the high side of the reference ladder. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage fullscale range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS. For optimum performance the full-scale voltage range (VRHS–VRLS) should be between 3 V to 5 V. The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each ADC uses 18 clock cycles to complete a conversion. The clock cycles are allocated as follows: Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than ±2 LSB can be obtained. Table II – Clock Cycles Clock Operation 1 Reference zero sampling 2 Auto-zero comparison 3 Auto-calibrate comparison 4 Input sample 5-17 13-bit SAR conversion 18 Data transfer Figure 3 – Ladder Force/Sense Circuit + – The 18-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one ADC section. After 18 clock periods, the timing cycle repeats. The latency from analog input sample to the corresponding digital output is 14 clock cycles. • Since only 18 comparators are used, a huge power savings is realized. • The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator’s response to a reference zero. • The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section. • Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. • The total input capacitance is very low since sections of the converter which are not sampling the signal are isolated from the input by transmission gates. SPT 1 AGND 2 VRHF 3 VRHS 4 N/C 5 – + VRLS 6 VRLF 7 VIN All capacitors are 0.01 µF SPT7937 7 1/14/00 Figure 4 – Simplified Reference Ladder Drive Circuit Without Force/Sense Circuit +4.0 V External Reference 21 mV VRHS (+3.91 V) ANALOG INPUT VIN is the analog input. The input voltage range is from VRLS to VRHS (typically 4.0 V) and will scale proportionally with respect to the voltage reference. (See the Voltage Reference section.) R/2 The drive requirements for the analog inputs are very minimal when compared to most other converters due to the SPT7937’s extremely low input capacitance of only 5 pF and very high input resistance in excess of 35 kΩ. R R R The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. To prevent possible latch-up condition, the power supplies must be powered up before the input is applied. R=30 Ω (typ) All capacitors are 0.01 µF R R Figure 5 – Recommended Input Protection Circuit +V AVDD R VRLS (0.075 V) 50 mV R/2 D1 VRLF (AGND) 0.0 V Buffer ADC 47 Ω D2 In cases in which wider variations in offset and gain can be tolerated, VRef can be tied directly to VRHF and AGND can be tied directly to VRLF as shown in figure 4. Decouple force and sense lines to AGND with a 0.01 µF capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account: –V D1 = D2 = Hewlett Packard HP5712 or equivalent CALIBRATION The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS. The SPT7937 uses a user-transparent, auto-calibration scheme to ensure 12-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 12-bit accuracy during device operation. Upon power up, the SPT7937 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 12bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon power-up of 357 µsec (for a 28 MHz clock). Once calibrated, the SPT7937 remains calibrated over time and temperature. Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF – VRHS = 0.5% of (VRHF – VRLF) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS – VRLF = 1.25% of (VRHF – VRLF) (typical). Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF and VRLF is tied to AGND. A 21 mV drop is seen at VRHS (= 3.79 V) and a 50 mV increase is seen at VRLS (= 0.050 V). SPT Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7937 to remain in calibration. SPT7937 8 1/14/00 Figure 6 – On-Chip Protection Circuit DIGITAL OUTPUTS VDD 120 Ω The digital outputs (D0–D12) are driven by a separate supply (OVDD) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7937’s TTL/CMOS-compatible outputs with the user’s logic system supply. The format of the output data (D0–D11) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. Analog 120 Ω Table III – Output Data Information Pad ANALOG INPUT +F.S. + 1/2 LSB +F.S. –1/2 LSB +1/2 F.S. +1/2 LSB 0.0 V OVERRANGE D12 1 0 0 0 0 OUTPUT CODE D11–D0 11 1111 1111 11 1111 111Ø ØØ ØØØØ ØØØØ 00 0000 000Ø 00 0000 0000 (Ø indicates the flickering bit between logic 0 and 1). OVERRANGE OUTPUT INPUT PROTECTION The Overrange Output (D12) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 LSB. When this condition occurs, D12 will switch to logic 1. All other data outputs (D0 to D11) will remain at logic 1 as long as D12 remains at logic 1. This feature makes it possible to include the SPT7937 in higher resolution systems. All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times. CLOCK INPUT The SPT7937 is driven from a single-ended TTL-input clock. Because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. SPT EVALUATION BOARD The EB7937 evaluation board is available to aid designers in demonstrating the full performance of the SPT7937. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note (AN7937) describing the operation of this board, as well as information on the testing of the SPT7937, is also available. Contact the factory for price and availability. SPT7937 9 1/14/00 PACKAGE OUTLINE 28-Lead SSOP INCHES 28 SYMBOL MIN MAX MIN MAX A 0.397 0.407 10.07 10.33 B 0.002 0.008 0.05 C I H 1 A MILLIMETERS 0.0256 typ 0.21 0.65 typ D 0.010 0.015 0.25 0.38 E 0.004 0.008 0.09 0.20 F 0.066 0.070 1.68 1.78 G 0.025 0.037 0.63 0.95 H 0.301 0.311 7.65 7.90 I 0.205 0.212 5.20 5.38 H F B C D G E SPT SPT7937 10 1/14/00 PIN ASSIGNMENTS PIN FUNCTIONS Name Function OVDD Digital Output Driver Supply OVDD 1 28 DVDD2 D0 (LSB) 2 27 VRLS D0-D11 Data Output, Bits 0 – Bit 11 D1 3 26 VRLF D12 Out of Range D2 4 25 VRHF OGND Digital Output Driver Ground D3 5 24 VRHS DGND Digital Ground D4 6 23 RGND CLK Input Clock D5 7 22 VIN DVDD1 Digital VDD D6 8 21 VINR DVDD2 Digital VDD; must be tied to DVDD1 D7 9 20 AGND AVDD Analog VDD AVDD Analog Ground 10 19 AGND D8 Analog Input Return 11 18 DVDD1 VINR D9 VIN Analog Input, Full Scale from VRLS to VRHS D10 12 17 CLK RGND Analog Ground Shield (Junction Isolated) D11 (MSB) 13 16 DGND VRHS Reference High Sense D12 14 15 OGND VRHF Reference High Force (VRHF≤AVDD) VRLS Reference Low Sense VRLF Reference Low Force 28L SSOP ORDERING INFORMATION PART NUMBER SPT7937SIR TEMPERATURE RANGE –40 to +85 °C PACKAGE TYPE 28L SSOP Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING – LIFE SUPPORT APPLICATIONS POLICY – SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty. SPT SPT7937 11 1/14/00