SPT7853 TRIPLE 10-BIT, 30 MSPS A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • Three 10-bit, 30 MSPS ADCs on one chip SINAD of 54.5 dB @ ƒIN = 3.58 MHz Channel-to-channel cross talk: –66 dB typical Channel-to-channel gain matching of <0.1 dB Single 2X sample rate clock Total power dissipation: 580 mW (typical) Tri-state +3 V to +5 V digital outputs CMOS-compatible Single +5 V power supply CCIR-601 (4:2:2/4:4:4) digital component video RGB video decoding Medical imaging Flat panel displays PC projectors GENERAL DESCRIPTION The SPT7853 has three 10-bit analog-to-digital converters on one CMOS chip, each with a sample rate of 30 MSPS. This device is ideal for professional-level video decoding to 4:2:2/4:4:4 CCIR-601 standard specifications for component digital video, including YCrCb and RGB decoding, professional video equipment, video frame grabbers, medical imaging, flat panel display and projection applications. The SPT7853 offers significant advantages over discrete single-channel A/D implementations. Board area, package count, system cost and power dissipation can greatly be reduced by using a single SPT7853 device. In addition, several performance advantages exist, including low channel-to-channel cross-talk noise and well matched channelto-channel gain specifications. The three analog-to-digital converters are driven from a common 2X sample rate CMOS clock. The SPT7853 typically consumes only 580 mW of total power from a single +5 V supply. Digital outputs can operate with +3 V or +5 V logic and are tri-state capable. The SPT7853 is offered in a small 52-pin thin quad flat pack (TQFP) package and operates over the 0 to +70 °C commercial temperature range. BLOCK DIAGRAM VRH Force/Sense 2 VRL Force/Sense 2 Reference Ladder VINA T/H ADCA 10 Output Buffer DA0–9 VINB T/H ADCB 10 Output Buffer DB0–9 VINC T/H ADCC 10 Output Buffer DC0–9 Clock Timing Generation DAV Output Enable ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages VDD .................................................................................................... +6 V OVDD ................................................................................................. +6 V Output Currents Digital Outputs ....................................................... 10 mA Temperature Operating Temperature ................................ 0 to + 70 °C Junction Temperature ......................................... +150 °C Lead, Soldering (10 seconds) ............................. +300 °C Storage .................................................... –65 to +150 °C Temperature Analog Inputs .................................. –0.5 V to VDD +0.5 V VREF ................................................ –0.5 V to VDD +0.5 V Clock Input ...................................... –0.5 V to VDD +0.5 V Note: 1. Operation at any Absolute Maximum Rating is not implied and operation beyond the ratings may cause damage to the device. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=30 MSPS, ƒCLK=60 MHz, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS DC Performance Resolution Differential Linearity Integral Linearity TEST CONDITIONS TEST LEVEL ƒs = 20 MSPS ƒs = 20 MSPS MIN IV IV V V V V VI VRLS Timing Characteristics Conversion Rate Clock Duty Cycle Range Clock-to-Sample Rate Relationship Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter Time VI IV IV IV V V 30 45 @ 25 °C @ 0 to 70 °C @ 25 °C VI V V @ 25 °C @ 0 to 70 °C @ 25 °C ƒIN = 10.0 MHz Signal-to-Noise Ratio ƒIN = 3.58 MHz ƒIN = 10.0 MHz Total Harmonic Distortion ƒIN = 3.58 MHz ƒIN = 10.0 MHz Signal-to-Noise + Distortion Ratio ƒIN = 3.58 MHz ƒIN = 10.0 MHz 2The MAX UNITS 10 ±0.5 ±1.0 V V Analog Input Input Voltage Range2 Input Resistance Input Capacitance Input Bandwidth (Full Power) –Full-Scale Error2 +Full-Scale Error2 Reference Ladder Resistance Dynamic Performance Effective Number of Bits ƒIN = 3.58 MHz SPT7853 TYP 120 Bits LSB LSB VRHS 50 5 120 ±0.5 ±0.25 170 220 55 V kΩ pF MHz %FS %FS Ω MSPS % 2:1 12 5 15 Clock Cycles ns ps 8.3 8.7 8.0 7.4 Bits Bits Bits VI V V 53 56 51.6 48 dB dB dB @ 25 °C @ 0 to 70 °C @ 25 °C VI V V –56 –58 –54.6 –51 dB dB dB @ 25 °C @ 0 to 70 °C @ 25 °C VI V V 52 54.5 49.7 46 dB dB dB full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion. SPT7853 2 12/14/99 ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, VDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=30 MSPS, ƒCLK=60 MHz, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Dynamic Performance Spurious Free Dynamic Range ƒIN = 3.58 MHz TEST CONDITIONS TEST LEVEL @ 25 °C @ 0 to 70 °C Channel-to-Channel Cross Talk ƒIN = 3.58 MHz Channel-to-Channel Gain Matching Differential Phase Differential Gain Power Supply Requirements VDD Supply Voltage OVDD Supply Voltage Supply Current IDD OIDD Power Dissipation Without reference ladder Including reference ladder Digital Inputs/Outputs Digital Input Logic 1 Voltage Digital Input Logic 0 Voltage Digital Output Logic 1 Voltage Digital Output Logic 0 Voltage tRISE/tFALL (CL = 10 pF) OEN to Data Output MIN SPT7853 TYP MAX UNITS V V 65 56.3 dBc dBc V V V V –66 ±0.1 0.5 0.5 dB dB Degree % IV IV +5.0 +5.25 +5.25 VI V 81 9 105 11 mA mA CL = 10 pF CL = 10 pF V VI 485 580 750 mW mW IOH = 500 µA IOL = 800 µA VI VI VI VI V V TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II +4.75 +2.7 4.0 1.0 OVDD –0.5 0.4 10 12 V V V V V V ns ns TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. III IV V VI SPT7853 3 12/14/99 Figure 1a – Timing Diagram 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ANALOG IN CLOCK IN SAMPLING CLOCK (Internal) INVALID VALID 1 DIGITAL OUT 2 3 4 5 6 7 8 9 10 11 DATA VALID Figure 1b – Timing Diagram 2 tC tCH tCL tCLK CLOCK IN tOD DATA OUTPUT DA, DB, DC Data 1 Data 0 tDAV DATA VALID Data 2 tDAV tS Table I – Timing Parameters Description Conversion time Clock period Parameters Min tC 2 x tCLK nS tCLK 16.67 nS Clock duty cycle 45 Clock to output delay (15 pF load) tOD DAV pulse width Clock to DAV Typ 50 Max Units 55 % 19 nS tDAV tCLK nS tD 6.5 nS SPT7853 4 12/14/99 TYPICAL PERFORMANCE CHARACTERISTICS THD, SNR, SINAD vs Sample Rate THD, SNR, SINAD vs Input Frequency 80 65 ƒIN=3.58 MHz THD 70 THD, SNR, SINAD (dB) THD, SNR, SINAD (dB) 60 55 SNR SINAD 50 45 SNR SINAD 50 40 30 40 20 35 0 2 6 4 8 0 10 10 20 30 40 Input Frequency (MHz) Sample Rate (MSPS) THD, SNR, SFDR, SINAD vs Temperature Power Dissipation vs Sample Rate1 600 70 SFDR THD, SNR, SFDR, SINAD (dB) THD 60 500 Power Dissipation (mW) 65 60 THD SNR 55 SINAD 50 400 300 200 100 45 0 0 40 0 20 40 60 5 10 15 20 25 30 35 40 Sample Rate (MSPS) 80 Temperature (°C) Note 1: Power dissipation does not include reference. Large Signal Bandwidth Spectral Response 1.0 0 CLK 30 MHz ƒIN=3.58 MHz 0.5 –20 –40 –0.5 dB Amplitude (dB) 0 –1.0 –60 –1.5 –80 –2.0 –100 –2.5 –3.0 –120 0 5 10 Frequency (MHz) 0 15 x106 25 50 75 100 125 Frequency (MHz) SPT7853 5 12/14/99 The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each SAR ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as follows: TYPICAL INTERFACE CIRCUIT Very few external components are required to achieve the stated device performance. Figure 2 shows the typical interface requirements when using the SPT7853 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. Table II – Clock Cycles Clock Figure 2 – Typical Interface Circuit DGND AGND Ferrite Bead Hi-Z +D2.7V–5V OEN 4.7 + VRHF Enable VRHS DA0–9 VRLF 10 VRLS VCAL VIN1 VINA VIN2 VINB VIN3 VINC DB0–9 SPT7853 VRLT DC0–9 10 DAV OVDD VDD DGND AGND 2 Auto-zero comparison 3 Auto-calibrate comparison 4 Input sample 5-15 11-bit SAR conversion 16 Data transfer The 16-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by two clock cycles so that the analog input is sampled on every other cycle of the input clock by exactly one ADC section. After 16 clock periods, the timing cycle repeats. The sample rate for the configuration is one-half of the clock rate, e.g., for a 60 MHz clock rate, the input sample rate is 30 MHz. The latency from analog input sample to the corresponding digital output is 12 clock cycles. +D2.7V-5V DGND CLK Clock Input • Since only eight comparators are used, a huge power savings is realized. + 4.7 AGND • The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator’s response to a reference zero. +A5 NOTES: 1. 2. 3. 4. Reference zero sampling 10 Interfacing Logic REF IN (+4V typ) Operation 1 Place the Ferrite bead as close to the ADC as possible. All capacitors are 0.01 microfarad surface mount unless otherwise specified. Place 0.01 microfarad surface mount as close to the respective decoupling pin as possible. All input pins (references, analog inputs, clock input and /OEN) must be protected to within the specified absolute maximum ratings. • The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section. POWER SUPPLIES AND GROUNDING The digital and the analog supply voltages on the SPT7853 are internally derived from a single analog supply. A separate digital supply must be used for all interface circuitry (OVDD). Connect the digital ground (DGND) to the analog ground plane, as shown in figure 2, to prevent possible latch-up condition. • Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. • The total input capacitance is very low since sections of the converter which are not sampling the signal are isolated from the input by transmission gates. OPERATING DESCRIPTION VOLTAGE REFERENCE The general architecture for the CMOS ADC is shown in the block diagram. Each ADC uses a parallel SAR architecture. Each contains eight identical successive approximation ADC sections, all operating in parallel, a 16-phase clock generator, an 11-bit 8:1 digital output multiplexer, correction logic, and a voltage reference generator which provides common reference levels for each ADC section. The SPT7853 requires the use of a single external voltage reference for driving the high side of the reference ladder of each ADC. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS. SPT7853 6 12/14/99 Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than ±2 LSB can be obtained. The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS. Figure 3 – Ladder Force/Sense Circuit Typically, the top side voltage drop for VRHF to VRHS will equal: + – VRHF – VRHS = 7% of (VRHF – VRLF) (typical), VRHF and the bottom side voltage drop for VRLS to VRLF will equal: VRLS – VRLF = 8.8% of (VRHF – VRLF) (typical). VRHS Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF, and VRLF is tied to AGND. A 280 mV drop is seen at VRHS (= 3.72 V) and a 350 mV increase is seen at VRLS (= 0.35 V). VRLS – + ANALOG INPUT VRLF The input voltage range is from VRLS to VRHS and will scale proportionally with respect to the voltage reference. (See voltage reference section.) All capacitors are 0.01 µF The drive requirements for the analog inputs are very minimal when compared to most other converters, due to the SPT7853’s extremely low input capacitance of only 5 pF and very high input resistance of 50 kΩ. Figure 4 – Simplified Reference Ladder Drive Circuit without Force/Sense Circuit +4.0 V External Reference 280 mV VRHS (+3.72 V) R/2 The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. R Figure 5 – Recommended Input Protection Circuit +V AVDD R R R=30 Ω (typ) All capacitors are 0.01 µF D1 R Buffer R ADC 47 Ω D2 R VRLS (0.35 V) 350 mV R/2 –V VRLF (AGND) (0.0 V) D1 = D2 = Hewlett Packard HP5712 or equivalent In cases where wider variations in offset and gain can be tolerated, VREF can be tied directly to VRHF and AGND can be tied directly to VRLF as shown in figure 4. Decouple force and sense lines to AGND with a 0.01 µF capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account: SPT7853 7 12/14/99 CALIBRATION CLOCK INPUT The SPT7853 uses an auto-calibration scheme to ensure 10-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 10-bit accuracy during device operation. This process is completely transparent to the user. The SPT7853 is driven from a single-ended input clock. Because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. The device’s sample rate is 1/2 of the input clock frequency. (See the timing diagram.) Upon powerup, the SPT7853 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10-bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10k clock cycles are required. This results in a minimum calibration time upon powerup of 150 µsec. Once calibrated, the SPT7853 remains calibrated over time and temperature. DIGITAL OUTPUTS The digital outputs for each channel (D0–D9) are driven by a separate supply (OVDD) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7853’s CMOScompatible outputs with the user’s logic system supply. The format of the output data (D0–D9) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. These outputs can be switched into a tri-state mode by bringing OEN high. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7853 to remain in calibration. Table III – Output Data Information INPUT PROTECTION ANALOG INPUT All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times. Figure 6 – On-Chip Protection Circuit VDD 120 Ω Analog OUTPUT CODE D9-D0 +F.S. + 1/2 LSB 11 1111 1111 +F.S. –1/2 LSB 11 1111 111Ø +1/2 F.S. ØØ ØØØØ ØØØØ +1/2 LSB 00 0000 000Ø 0.0 V 00 0000 0000 (Ø indicates the flickering bit between logic 0 and 1). DATA AVAILABLE The Data Available pin goes high when the data output bits are valid (see figure 1b). Note: Optimal performance of the data valid pin is achieved when using an input clock with a minimum span range of ≤1 V (clock low) to ≥4 V (clock high). 120 Ω Pad EVALUATION BOARD The EB7853 Evaluation Board is available to aid designers in demonstrating the full performance of the SPT7853. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note (AN7853) describing the operation of this board as well as information on the testing of the SPT7853 is also available. Contact the factory for price and availability. POWER SUPPLY SEQUENCING CONSIDERATIONS All logic inputs should be held low until power to the device has settled to the specific tolerances. Avoid power decoupling networks with large time constants which could delay VDD power to the device. SPT7853 8 12/14/99 PACKAGE OUTLINE 52-Lead TQFP INCHES A B 52 1 C SYMBOL 40 39 D 13 J 26 14 I E MIN MAX 0.472 typ 12.0 typ B 0.394 typ 10.0 typ C 0.472 typ 12.0 typ D 0.394 typ 10.0 typ E 0.0630 typ F 0.0256 typ 0.009 H H MAX A G 27 MIN MILLIMETERS 0.013 1.60 0.65 typ 0.22 0.0394 typ 0.33 1.0 typ I 0.004 0.006 0.09 0.16 J 0.018 0.029 0.45 0.75 K 0° 7° 0° 7° K F G SPT7853 9 12/14/99 41 DA0 40 DGND 44 DA3 43 DA2 42 DA1 46 DA5 45 DA4 48 DA7 PIN FUNCTIONS 47 DA6 50 DA9 49 DA8 52 VRHF 51 AGND PIN ASSIGNMENTS VRHS 1 39 CLK VRLF 2 38 DB9 VRLS 3 37 DB8 VRLT Name Function VINA Analog input for channel A VINB Analog input for channel B VINC Analog input for channel C DA0–DA9 CMOS-compatible digital output data for channel A (+2.7 V to +5.0 voltage logic) DB0–DB9 CMOS-compatible digital output data for channel B (+2.7 V to +5.0 voltage logic) Output enable pin. (Low = enabled; High = high impedance) VCAL AGND 10 30 DB1 CLK CMOS-compatible input clock (2x of sample rate). 11 29 DB0 VINC 28 DAV VRHF Input for top of reference ladder (force) 12 AGND 13 27 OVDD VRHS Input for top of reference ladder (sense) VRLF Input for bottom of reference ladder (force) VRLS Input for bottom of reference ladder (sense) VDD Analog +5 V; Digital +5 V OVDD Output supply +2.7 / +5 V AGND Analog ground DGND Digital ground VRLT Tie to VRLS VCAL Calibration reference DAV Data available VDD 26 OEN 31 DB2 DC8 24 32 DB3 9 DC9 25 8 VDD DC7 23 VINB DC6 22 DC0–DC9 CMOS-compatible digital output data for channel C (+2.7 V to +5.0 voltage logic) DC4 20 33 DB4 DC5 21 7 DC3 19 34 DB5 DC2 18 6 AGND DC1 17 VINA DC0 16 5 35 DB6 N/C 14 36 DB7 OEN 15 4 AGND ORDERING INFORMATION PART NUMBER SPT7853SCT TEMPERATURE RANGE 0 to +70 °C PACKAGE TYPE 52-Pin TQFP SPT7853 10 12/14/99