CADEKA SPT7850SCT

SPT7850
10-BIT, 20 MSPS, 140 mW A/D CONVERTER
TECHNICAL DATA
JUNE 15, 2001
FEATURES
APPLICATIONS
• Monolithic 20 MSPS converter
• 140 mW power dissipation
• On-chip track-and-hold
• Single +5 V power supply
• TTL/CMOS outputs
• 5 pF input capacitance
• Low cost
• Tri-state output buffers
• High ESD protection: 3,500 V minimum
• Selectable +3 V or +5 V logic I/O
• All high-speed applications where low power
dissipation is required
• Video imaging
• Medical imaging
• IR imaging
• Scanners
• Digital communications
GENERAL DESCRIPTION
family of 10-bit, CMOS converters (SPT7835/40/50/55/60/
61), which simplifies upgrades. The SPT7850 has incorporated proprietary circuit design* and CMOS processing
technologies to achieve its advanced performance. Inputs
and outputs are TTL/CMOS-compatible to interface with
TTL/CMOS logic systems. Output data format is straight
binary.
The SPT7850 is a 10-bit monolithic, low-cost, ultralowpower analog-to-digital converter capable of minimum
word rates of 20 MSPS. The on-chip track-and-hold function assures very good dynamic performance without the
need for external components. The input drive requirements are minimized due to the SPT7850’s low input
capacitance of only 5 pF.
Power dissipation is extremely low at only 140 mW typical
(165 mW maximum) at 20 MSPS with a power supply of
+5.0 V. The digital outputs are +3 V or +5 V, and are user
selectable. The SPT7850 is pin-compatible with an entire
The SPT7850 is available in 28-lead 300 mil PDIP and
32-lead small (7 mm square) TQFP packages over the
commercial temperature range, and in a 28-lead SOIC
package over the industrial temperature range.
*Patent pending
BLOCK DIAGRAM
ADC Section 1
AIN
1:8
Mux
T/H
AutoZero
CMP
11-Bit
SAR
D10 Overrange
11
D9 (MSB)
11
CLK In
..
.
P2
Timing
P7
and
Control
Enable
P8
..
.
ADC Section 7
..
. 11
..
.
ADC Section 2
ADC Section 8
T/H
Data
Valid
D8
DAC
P1
AutoZero
CMP
11
11-Bit
SAR
D7
11
11-Bit
8:1
Mux/
Error
Correction
D6
D5
D4
D3
11
D2
DAC
D1
Ref
In
Reference Ladder
VREF
D0 (LSB)
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD ...................................................................... +6 V
DVDD ..................................................................... +6 V
Output
Digital Outputs ................................................... 10 mA
Temperature
Operating Temperature ............................ –40 to 85 °C
Junction Temperature ........................................ 175 °C
Lead Temperature, (soldering 10 seconds) ....... 300 °C
Storage Temperature ............................ –65 to +150 °C
Input Voltages
Analog Input .............................. –0.5 V to AVDD +0.5 V
VREF .............................................................. 0 to AVDD
CLK Input ............................................................... VDD
AVDD – DVDD .................................................. ±100 mV
AGND – DGND .............................................. ±100 mV
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒCLK=40 MHz, ƒS=20 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
Resolution
MIN
MAX
10
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
No Missing Codes
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
Gain Error
UNITS
Bits
100 kHz clock rate1
V
V
VI
(Small Signal)
±1.0
±0.5
Guaranteed
VI
IV
V
V
V
V
VRLS
50
VI
V
400
100
IV
IV
V
V
V
0
3.0
1.0
Reference Settling Time
VRHS
VRLS
V
V
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
VI
V
IV
V
V
Dynamic Performance
Effective Number of Bits (ENOB)
ƒIN = 3.58 MHz
ƒIN = 10.3 MHz
Signal-to-Noise Ratio (SNR)
(without Harmonics)
ƒIN = 3.58 MHz
ƒIN = 10.3 MHz
VRHS
V
kΩ
pF
MHz
LSB
LSB
500
150
600
Ω
MHz
4.0
90
75
2.0
AVDD
5.0
15
20
5
30
MHz
kHz
Clock Cycles
ns
ps (p-p)
8.8
8.5
Bits
Bits
56
55
dB
dB
50
12
53
52
V
V
V
mV
mV
Clock Cycles
Clock Cycles
20
VI
VI
VI
VI
LSB
LSB
5.0
100
±2.0
±2.0
Reference Input
Resistance
Bandwidth
Voltage Range
VRLS
VRHS
VRHS – VRLS
∆(VRHF – VRHS)
∆(VRLS – VRLF)
1SPT7850SCN
SPT7850
TYP
is screened for DC accuracy tests at 100 kHz. SPT7850SIS and SPT7850SCT are screened for DC accuracy tests at 35 MHz.
SPT7850
2
6/15/01
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒCLK=40 MHz, ƒS=20 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
PARAMETERS
Dynamic Performance
Total Harmonic Distortion (THD)
ƒIN = 3.58 MHz
ƒIN = 10.3 MHz
Signal-to-Noise and Distortion
(SINAD)
ƒIN = 3.58 MHz
ƒIN = 10.3 MHz
Spurious Free Dynamic Range
TEST
CONDITIONS
TEST
LEVEL
ƒIN = 1 MHz
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
tRISE
tFALL
Output Enable to Data Output Delay
IOH = 0.5 mA
IOL = 1.6 mA
15 pF load
15 pF load
20 pF load, TA = +25 °C
50 pF load over temp.
Power Supply Requirements
Voltages
OVDD
DVDD
AVDD
Currents
AIDD
DIDD
Power Dissipation
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL
I
II
III
IV
V
VI
MIN
SPT7850
TYP
MAX
UNITS
VI
VI
56
53
59
56
dB
dB
VI
VI
V
52
50
55
53
63
dB
dB
dB
VI
VI
VI
VI
V
2.0
0.8
+10
+10
–10
–10
5
VI
VI
V
V
V
V
3.5
IV
IV
IV
VI
VI
VI
3.0
4.75
4.75
0.4
10
10
10
22
5.0
5.0
10
18
140
5.25
5.25
5.25
12
21
165
V
V
µA
µA
pF
V
V
ns
ns
ns
ns
V
V
V
mA
mA
mW
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT7850
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SPECIFICATION DEFINITIONS
APERTURE DELAY
OUTPUT DELAY
Aperture delay represents the point in time, relative to the
rising edge of the CLOCK input, that the analog input is
sampled.
Time between the clock’s triggering edge and output data
valid.
OVERVOLTAGE RECOVERY TIME
APERTURE JITTER
The time required for the ADC to recover to full accuracy
after an analog input signal 125% of full scale is reduced
to 50% of the full-scale value.
The variations in aperture delay for successive samples.
EFFECTIVE NUMBER OF BITS (ENOB)
SIGNAL-TO-NOISE RATIO (SNR)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
SINAD – 1.76
N=
6.02
The ratio of the fundamental sinusoid power to the total
noise power. Harmonics are excluded.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
INPUT BANDWIDTH
The ratio of the fundamental sinusoid power to the total
noise and distortion power.
Small signal (50 mV) bandwidth (3 dB) of analog input
stage.
TOTAL HARMONIC DISTORTION (THD)
DIFFERENTIAL LINEARITY ERROR (DLE)
The ratio of the total power of the first 9 harmonics to the
power of the measured sinusoidal signal.
Error in the width of each code from its theoretical value.
(Theoretical = VFS/2N)
SPURIOUS FREE DYNAMIC RANGE (SFDR)
INTEGRAL LINEARITY ERROR (ILE)
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
Linearity error refers to the deviation of each individual
code (normalized) from a straight line drawn from –FS
through +FS. The deviation is measured from the edge of
each particular code to the true straight line.
SPT7850
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Figure 1A – Timing Diagram 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
ANALOG IN
CLOCK IN
SAMPLING CLOCK
(Internal)
INVALID
VALID
1
DIGITAL OUT
2
3
4
5
6
7
8
9
10
11
DATA VALID
Figure 1B – Timing Diagram 2
tC
tCH
tCL
tCLK
CLOCK
IN
tOD
DATA
OUTPUT
Data 1
Data 0
Data 2
tDAV
DATA
VALID
tDAV
tS
Table I – Timing Parameters
DESCRIPTION
PARAMETERS
MIN
tC
2*tCLK
ns
Clock Period
tCLK
25
ns
Clock High Duty Cycle
tCH
40
50
60
%
Clock Low Duty Cycle
tCL
40
50
60
%
Clock to Output Delay (15 pF Load)
tOD
15
20
25
ns
DAV Pulse Width
tDAV
Conversion Time
Clock to DAV
TYP
MAX
tCLK
tS
16
21
UNITS
ns
26
ns
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TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
THD vs Input Frequency
80
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
80
70
ƒS = 20 MSPS
60
50
40
30
20
100
101
Input Frequency (MHz)
70
ƒs = 20 MSPS
60
50
40
30
20
102
100
102
Total Power Dissipation vs Sample Rate
Reference is Excluded = 30 mW Typ
SINAD vs Input Frequency
80
170
70
ƒS =20 MSPS
Power Dissipation (mW)
Signal-to-Noise and Distortion (dB)
101
Input Frequency (MHz)
60
50
40
30
20
100
101
Input Frequency (MHz)
150
130
110
90
70
102
5
10
15
20
Sample Rate (CLK/2) MHz
SPT7850
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Figure 2 – Typical Interface Circuit
Ref In
(+4 V)
VRHF
VRHS
VRLS
VRLF
VIN
VIN
SPT7850
VCAL
CLK IN
3.3/5
OGND
D4
Interfacing
Logics
D3
D2
D1
D0
CLK
DAV
AVDD
D10
D9
D8
D7
D6
D5
OVDD
AGND
EN
DGND* DVDD
3.3/5
Enable/Tri-State
(Enable = Active Low)
+A5
L1
AGND
+A5
+
10 µF
+5 V
Analog
+5 V
Analog
RTN
DGND
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
3.3/5
+
10 µF
+5 V
Digital
RTN
+5 V
Digital
NOTES: 1) L1 is to be located as closely to the device as possible.
2) All capacitors are 0.1 µF surface-mount unless otherwise specified.
3) L1 is a 10 µH inductor or a ferrite bead.
TYPICAL INTERFACE CIRCUIT
OPERATING DESCRIPTION
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical interface requirements when using the SPT7850 in normal
circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device
performance.
The general architecture for the CMOS ADC is shown in
the block diagram. The design contains eight identical
successive approximation ADC sections, all operating in
parallel, a 16-phase clock generator, an 11-bit 8:1 digital
output multiplexer, correction logic, and a voltage reference generator that provides common reference levels for
each ADC section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
CADEKA suggests that both the digital and the analog sup- signal in sequence. Each ADC uses 16 clock cycles to
ply voltages on the SPT7850 be derived from a single ana- complete a conversion. The clock cycles are allocated as
log supply as shown in figure 2. A separate digital supply shown in table II.
should be used for all interface circuitry. CADEKA suggests
using this power supply configuration to prevent a possible
latch-up condition on powerup.
POWER SUPPLIES AND GROUNDING
SPT7850
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6/15/01
Table II – Clock Cycles
Clock
1
2
3
4
5-15
16
Figure 3 – Ladder Force/Sense Circuit
Operation
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
11-bit SAR conversion
Data transfer
AGND
+
–
VRHF
VRHS
The 16-phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADC sections are shifted by two clock cycles so that the
analog input is sampled on every other cycle of the input
clock by exactly one ADC section. After 16 clock periods,
the timing cycle repeats. The sample rate for the configuration is one-half of the clock rate; e.g., for a 40 MHz clock
rate, the input sample rate is 20 MHz. The latency from
analog input sample to the corresponding digital output is
12 clock cycles.
VRLS
–
+
VRLF
VIN
All capacitors are 0.01 µF
• Since only eight comparators are used, a huge power
savings is realized.
• The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparators’
response to a reference zero.
• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of the
gain error are integrated to produce a calibration voltage for each ADC section.
• Capacitive displacement currents, which can induce
sampling error, are minimized since only one comparator samples the input during a clock cycle.
• The total input capacitance is very low since sections of
the converter that are not sampling the signal are isolated from the input by transmission gates.
Figure 4 – Reference Ladder
+4.0 V
External
Reference
90 mV
VRHS
(+3.91 V)
R/2
R
R
R
R=30 W (typ)
All capacitors are 0.01 µF
R
R
VOLTAGE REFERENCE
R
The SPT7850 requires the use of a single external voltage
reference for driving the high side of the reference ladder.
It must be within the range of 3 V to 5 V. The lower side of
the ladder is typically tied to AGND (0.0 V), but can be run
up to 2.0 V with a second reference. The analog input voltage range will track the total voltage difference measured
between the ladder sense lines, VRHS and VRLS.
VRLS
(0.075 V)
VRLF
(AGND)
0.0 V
75 mV
R/2
force and sense lines to AGND with a .01 µF capacitor
(chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following
considerations should be taken into account.
Force and sense taps are provided to ensure accurate
and stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations.
By using the configuration shown in figure 3, offset and
gain errors of less than ±2 LSB can be obtained.
The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with
force and sense taps shown. Due to the actual internal
structure of the ladder, the voltage drop from VRHF to VRHS
is not equivalent to the voltage drop from VRLF to VRLS.
In cases where wider variations in offset and gain can be
tolerated, VREF can be tied directly to VRHF, and AGND can
be tied directly to VRLF as shown in figure 4. Decouple
SPT7850
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6/15/01
Typically, the top side voltage drop for VRHF to VRHS will
equal:
Upon powerup, the SPT7850 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10-bit LSB. Since the calibration algorithm is an
oversampling process, a minimum of 10,000 clock cycles
are required. This results in a minimum calibration time
upon powerup of 250 µsec for a 20 MHz sample rate.
Once calibrated, the SPT7850 remains calibrated over
time and temperature.
VRHF – VRHS = 2.25 % of (VRHF – VRLF) (typical),
and the bottom side voltage drop for VRLS to VRLF will
equal:
VRLS – VRLF = 1.9 % of (VRHF – VRLF) (typical).
Figure 4 shows an example of expected voltage drops for
a specific case. VREF of 4.0 V is applied to VRHF, and VRLF
is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V),
and a 75 mV increase is seen at VRLS (= 0.075 V).
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7850 to remain in calibration.
ANALOG INPUT
INPUT PROTECTION
VIN is the analog input. The input voltage range is from
VRLS to VRHS (typically 4.0 V) and will scale proportionally
with respect to the voltage reference. (See voltage reference section.)
All I/O pads are protected with an on-chip protection
circuit shown in figure 6. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition
times.
The drive requirements for the analog inputs are very
minimal when compared to most other converters due to
the SPT7850’s extremely low input capacitance of only
5 pF and very high input resistance of 50 kΩ.
Figure 6 – On-Chip Protection Circuit
VDD
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 5.
120 W
Figure 5 – Recommended Input Protection Circuit
+V
Analog
120 W
AVDD
Pad
D1
Buffer
ADC
47 W
D2
POWER SUPPLY SEQUENCING CONSIDERATIONS
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decoupling networks with large time constants that could delay
VDD power to the device.
–V
D1 = D2 = Hewlett-Packard HP5712 or equivalent
CALIBRATION
CLOCK INPUT
The SPT7850 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 10-bit accuracy
during device operation. This process is completely transparent to the user.
The SPT7850 is driven from a single-ended TTL-input
clock. Because the pipelined architecture operates on the
rising edge of the clock input, the device can operate over
a wide range of input clock duty cycles without degrading
the dynamic performance. The device’s sample rate is
1/2 of the input clock frequency. (See figure 1A timing
diagram.)
SPT7850
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DIGITAL OUTPUTS
OVERRANGE OUTPUT
The digital outputs (D0–D10) are driven by a separate
supply (OVDD) ranging from +3 V to +5 V. This feature
makes it possible to drive the SPT7850’s TTL/CMOScompatible outputs with the user’s logic system supply.
The format of the output data (D0–D9) is straight binary.
(See table III.) The outputs are latched on the rising edge
of CLK. These outputs can be switched into a tri-state
mode by bringing EN high.
The OVERRANGE OUTPUT (D10) is an indication that
the analog input signal has exceeded the positive fullscale input voltage by 1 LSB. When this condition occurs,
D10 will switch to logic 1. All other data outputs (D0 to D9)
will remain at logic 1 as long as D10 remains at logic 1.
This feature makes it possible to include the SPT7850 in
higher resolution systems.
EVALUATION BOARD
Table III – Output Data Information
The EB7850 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7850.
This board includes a reference circuit, clock driver circuit,
output data latches, and an on-board reconstruction of the
digital data. An application note describing the operation
of this board, as well as information on the testing of the
SPT7850, is also available. Contact the factory for price
and availability.
ANALOG INPUT
OVERRANGE
OUTPUT CODE
D10
D9–D0
+F.S. + 1/2 LSB
1
11 1111 1111
+F.S. –1/2 LSB
0
1 1 1 1 1 1 1 1 1Ø
+1/2 F.S.
0
ØØ ØØØØ ØØØØ
+1/2 LSB
0
00 0000 000Ø
0.0 V
0
00 0000 0000
(Ø indicates the flickering bit between logic 0 and 1.)
SPT7850
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6/15/01
PACKAGE OUTLINES
28-Lead SOIC
28
SYMBOL
A
B
C
D
E
F
G
H
I
I H
1
INCHES
MIN
MAX
0.699
0.709
0.005
0.011
0.050 typ
0.018 typ
0.0077
0.0083
0.090
0.096
0.031
0.039
0.396
0.416
0.286
0.292
MILLIMETERS
MIN
MAX
17.75
18.01
0.13
0.28
1.27 typ
0.46 typ
0.20
0.21
2.29
2.44
0.79
0.99
10.06
10.57
7.26
7.42
INCHES
MIN
MAX
0.346
0.362
0.272
0.280
0.346
0.362
0.272
0.280
0.031 typ
0.012
0.016
0.053
0.057
0.002
0.006
0.037
0.041
0.007
0°
7°
0.020
0.030
MILLIMETERS
MIN
MAX
8.80
9.20
6.90
7.10
8.80
9.20
6.90
7.10
0.80 BSC
0.30
0.40
1.35
1.45
0.05
0.15
0.95
1.05
0.17
0°
7°
0.50
0.75
A
F
B
C
D
H
G
E
32-Lead TQFP
G H
A
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
L
B
C
D
I
J
E
F
K
L
SPT7850
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6/15/01
PACKAGE OUTLINES
28-Lead Skinny PDIP
A
SYMBOL
A
B
C
D
E
F
G
H
I
B
D
F
C
G
INCHES
NOM MAX
0.288 0.295
1.365 1.370
0.130
0.055 0.060 0.065
0.100 BSC
0.020
0.120 0.130 0.135
0.300 BSC
0.430
MIN
0.280
1.360
MILLIMETERS
MIN
NOM MAX
7.112 7.315 7.493
34.544 34.671 34.798
3.302
1.397 1.524 1.651
2.540 BSC
0.508
3.048 3.302 3.429
7.620 BSC
10.922
E
H
I
SPT7850
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6/15/01
PIN ASSIGNMENTS
PIN FUNCTIONS
AGND
1
28
VRHF
2
27 D9
VRHS 3
26 D8
D10
Name
Function
AGND
Analog Ground
VRHF
Reference High Force
VRHS
Reference High Sense
D7
VRLS
Reference Low Sense
VRLS 5
24 D6
VRLF
Reference Low Force
VRLF
6
23 D5
VCAL
Calibration Reference
VIN
7
22
VIN
Analog Input
AVDD
Analog VDD
DVDD
Digital VDD
DGND
Digital Ground
CLK
Input Clock ƒCLK = FS (TTL)
N/C
AGND
VCAL
25
4
PDIP
and
SOIC
8
21
OVDD
OGND
20 D4
9
AVDD 10
19
D3
DVDD 11
18
D2
DGND 12
17 D1
EN
Output Enable
D0–9
Tri-State Data Output, (D0=LSB)
DAV
Data Valid Output
OVDD
Digital Output Supply
OGND
Digital Output Ground
N/C
No Connect
D8
EN
D9
15
D10
DAV 14
AGND
Tri-State Output Overrange
VRHF
D10
AGND
D0
VRLS
16
VRHS
CLK 13
25
27
26
28
30
29
31
32
VRLF
1
24
D7
VIN
2
23
D6
AGND
3
22
D5
AGND
4
21
OVDD
TQFP
VCAL
5
20
OGND
AVDD
6
19
D4
AVDD
7
18
D3
DVDD
8
17
D2
D1
EN
16
14
CLK
DAV
15 D0
13
11 DGND
DVDD
DGND
12
9
10
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE TYPE
SPT7850SCN
0 to +70 °C
28L Plastic DIP (300 mil)
SPT7850SIS
–40 to +85 °C
28L SOIC
SPT7850SCT
0 to +70 °C
32L TQFP
SPT7850
13
6/15/01