CADEKA SPT7935SIT

SPT7935
12-BIT, 20 MSPS, 79 mW A/D CONVERTER
FEATURES
APPLICATIONS
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12-Bit, 20 MSPS Analog-to-Digital Converter
Monolithic CMOS
Internal Track-and-Hold
Low Input Capacitance: 1.4 pF
Low Power Dissipation: 79 mW
2.8 – 3.6 V Power Supply Range
TTL-Compatible Outputs
GENERAL DESCRIPTION
The SPT7935 12-bit, 20 MSPS analog-to-digital converter
has a pipelined converter architecture built in a CMOS
process. It delivers high performance with a typical power
dissipation of only 79 mW. With low distortion and high
dynamic range, this device offers the performance needed
CCD Imaging Cameras and Sensors
Medical Imaging
RF Communications
Document and Film Scanners
Electro-Optics
Transient Signal Analysis
Handheld Equipment
for imaging, multimedia, telecommunications and instrumentation applications.
The SPT7935 is available in a 44-lead Thin Quad Flat Pack
(TQFP) package in the industrial temperature range (–40 to
+85 °C).
BLOCK DIAGRAM
ADC
+
DAC
– G=2
D<1…0> Pipeline Stage
VIN+
VIN–
VREF+
Stage
1
Stage
2
Stage
9
Stage
10
VREF–
CLK
Clock
Driver
Digital Delays, Error Correction and Output
12
Digital Output (D0 – D11)
2-Bit
ADC
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VDD1 .................................................................... –0.5 V to +6 V
VDD2 .................................................................... –0.5 V to +6 V
VDD3 .................................................................... –0.5 V to +6 V
Temperature
Operating Temperature ............................. –40 to +85 °C
Storage Temperature ............................... –65 to +125 °C
Input Voltages
Analog Input ................................. –0.5 V to (VDD +0.5 V)
Digital Input .................................. –0.5 V to (VDD +0.5 V)
VREF+ .......................................... –0.5 V to (VDD +0.5 V)
VREF– .......................................... –0.5 V to (VDD +0.5 V)
CLK .............................................. –0.5 V to (VDD +0.5 V)
Note: 1. Operation at any Absolute Maximum Rating is not
implied. See Electrical Specifications for proper
nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN–TMAX , VDD1=VDD2=VDD3=3.3 V, VREF–=1.0 V, VREF+=2.0 V, Common Mode Voltage=1.65 V, ƒCLK=20 MSPS, Bias 1=90 µA,
Bias 2=9.5 µA, Differential Input, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
DC Accuracy
Resolution
Differential Linearity
Integral Linearity
No Missing Codes
Analog Input
Input Voltage Range (Differential)
Common Mode Input Voltage
Input Capacitance
Input Bandwidth (Large Signal)
Offset (Mid-scale)
Gain Error
Reference Voltages
Reference Input Voltage Range
(VREF+ – VREF–)
Negative Reference Voltage (VREF–)
Positive Reference Voltage (VREF+)
Common Mode Output Voltage (VCM)
VREF+ Current
VREF– Current
MIN
IO = –1 µA
Switching Performance
Maximum Conversion Rate
Pipeline Delay
(See Timing Diagram)
Aperture Delay Time (TAP)
Aperture Jitter Time
UNITS
Bits
LSB
LSB
IV
IV
V
V
V
V
±0.6
1.2
±1.0
1.65
1.4
120
±1.0
0.3
±1.7
1.9
V
V
pF
MHz
% FSR
% FSR
IV
0.6
1.0
1.7
V
IV
IV
VI
V
V
0.9
1.9
1.3
1.0
2.0
1.65
35
–25
1.3
2.6
1.8
V
V
V
µA
µA
VI
IV
20
V
V
Dynamic Performance
Effective Number of Bits
ƒIN = 5.0 MHz
ƒIN = 10.0 MHz
Signal-To-Noise Ratio
ƒIN = 5.0 MHz
ƒIN = 10.0 MHz
Total Harmonic Distortion
ƒIN = 5.0 MHz
ƒIN = 10.0 MHz
MAX
12
±0.6
±3.0
Guaranteed
V
V
VI
VIN+=VIN–=VCM
SPT7935
TYP
7.5
MHz
Clocks
5
10
ns
ps-rms
VI
V
9.2
9.8
9.0
Bits
Bits
VI
V
59
62
58
dB
dB
VI
V
–68
–60
–61
dB
dB
SPT7935
2
7/12/00
ELECTRICAL SPECIFICATIONS
TA=TMIN–TMAX , VDD1=VDD2=VDD3=3.3 V, VREF–=1.0 V, VREF+=2.0 V, Common Mode Voltage=1.65 V, ƒCLK=20 MSPS, Bias 1=90 µA,
Bias 2=9.5 µA, Differential Input, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
Dynamic Performance–Continued
Signal-To-Noise and Distortion
ƒIN = 5 MHz
ƒIN = 10 MHz
Spurious Free Dynamic Range
ƒIN = 5.0 MHz
ƒIN = 10.0 MHz
Differential Phase
Differential Gain
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
CLK to Output Delay Time (tD)
VIN = GND
VIN = VDD
IO = -2 mA
IO = +2 mA
Power Supply Requirements
Supply Voltages
VDD1, VDD2, VDD3
Supply Current
IDD
Power Dissipation
Power Supply Rejection Ratio (PSRR)
TEST LEVEL CODES
TEST LEVEL
I
All electrical characteristics are subject to the
following conditions: All parameters having
II
min/max specifications are guaranteed. The
Test Level column indicates the specific
III
device testing actually performed during proIV
duction and Quality Assurance inspection.
Any blank section in the data column indiV
cates that the specification is not tested at the
specified condition.
VI
MIN
SPT7935
TYP
MAX
UNITS
VI
V
57
61
56
dB
dB
VI
V
V
V
62
70
61
0.2
0.5
dB
dB
Degrees
%
VI
VI
VI
VI
V
80% VDD
VI
VI
IV
85% VDD
IV
VI
VI
V
1.8
20% VDD
±1
µA
±1
µA
pF
4
95% VDD
0.1
8
0.4
12
V
V
ns
2.8
3.3
3.6
V
24
79
67
30
100
mA
mW
dB
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested at
the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and
characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range.
SPT7935
3
7/12/00
TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Sample Rate
80
80
70
70
60
THD, SNR, SINAD (dB)
THD, SNR, SINAD (dB)
THD, SNR, SINAD vs Input Frequency
THD
SNR
SINAD
50
40
THD
THD
SNR
SNR
60
SINAD
SINAD
50
40
30
30
20
20
100
10 0
102
101
Input Frequency (MHz)
102
101
Sample Rate (MSPS)
Note: Bias1 and Bias2 currents optimized for each sample rate.
THD, SNR, SINAD vs Temperature
Power Dissipation vs Sample Rate
70
150
125
Power Dissipation (mW)
THD
66
64
SNR
62
SINAD
60
100
75
50
25
58
0
56
0
25
10 0
70
Temperature (°C)
102
101
Sample Rate (MSPS)
Note: Bias1 and Bias2 optimized for each sample rate.
Bias 1 Voltage vs Bias 1 Current
Bias 2 Voltage vs Bias 2 Current
3.4
0.90
3.2
0.85
3.0
0.80
2.8
VBias2 (V)
VBias1 (V)
THD, SNR, SINAD (dB)
68
IBias1 VBias1
30
2.19
60
2.53
90
2.79
120
3.00
150
3.22
2.6
2.4
IBias2
3
6
9
12
15
0.75
0.70
VBias2
0.6975
0.7535
0.796
0.8295
0.8595
0.65
2.2
2.0
0.60
0
30
60
90
120
150
180
0
IBias1 (µA)
3
6
9
12
15
18
IBias2 (µA)
SPT7935
4
7/12/00
Figure 1 – Timing Diagram
Sampling Points
N
N-1
N+1
tAP
N+2
N+6
N+8
N+7
AIN
CLK
tD
DOUT
N-2
N-1
N
GENERAL DESCRIPTION
TYPICAL INTERFACE CIRCUIT
The SPT7935 is an ultra-low power, 12-bit, 20 MSPS ADC.
It has a pipelined architecture and incorporates digital error
correction of the 11 most significant bits. This error correction
ensures good linearity performance for input frequencies up
to Nyquist. The inputs are fully differential, making the device
insensitive to system-level noise. This device can also be
used in a single-ended mode. (See analog input section.)
With the power dissipation roughly proportional to the sampling rate, this device is ideal for very low power applications
in the range of 1 to 20 MSPS.
The SPT7935 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7935 in
normal circuit operation. The following sections provide
a description of the functions and outline critical performance criteria to consider for achieving the optimal device
performance.
ANALOG INPUT
The input of the SPT7935 can be configured in various ways
depending on if a single-ended or differential, AC- or DCcoupled input is desired.
Figure 2 – Typical Interface Circuit
+3.3 V
CLK In
(3 V Logic)
4.7 µF
Ref– In
10 µF
+
.01 µF
+
+3.3 V
(+1.15 V)
Ref+ In
+3.3 V Digital
.01 µF
(+2.15 V)
+
.01 µF
11
1
N/C
GND
CLK
VDD3
VDD2
VDD1
VDD2
VDD1
VDD1
N/C
VREF+
12
VREF–
4.7 µF
0.1 µF
N/C
VDD3 44
(LSB)
D0
D1
N/C
90 µA
D2
GND
Bias1
9.5 µA
(+1.65 V)
RF In
68 pF
51
VCM
D5
GND
D6
VIN+
D7
VIN–
D8
GND
GND
23
33
AGND
Interfacing
3 V Logic
D9
D10
Minicircuit
T1-6T
D4
D11
22
D3
U1
SPT7935
Bias2
.01 µF
Decoupling Cap
34
(MSB)
FB
DGND
Notes: All VDD1, VDD2 and VDD3 should be tied together.
FB = Ferrite Bead; must be placed as close to U1 as possible.
SPT7935
5
7/12/00
The AC coupled input is most conveniently implemented
using a transformer with a center tapped secondary winding.
The center tap is connected to the VCM pin as shown in
figure 2. To obtain low distortion, it is important that the
selected transformer does not exhibit core saturation at the
full-scale voltage. Proper termination of the input is important
for input signal purity. A small capacitor across the inputs
attenuates kickback noise from the internal sample and hold.
COMMON MODE VOLTAGE
REFERENCE CIRCUIT
The SPT7935 has an on-board common mode voltage reference circuit (VCM). It is typically one-half of the supply voltage
and can drive loads of up to 20 µA. This circuit is commonly
used to drive the center tap of the RF transformer in fully
differential applications. For single-ended applications, this
output can be used to provide the level shifting required for
the single-to-differential converter conversion circuit.
Figure 3 illustrates a solution (based on operational amplifiers) that can be used if a DC coupled single-ended input is
desired. The selection criteria of the buffer op-amps is as
follows:
– Open loop gain >75 dB
– Gain bandwidth product >50 MHz
– Total harmonic distortion ≤–75 dB
– Signal to noise ratio >75 dB
BIAS CURRENT CIRCUITS
The bias currents suggested (Bias 1 and Bias 2 in figure 2)
optimize device performance for the stated sample rate of
20 MSPS. To achieve the best dynamic performance when
operating the device at sample rates other than 20 MSPS, the
bias current levels should be adjusted. Table I shows the
settings for Bias 1 and Bias 2 for selected sample rates. The
“Bias Voltage vs Bias Current” graphs on page 4 show the
relationship between the bias current and the bias voltage.
POWER SUPPLIES AND GROUNDING
The SPT7935 is operated from a single power supply in the
range of 2.8 to 3.6 volts. Nominal operation is suggested to
be 3.3 volts. All power supply pins should be bypassed as
close to the package as possible. The analog and digital
grounds should be connected together with a ferrite bead as
shown in the typical interface circuit and as close to the ADC
as possible.
Table I – Sample Rate Settings
Sample Rate (MHz)
1
5
10
20
REFERENCES
Bias 1 (µA)
20
50
80
90
Bias 2 (µA)
3.5
6.5
8.0
9.5
The SPT7935 has a differential analog input. The voltages
applied to the VREF+ and VREF- pins determine the input
voltage range and are equal to ±(VREF+ – VREF–). This
voltage range will be symmetric about the common mode
voltage. Externally generated reference voltages must be
connected to these pins. (See figure 2, Typical Interface
Circuit.) For best performance, these voltages should be
symmetrical about the midpoint of the supply voltage.
Figure 3 – DC-Coupled Single Ended to Differential Conversion (Power Supplies and Bypassing are Not Shown)
R3
R3
R
–
VCM
ADC
+
Input
Voltage
(±0.5 V)
(R3)/2
R
51 Ω
–
R2
+
VIN+
15 pF
R2
VIN–
51 Ω
R
51 Ω
+
–
R
R
SPT7935
6
7/12/00
CLOCK
DIGITAL OUTPUTS
The SPT7935 accepts a low voltage CMOS logic level at
the CLK input. The duty cycle of the clock should be kept as
close to 50% as possible. Because consecutive stages in the
ADC are clocked in opposite phase to each other, a non-50%
duty cycle reduces the settling time available for every other
stage and thus potentially causing a degradation of dynamic
performance.
The digital output data appears in an offset binary code at
3.3 V CMOS logic levels. A negative full scale input results in
an all zeros output code (000…0). A positive full scale input
results in an all 1’s code (111…1). The output data is available
7.5 clock cycles after the data is sampled. The input signal is
sampled on the high to low transition of the input clock. Output
data should be latched on the low to high clock transition as
shown in figure 1, the Timing Diagram. The output data is
invalid for the first 20 clock cycles after the device is powered up.
For optimal performance at high input frequencies, the clock
should have low jitter and fast edges. The rise/fall times
should be kept shorter than 2 ns. Overshoot and undershoot
should be avoided. Clock jitter causes the noise floor to rise
proportional to the input frequency. Because jitter can be
caused by crosstalk on the PC board, it is recommended that
the clock trace be kept as short as possible and standard
transmission line practices be followed.
EVALUATION BOARD
The EB7935 Evaluation Board is available to aid designers in
demonstrating the full performance capability of the
SPT7935. The board includes an on-board clock driver,
adjustable voltage references, adjustable bias current circuits, single-to-differential input buffers with adjustable levels, a single-to-differential transformer (1:1), digital output
buffers and 3.3/5 V adjustable logic outputs. An application
note (AN7935) is also available which describes the operation of the evaluation board and provides an example of the
recommended power and ground layout and signal routing.
Contact the factory for price and availability.
PACKAGE OUTLINE
44L TQFP
A
B
INCHES
C
D
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.472 Typ
12.00 Typ
B
0.394 Typ
10.00 Typ
C
0.394 Typ
10.00 Typ
D
0.472 Typ
12.00 Typ
E
0.031 Typ
F
0.012
0.018
0.300
0.45
G
0.053
0.057
1.35
1.45
H
0.002
0.006
0.05
0.15
0.030
0.450
0.750
0.80 Typ
I
0.018
J
0.039 Typ
1.00 Typ
K
0-7°
0-7°
Index
Pin 1
E
F
G
K
I
H
J
SPT7935
7
7/12/00
PIN ASSIGNMENTS
PIN FUNCTIONS
34
37
D9
38
35
D6
39
D8
D5
40
D7
D4
41
36
D2
43
42
D3
D1
44
D0 (LSB)
VDD3
Name
Function
VIN+, VIN–
Analog Inputs
VREF+, VREF–
External Reference Inputs
CLK
Input Clock
VCM
Common Mode Output Voltage
(1.65 V typ)
Bias Current (90 µA typ)
VDD2
6
28
GND
Bias 2
Bias Current (9.5 µA typ)
VDD1
7
27
GND
D0 – D11
Digital Outputs (D0 = LSB)
VDD1
8
26
GND
GND
Analog Ground
VDD1
9
25
GND
VREF-
10
24
GND
VREF+
11
23
GND
VDD1
VDD2
VDD3
Analog Power Supply
Digital Power Supply
Digital Output Power Supply
N/C
No Connect Pins. Recommended to
connect to analog ground.
N/C
GND
Bias 1
22
GND
VIN-
29
21
5
VIN+
VDD2
GND
GND
20
30
19
4
VCM
VDD3
Bias 2
GND
18
31
Bias 1
3
17
N/C
16
D11 (MSB)
N/C
32
15
2
N/C
CLK
N/C
D10
13
33
14
1
12
GND
ORDERING INFORMATION
PART NUMBER
SPT7935SIT
TEMPERATURE RANGE
PACKAGE TYPE
–40 to +85 °C
44L TQFP
SPT7935
8
7/12/00