CADEKA SPT7866SCR

SPT7866
10-BIT, 60 MSPS A/D CONVERTER
TECHNICAL DATA
NOVEMBER 20, 2001
FEATURES
APPLICATIONS
• 60 MSPS maximum sample rate
• 9.4 effective number of bits at ƒ IN = 10 MHz and
ƒS = 60 MSPS
• 2V P-P full-scale input range
• Differential input 2.5 V common mode
• Internal or external voltage reference
• Common-mode voltage reference output
• +3 V / +5 V digital output logic compatibility
• +5 V analog power supply
• Sleep mode power dissipation: 55 mW
• Video imaging
• Medical imaging
• Radar receivers
• IR imaging
• Digital communications
GENERAL DESCRIPTION
processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS compatible to
interface with TTL/CMOS logic systems. Output data format is offset binary.
The SPT7866 is a 10-bit, 60 MSPS analog-to-digital converter with low power dissipation at only 480 mW typical at
60 MSPS with a power supply of +5.0 V. The digital outputs
are +3 V or +5 V, and are user selectable. The SPT7866
has incorporated proprietary circuit design and CMOS
The SPT7866 is available in a 28-lead SSOP package
over the commercial temperature range.
BLOCK DIAGRAM
VDD
GND
Sleep
VCM
Bias
Cell
Bandgap
Reference
EXT/INT
REFH
REFL
VIN
VIN
THA
10-BIT
60 MSPS
ADC
10
Data
Output
Latches
& Buffers
2
CLK, CLK
GND
OVDD
1
10
OR
D0–D9
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 °C
Supply Voltages
VDD ...................................................................... 6.0 V
OVDD .................................................................... 6.0 V
Output
Digital Outputs .............................. –0.3 V to VDD +0.7 V
Temperature
Operating Temperature ............................... 0 to +70 °C
Storage Temperature ............................ –65 to +150 °C
Input Voltages
Analog Input ................................. –0.3 V to VDD +0.7 V
CLK Input ..................................... –0.3 V to VDD +0.7 V
Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical
applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, ƒS=60 MSPS, VREFH=3.0 V, VREFL=2.0 V, OVDD=3.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
Resolution
DC Accuracy
Differential Linearity Error (DLE)
Integral Linearity Error (ILE)
@ +25 °C
full temperature
@ +25 °C
full temperature
V
V
V
V
VI
Analog Input
Input Voltage Range (Differential)
Input Common Mode (VCM)
Input Capacitance
Input Bandwidth
Common Mode Rejection Ratio (CMRR)
V
IV
V
V
V
Timing Characteristics
Conversion Rate
Pipeline Delay (Latency)
Output Delay (tD)
Aperture Delay Time (tAP)
Aperture Jitter Time
VI
IV
IV
V
V
Signal-to-Noise Ratio (SNR)
ƒIN = 10 MHz, ƒCLK = 60 MSPS
Total Harmonic Distortion (THD)
ƒIN = 10 MHz, ƒCLK = 60 MSPS
Signal-to-Noise and Distortion (SINAD)
ƒIN = 10 MHz, ƒCLK = 60 MSPS
Spurious Free Dynamic Range (SFDR)
ƒIN = 10 MHz, ƒCLK = 60 MSPS
SPT7866
TYP
MAX
10
No Missing Codes
Dynamic Performance
Effective Number of Bits (ENOB)
ƒIN = 10 MHz, ƒCLK = 60 MSPS
MIN
Bits
±0.8
±0.8
±0.6
±1.0
Guaranteed
2
UNITS
±1
2.5
4
LSB
LSB
LSB
LSB
3
97
57
60
V
V
pF
MHz
dB
6
7
1
11
MSPS
clocks
ns
ns
ps (rms)
25 °C
0 °C to +70 °C
I
IV
9.3
9.3
9.4
9.4
Bits
Bits
25 °C
0 °C to +70 °C
I
IV
58
57
59
59
dB
dB
25 °C
0 °C to +70 °C
I
IV
25 °C
0 °C to +70 °C
I
IV
57
57
58
58
dB
dB
25 °C
0 °C to +70 °C
I
IV
67
67
73
71
dB
dB
–71
–69
–66
–66
dB
dB
SPT7866
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ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, ƒS=60 MSPS, VREFH=3.0 V, VREFL=2.0 V, OVDD=3.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
Power Supply Requirements
VDD Voltage (Analog Supply)
OVDD Voltage (Output Supply)
VDD Current
OVDD Current
Power Dissipation
External Voltage Reference
Internal Voltage Reference
Sleep Mode Power Dissipation
External Voltage Reference
Internal Voltage Reference
Power Supply Rejection Ratio (PSRR)
SPT7866
TYP
MAX
UNITS
5.0
3.0/5.0
98
10
5.25
5.25
V
V
mA
mA
VI
VI
482
480
513
512
mW
mW
VI
VI
V
45
55
51
47
57
mW
mW
dB
2.6
2.05
3.05
V
ppm/°C
kΩ
V
V
IV
IV
VI
VI
MIN
4.75
2.7
Internal References
Common Mode Voltage Reference (VCM) IO = –1 µA
Common Mode Voltage Tempco
Output Impedance (VCM)
(EXT/INT) = 0
Reference Low Output Voltage (VREFL)
Reference High Output Voltage (VREFH) (EXT/INT) = 0
VI
V
V
VI
VI
1.95
2.95
2.5
100
1.4
2.0
3.0
External References
Reference Low Input Voltage Range
Reference High Input Voltage Range
(EXT/INT) = 1
(EXT/INT) = 1
IV
IV
1.7
2.7
2.0
3.0
2.3
3.3
V
V
IO = –2 mA
IO = 2 mA
VI
VI
85% OVDD
90% OVDD
0.2
OVDD
0.4
V
V
Digital Inputs
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VI
VI
VI
VI
80% VDD
20% VDD
±100
±100
V
V
µA
µA
Clock Inputs
Clock Inputs High Voltage
Clock Inputs Low Voltage
Clock Inputs High Current
Clock Inputs Low Current
VI
VI
VI
VI
2
5
0.4
±115
±115
V
V
µA
µA
Digital Outputs
Output Voltage High
Output Voltage Low
TEST LEVEL CODES
TEST LEVEL
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection. Any
blank section in the data column indicates that the
specification is not tested at the specified
condition.
I
II
2.4
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested
at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and
characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
III
IV
V
VI
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TYPICAL PERFORMANCE CHARACTERISTICS
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
30
40
50
60
70
Sample Rate (MSPS)
DLE Versus Temperature
LSB
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–20
0
20
40
Temperature (Degrees C)
80
60
60
70
ƒIN = 1 kHz
ƒS = 60 MSPS
0
20
40
Temperature (Degrees C)
80
60
SNR, SINAD, –THD, SFDR Versus Temperature
ƒIN = 10 MHz
SNR, SINAD, –THD, SFDR (dB)
SNR, SINAD, –THD, SFDR (dB)
50
Sample Rate (MSPS)
80
70
SFDR
65
–THD
60
SNR
55
SINAD
50
45
40
LSB
ƒIN = 1 kHz
ƒS = 60 MSPS
75
45
ƒIN = 1 kHz
ILE Versus Temperature
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–20
SNR, SINAD, –THD, SFDR Versus Sample Rate
80
ILE Versus Sample Rate
LSB
ƒIN = 1 kHz
LSB
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
30
DLE Versus Sample Rate
50
55
60
65
70
75
75
70
–THD
65
SNR
60
55
50
45
–20
80
SFDR
SINAD
ƒS = 60 MHz
ƒIN = 10 MHz
0
20
40
60
80
Temperature (Degrees C)
Sample Rate (MSPS)
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VIN
SPT7866
+
10
0.1
+
0.1
10
0.1
0.1
+ 10
RT2
50 W
Buffer
+D3/5
+D3/5
DGND
+ 10
+A3/5
AGND
AGND
50 W
10
0.1
+A5
(LSB)
CLK
+A5
EXT/INT
REFL
REFH
CLK
Ext
OGND
VIN
OVDD
Mini-Circuits
T1–6T or
T1–1T
10
GND
+
RT1
50 W
VDD
0.1
(MSB)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VCM
T1
AIN
OR
Sleep
Sleep
Logic Interface Circuit
Figure 1 – Typical Interface Circuit
+
Ferrite Bead
Mini-Circuits
T1–6T or
T1–1T
1 kW
+A5
T2
TYPICAL INTERFACE CIRCUIT
1 kW
CLKIN
Circuits T1-6T or T1-1T. Proper termination of the input is
important for input signal purity. A small capacitor (typically
68 pF) across the inputs attenuates kickback noise from
the sample-and-hold. A small capacitor (1 nF) between
VCM and ground has also been proven to be advantageous.
REFERENCES
The SPT7866 has a differential analog input. The input
range is determined by the voltages VIN and VIN applied to
reference pins REFH and REFL respectively, and is equal
to ±(VIN–VIN). Externally generated reference voltages
connected to REFH and REFL should be symmetric
around 2.5 V. The input range can be defined between
±0.6 V and ±1.5 V. An internal reference exists, providing
reference voltages at pins REFH and REFL equal to +3.0 V
(VREFH) and +2.0 V (VREFL). These can be connected to
REFH and REFL by connecting pin EXT/INT to GND. The
references should be bypassed as close to the converter
pins as possible using 100 nF capacitors in parallel with
smaller capacitors (e.g. 220 pF) to ground.
If a DC-coupled, single-ended input is wanted, a solution
based on operational amplifiers, as shown in figure 2, is
usually preferred. The AD8138 is suggested for low distortion and video bandwidth. Lower cost operational amplifiers may be used if the demands are less strict.
Figure 2 – DC-Coupled, Single-Ended to Differential
Conversion (power supplies and bypassing
not shown)
51 W
ANALOG INPUT
470 W
Input
Offset
The input of the SPT7866 can be configured in various
ways, dependent upon whether a single-ended or differential, AC- or DC-coupled input is wanted.
Analog
In
AD8138
470 W
100 W
AD8138
VIN
15 pF
100 W
AC-coupled input is most conveniently implemented using
a transformer with a center-tapped secondary winding.
The center tap is connected to the VCM node, as shown in
figure 1. In order to obtain low distortion, it is important that
the selected transformer does not exhibit core saturation
at full scale. Excellent results are obtained with the Mini-
ADC
51 W
VIN
51 W
470 W
470 W
51 W
AD8138
470 W
SPT7866
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11/20/01
DIFFERENTIAL CLOCK INPUT
ates from 50%, every second stage has a shorter time for
settling; thus it operates less accurately, causing degradation of SNR.
The SPT7866 clock can be driven differentially or singleended. When driven differentially, CLK and CLK accommodate differential sinusodial signals centered around VDD/2.
The peak-to-peak value should be 0.8 V. In order to preserve accuracy at high input frequency, it is important that
the clock have low jitter. The differential clock input is made
to allow a low-jitter clock design. To ensure low jitter, the
differential input should be a pure sine wave with low white
noise floor.
In order to preserve accuracy at high input frequency, it is
important that the clock have low jitter and steep edges.
Rise/fall times should be kept shorter than 2 ns whenever
possible. Overshoot should be minimized. Low jitter is especially important when converting high-frequency input
signals. Jitter causes the noise floor to rise proportionally
to input signal frequency. Jitter may be caused by crosstalk
on the PCB. It is therefore recommended that the clock
trace on the PCB be made as short as possible.
SINGLE-ENDED CLOCK INPUT
For single-ended operation, the CLK node is internally
biased to 1.5 V, and should externally be decoupled to
ground by a capacitor. A CMOS logic level clock (5 V or
3 V) is applied at the CLK node. (To get an inverted clock
input, CLK should be decoupled and the clock signal applied at the CLK node). The duty cycle of the clock should
be close to 50%. Consecutive pipeline stages in the ADC
are clocked in antiphase. With a 50% duty cycle, every
stage has the same time for settling. If the duty cycle devi-
DIGITAL OUTPUTS
The digital output data appears in offset binary code at
CMOS logic levels. Full-scale negative input results in output code 000...0. Full-scale positive input results in output
code 111...1. Output data is available 6 clock cycles after
the data is sampled. The analog input is sampled one
aperture delay (tAP) after the high-to-low clock transition.
Output data should be sampled as shown in the timing diagram (figure 5). The OR pin is an out-of-range pin; if the
outputs go either over or under range, OR is set high.
Figure 3 – Driving Differential Inputs with a
Differential Configuration
VIHD
VICM
VILD
PCB LAYOUT AND DECOUPLING
A well designed PCB is necessary to get good spectral
purity from any high-performance ADC. A multilayer PCB
with a solid ground plane is recommended for optimum
performance. If the system has a split analog and digital
ground plane, it is recommended that all ground pins on
the ADC be connected to the analog ground plane. It is our
experience that this gives the best performance. The
power supply pins should be bypassed using 100 nF
surface mounted capacitors as close to the package pins
as possible. Analog and digital supply pins should be
separately filtered.
VID
Figure 4 – Driving Differential Inputs with a
Single-Ended Configuration
VIH
VICM
VIL
Figure 5 – Timing Diagram
N–1
N
N+1
N+2
N+3
AIN
Clock
Clock
tD
tH
tAP
Data
Data
N–1
Data
N
Data
N+1
Data
N+2
SPT7866
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PACKAGE OUTLINE
28-Lead SSOP
INCHES
28
I H
SYMBOL
MIN
MAX
MIN
MAX
A
0.390
0.413
9.90
10.50
B
0.002
0.008
0.05
0.20
C
1
A
MILLIMETERS
0.026 typ
0.65 BSC
D
0.009
0.015
0.22
0.38
E
0.004
0.010
0.09
0.25
F
0.065
0.073
1.65
1.85
G
0.022
0.037
0.55
0.95
H
0.291
0.323
7.40
8.20
I
0.197
0.220
5.00
5.60
F
B
C
D
H
G
E
SPT7866
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11/20/01
PIN ASSIGNMENTS
PIN FUNCTIONS
Name Function
GND
Analog ground
VDD
Analog +5 V
OGND
Output ground
GND
1
28
D0
VDD
2
27
D1
REFL
3
26
D2
REFH
4
25
D3
EXT/INT
5
24
D4
VCM
6
23
OGND
GND
7
22
OVDD
VDD
8
21
OGND
VIN
9
20
OVDD
VIN 10
19
D5
Sleep 11
18
D6
CLK 12
17
D7
CLK 13
16
D8
OR 14
15
D9 (MSB)
SPT7866
28L SSOP
OVDD
REFL
Supply voltage for digital outputs 3 V/5 V
Reference pin low, input for external
reference, bypass with capacitor (10 µF)
when internal reference is selected.
REFH
Reference pin high, input for external
reference, bypass with capacitor (10 µF)
when internal voltage is selected.
VCM
2.5 V common mode voltage reference output
VIN
Non-inverted analog input
VIN
Inverted analog input
CLK
Clock input pin
CLK
Complement of clock input pin, internally
biased to 1.5 V; if single-ended clock is used,
bypass to GND with 10 µF
D0–D9
Digital outputs; D0 = LSB; 3 V/5 V compatible
OR
Out-of-range bit; 3 V/5 V compatible
EXT/INT EXT/INT = 1, external reference used; internal
reference powered down
EXT/INT = 0, internal reference used;
internally pulled down
Sleep
Sleep = 1, normal operation; internally pulled
up
Sleep = 0, powered-down mode
ORDERING INFORMATION
PART NUMBER
SPT7866SCR
TEMPERATURE RANGE
PACKAGE TYPE
0 to +70 °C
28L SSOP
SPT7866
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11/20/01