CADEKA SPT7720

SPT7720
8-BIT, 200 MSPS A/D CONVERTER
TECHNICAL DATA
MAY 9, 2001
FEATURES
APPLICATIONS
• Pin-compatible with AD9054
• High conversion rate: 200 MSPS
• Less than ±1/2 LSB DLE
• 7.16 effective number of bits (ENOB) at 70 MHz
• Single +5 V power supply
• Internal THA and voltage reference
• Low power: 430 mW
• 500 MHz full-power bandwidth
• 1V PP input range
• Single or demuxed TTL output ports
• 44-lead TQFP
• Digital sampling oscilloscopes (DSO)
• RGB video processing
• Digital communications
• High-speed instrumentation
• Projection display systems
GENERAL DESCRIPTION
The SPT7720 digital inputs interface directly to TTL,
CMOS or positive ECL (PECL) logic. The digital outputs
are user selectable in either single-channel or dual-channel modes. It is a pin-compatible, direct replacement for
the AD9054. The SPT7720 is available in a 44-lead TQFP
surface mount package over the industrial temperature
range of –40 to +85 °C.
The SPT7720 is an 8-bit, high-speed, analog-to-digital
converter implemented in a 0.5 µm BiCMOS process. It
utilizes a folding and interpolating architecture that provides both high sample rates and low power. The device
comes complete with a high bandwidth track-and-hold
amplifier and internal voltage reference.
BLOCK DIAGRAM
VREF IN
AIN
+
AIN
–
VREF OUT
Reference
THA
Quantizer
Channel A
ENCODE
ENCODE
Timing & Control
DEMUX DS
DS
Binary
Encoder
Channel B
8
8
DA7 – DA0
DB7 – DB0
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VDD ........................................................................ +6 V
Input Voltages
Analog Inputs ............................................... 0.0 to VDD
Digital Inputs ................................................ 0.0 to VDD
VREFL, VREFH ................................................ 0.0 to VDD
Temperatures
Operating Temperature .......................... –40 to +85 °C
Storage Temperature ............................ –65 to +125 °C
Note 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions in
typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, external reference, ƒS=200 MSPS, input amplitude = –1 dBFS, unless otherwise noted
PARAMETERS
DC Accuracy
Differential Linearity Error (DLE)
Integral Linearity Error (ILE)
No Missing Codes
Gain Error
Gain Tempco
Switching Performance
Encode Pulsewidth High
Encode Pulsewidth Low
Aperture Delay (tA)
Aperture Uncertainty (Jitter) & Noise
Data Sync Setup Time (tSDS)
Data Sync Hold Time (tHDS)
Data Sync Pulsewidth Time (tPWDS)
Output Valid Time (tV)
Output Prop. Delay (tPD)
Dynamic Performance
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(without harmonics)
ƒIN = 19.7 MHz
ƒIN = 19.7 MHz
ƒIN = 70.1 MHz
ƒIN = 70.1 MHz
Signal-to-Noise Ratio and Distortion
(SINAD)
ƒIN = 19.7 MHz
ƒIN = 19.7 MHz
ƒIN = 70.1 MHz
ƒIN = 70.1 MHz
2nd Harmonic Distortion
ƒIN = 19.7 MHz
ƒIN = 70.1 MHz
3rd Harmonic Distortion
ƒIN = 19.7 MHz
ƒIN = 70.1 MHz
Total Harmonic Distortion (THD)
ƒIN = 70.1 MHz
ƒIN = 70.1 MHz
Effective Number of Bits (ENOB)
ƒIN = 70.1 MHz
ƒIN = 70.1 MHz
TEST
CONDITIONS
TEST
LEVEL
+25 °C
–40 °C to +85 °C
+25 °C
–40 °C to +85 °C
I
V
I
V
VI
I
V
+25 °C
+25
+25
+25
+25
+25
+25
+25
MIN
°C
°C
°C
°C
°C
°C
°C
IV
IV
V
V
IV
IV
IV
IV
IV
SPT7720
TYP
±0.41
±1.0
±0.56
±0.9
Guaranteed
±1.06
0
2.125
2.125
0
0.5
2.0
4.4
MAX
UNITS
±0.75
±1.0
±1.0
±1.2
LSB
LSB
LSB
LSB
±1.08
%FS
ppm/°C
15
15
0.57
4.5
5.7
6.7
8.0
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
+25 °C
+25 °C
V
V
1.5
1.5
ns
ns
+25 °C
–40 °C to +85 °C
+25 °C
–40 °C to +85 °C
V
V
I
V
47
47
46.3
45.8
dB
dB
dB
dB
+25 °C
–40 °C to +85 °C
+25 °C
–40 °C to +85 °C
V
V
I
V
47
43
44.9
44.5
dB
dB
dB
dB
+25 °C
+25 °C
V
V
–59
–55.4
dBc
dBc
+25 °C
+25 °C
V
V
–58
–56.4
dBc
dBc
+25 °C
–40 to +85 °C
I
V
–50.9
–48.3
+25 °C
–40 to +85 °C
I
V
44
43
6.9
6.5
7.16
–46.0
dBc
dBc
Bits
Bits
SPT7720
2
5/9/01
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, external reference, ƒS=200 MSPS, input amplitude = –1 dBFS, unless otherwise noted
PARAMETERS
Analog Input
Input Voltage Range (differential)
Compliance Range
Input Offset Voltage
Input Offset Voltage
Input Resistance
Input Capacitance
Input Bias Current
Input Bias Current
Full Power Bandwidth
TEST
CONDITIONS
TEST
LEVEL
V
V
I
V
V
V
I
V
V
+25 °C
–40 °C to +85 °C
+25 °C
+25 °C
–40 °C to +85 °C
Reference Output Voltage
Temperature Coefficient
Differential Digital Inputs
High Level Current
Low Level Current
VI
V
–40 to +85 °C
>1.5 V differential
–40 to +85 °C
>1.5 V differential
Input Capacitance
MIN
SPT7720
TYP
MAX
±0.5
1.8
36
±4
±8
62
4
11
3.2
±16
±19
50
75
500
2.4
UNITS
V
V
mV
mV
kΩ
pF
µA
µA
MHz
2.5
110
2.6
V
ppm/°C
V
500
625
µA
V
500
625
µA
V
3
pF
Differential Inputs
Differential Signal Amplitude
High Input Voltage
Low Input Voltage
Common-Mode Input Voltage
IV
IV
IV
IV
400
1.5
0
1.5
VDD
VDD–0.4
Demux Input
High Input Voltage
Low Input Voltage
VI
VI
2.0
0
VDD
0.8
V
V
Source 800 µA
Sink 1.6 mA
VI
VI
2.4
3.9
0.8
Binary
0.4
V
V
–40 to +85 °C
VI
VI
IV
86
430
0.005
111
555
0.015
Digital Outputs
High Output Voltage
Low Output Voltage
Output Coding
Power Supply
VDD Supply Current
Power Dissipation
Power Supply Sensitivity
+25 °C
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates
the specific device testing actually performed
during production and Quality Assurance
inspection. Any blank section in the data column
indicates that the specification is not tested at
the specified condition.
mV
V
V
V
mA
mW
V/V
TEST LEVEL TEST PROCEDURE
I
II
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested at
the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and
characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
III
IV
V
VI
SPT7720
3
5/9/01
Figure 1 – Timing Diagram – Single-Channel Mode
N+4
N+3
N+2
N+1
N
N–1
N+6
N+7
N+5
tA
ENCODE
ENCODE
tPD
DA0 – DA7
OUTPUT
DATA
N–5
N–4
N–3
N–2
N–1
tV
N
N+1
N+2
Figure 2 – Timing Diagram – Dual-Channel Mode
N+4
N+3
N+2
N+1
N
N–1
N+6
N+7
N+5
tA
ENCODE
ENCODE
tHDS
DS
tSDS
tHDS tSDS
tPWDS
tPD
tV
INTERLEAVED DATA OUT
DA0 – DA7
OUTPUT
DATA
DB0 – DB7
OUTPUT
DATA
N–6
N–4
N–5
N–2
N–3
N
N–1
SPT7720
4
5/9/01
TYPICAL PERFORMANCE CHARACTERISTICS
SNR, SINAD vs Sample Rate
60
ƒIN = 70.1 MHz
50
SINAD
40
35
–50
25
–65
50
0
100
150
Sample Rate (MSPS)
–70
250
200
SNR, SINAD vs Temperature
50
100
150
Sample Rate (MSPS)
250
200
THD vs Temperature
ƒIN = 70.1 MHz
ƒS = 200 MSPS
THD (dB)
–45
SINAD
–50
35
–55
30
–60
25
–65
–25
0
25
50
Temperature (Degrees C)
–70
–40
100
75
SNR, SINAD vs VDD
60
50
25
0
50
Temperature (Degrees C)
75
100
THD vs VDD
ƒIN = 70.1 MHz
ƒS = 200 MSPS
–35
–40
SNR
45
–25
–30
ƒIN = 70.1 MHz
ƒS = 200 MSPS
55
–45
SINAD
40
–50
35
–55
30
–60
25
–65
20
50
0
–40
40
20
–40
SFDR
–35
SNR
45
SFDR
THD
–30
ƒIN = 70.1 MHz
ƒS = 200 MSPS
55
THD
–55
–60
60
SNR, SINAD (dB)
–45
30
20
SNR, SINAD (dB)
–40
SFDR, THD (dB)
SNR
45
ƒIN = 70.1 MHz
–35
THD (dB)
SNR, SINAD (dB)
55
SFDR, THD vs Sample Rate
–30
4.5 4.6
4.7
4.8 4.9
5.0
Volts
5.1
5.2
5.3
5.4 5.5
–70
4.5 4.6
4.7
4.8 4.9
5.0
Volts
5.1
5.2
5.3
5.4 5.5
SPT7720
5
5/9/01
TYPICAL PERFORMANCE CHARACTERISTICS
SNR, SINAD vs Encode Pulsewidth
60
ƒIN = 70.1 MHz
ƒS = 200 MSPS
50
SNR
45
SINAD
40
35
–40
–50
25
–65
2.0
2.5
Encode Pulsewidth (nS)
–70
3.5
3.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–40
100
150
Sample Rate (MSPS)
250
200
DLE vs VDD
2.5
3.5
3.0
ƒIN = 70.1 MHz
ƒS = 200 MSPS
–25
0
25
50
Temperature (Degrees C)
75
100
Supply Current vs Temperature
120
ƒIN = 70.1 MHz
ƒS = 200 MSPS
ƒIN = 70.1 MHz
ƒS = 200 MSPS
Supply Current (mA)
100
LSB
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
4.5 4.6
50
2.0
Encode Pulsewidth (nS)
LSB
LSB
ƒIN = 70.1 MHz
0
1.5
1.0
DLE vs Temperature
DLE vs Sample Rate
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
SFDR
–55
–60
1.5
THD
–45
30
20
1.0
ƒIN = 70.1 MHz
ƒS = 200 MSPS
–35
SFDR, THD (dB)
SNR, SINAD (dB)
55
SFDR, THD vs Encode Pulsewidth
–30
4.7
4.8 4.9
5.0
Volts
5.1
5.2
5.3
5.4 5.5
80
60
40
–40
–25
0
25
50
Temperature (Degrees C)
75
100
SPT7720
6
5/9/01
0.1 µF
0.1 µF
VREFIN
AIN
1KW
VIN
Clock In
Port A
DA0–7
SPT7720
AIN
Interfacing
Logics
DB0–7
Port B
GND (10)
0.1 µF
VDD (9)
(1 VP-P)
DS
VREFOUT
DEMUX
(+2.5 V typ)
Dual
Mode
ENCODE
Single
Mode
Data
Sync
ENCODE
+A5
DS
Figure 3 – Typical Interface Circuit
.01 µF (9x)
Notes:
1) FB = Ferrite bead. It must placed as close to the DUT as possible.
2) All 0.01 microfarad capacitors are surface mount caps. They must be
placed as close to the respective pin as possible.
FB
+
10 µF
+D5
+A5
TYPICAL INTERFACE CIRCUIT
Figure 4 – DC-Coupled Single-Ended to Differential
Conversion (power supplies and bypassing
are not shown)
Very few external components are required to achieve the
stated device performance. Figure 3 shows the typical
interface requirements when using the SPT7720 in normal circuit operation. The following sections provide descriptions of the major functions and outline performance
criteria to consider for achieving the optimal device
performance.
R3
–
VCM
Input
Voltage
(±0.5 V)
R3
R
+
(R3)/2
ADC
R
51 W
–
R2
+
R2
VIN–
ANALOG INPUT
51 W
The input of the SPT7720 can be configured in various
ways depending on whether a single-ended or differential
input is desired.
R
R
The AC-coupled input is most conveniently implemented
using a transformer with a center-tapped secondary winding. The center tap is connected to the VCM pin as shown
in figure 3. To obtain low distortion, it is important that the
selected transformer does not exhibit core saturation at
the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the
input attenuates kickback noise from the internal trackand-hold.
VIN+
15 pF
51 W
+
–
R
INPUT PROTECTION
All I/O pads are protected with an on-chip protection
circuit. This circuit provides ESD robustness and prevents
latchup under severe discharge conditions without
degrading analog transmission times.
POWER SUPPLIES AND GROUNDING
Figure 4 illustrates a solution (based on operational amplifiers) that can be used if a DC-coupled single-ended input
is desired. It is very important to select op amps with a
high open-loop gain, a bandwidth high enough so as not to
impair the performance of the ADC, low THD, and high
SNR.
The SPT7720 is operated from a single power supply in
the range of 4.75 to 5.25 volts. Normal operation is suggested to be 5.0 volts. All power supply pins should be bypassed as close to the package as possible.
SPT7720
7
5/9/01
REFERENCES
Table I – Output Data Format
To save on parts count, design time, and PC board real
estate, the SPT7720 utilizes an internal reference. No
other external components are required to implement this
feature.
Analog Input
Output Code
D7–D0
+FS
1111 1111
+FS – 1/2 LSB
1111 111Ø
+1/2 FS
ØØØØ ØØØØ
–FS + 1/2 LSB
0000 000Ø
–FS
0000 0000
Ø indicates the flickering bit between logic 0 and 1
VOLTAGE REFERENCE CIRCUIT
The SPT7720 has an on-board voltage reference circuit
(VREF). It is 2.5 volts and is capable of driving 50 µA loads
typically. The circuit is commonly used to drive the center
tap of the RF transformer in fully differential applications.
For single-ended applications, this output can be used to
provide the level shifting required for the single-to-differential converter conversion circuit.
The data output mode is set using the DEMUX input (pin
42). Table II describes the mode switching options.
Table II – Output Data Modes
Output Mode
Interleaved Dual Channel Output
Single Channel Data Output
(Bank A only 100 MSPS max)
ENCODE INPUT
The ENCODE input on the SPT7720 can be driven by either a single-ended or differential clock circuit and can
handle TTL, PECL, and CMOS signals. When operating at
high sample rates it is important to keep the pulse width of
the duty signal as close to 50% as possible. For TTL/
CMOS single-ended ENCODE inputs, the rise time of the
signal also becomes an important consideration. The
ENCODE input is 300 Ω into a bipolar differential pair.
ENCODE is internally biased to 1.5 V with a Thevenin
equivalent of 5.25 kΩ.
DEMUX
0
1
EVALUATION BOARD
The EB7720 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7720.
This board includes a clock driver and reset circuit, adjustable references and common mode, a single-ended to differential input buffer and a single-ended to differential
transformer (1:1). An application note (AN7720) describing the operation of this board, as well as information on
the testing of the SPT7720, is also available. Contact the
factory for price and availability of the EB7720.
DIGITAL INPUTS
The DS input is 35 Ω into one side of a differential pair.
There is a two-diode clamp from DS to DS in both directions. DS is biased to 1.5 V with a Thevenin equivalent of
5.25 kΩ.
The DEMUX pin is input to one side of a CMOS differential
pair. The other side is internally biased to 1.5 V and does
not connect to the outside.
DIGITAL OUTPUTS
The output circuitry of the SPT7720 has been designed to
be able to support two separate output modes. The
demuxed (double-wide) mode supports interleaved data
output. The single-channel mode is not demuxed and can
support direct output at speeds up to 100 MSPS.
The output format is straight binary (table I).
SPT7720
8
5/9/01
PACKAGE OUTLINE
44-Lead TQFP
A
B
INCHES
SYMBOL
Pin 1
Index
C
E
D
MIN
MILLIMETERS
MAX
MIN
MAX
A
0.472 Typ
12.00 Typ
B
0.394 Typ
10.00 Typ
C
0.394 Typ
10.00 Typ
D
0.472 Typ
12.00 Typ
E
0.031 Typ
0.80 Typ
F
0.012
0.018
0.300
0.45
G
0.053
0.057
1.35
1.45
H
0.002
0.006
0.05
0.15
I
0.018
0.030
0.450
0.750
J
0.039 Typ
1.00 Typ
K
0-7°
0-7°
F
G
H
K
I
J
SPT7720
9
5/9/01
PIN FUNCTIONS
PIN ASSIGNMENTS
Pin Name Description
GND
VREF IN
VDD
GND
AIN
AIN
GND
VDD
DEMUX
DS
DS
AIN, AIN
Differential Input Pins
ENCODE
Differential Clock Input
ENCODE
34
35
36
37
38
39
40
41
42
ENCODE
43
1
44
ENCODE
VDD
Power Supply
GND
Ground
DA0–DA7
Digital Outputs, Channel A
VDD
DB0–DB7
Digital Outputs, Channel B
GND
VREF OUT Reference Output Voltage
28
VDD
GND
VREF IN
Reference Input Voltage, High
27
26
DB7 (MSB)
DEMUX
Format Select: LOW = Dual-Channel Mode,
HIGH = Single-Channel Mode
DS, DS
Data Sync and Data Sync Complement –
Aligns Output Channels in Dual-Channel Mode
33
VREF OUT
2
32
GND
VDD
3
31
VDD
GND
4
30
VDD
5
29
GND
6
DA7 (MSB)
7
SPT7720
TOP VIEW
44L TQFP
21
22
DB0 (LSB)
DB1
DB2
DB3
VDD
20
GND
19
18
DB4
GND
23
17
11
16
DA3
DA0 (LSB)
DB5
VDD
24
15
10
DA1
DB6
DA4
14
25
DA2
9
13
8
12
DA6
DA5
ORDERING INFORMATION
PART NUMBER
SPT7720SIT
TEMPERATURE RANGE
PACKAGE
–40 to +85 °C
44L TQFP
SPT7720
10
5/9/01