8 SLVS612 − APRIL 2006 FEATURES D Operating Input Voltage 10 V to 40 V D Output Voltage Tracks External Reference D Programmable Fixed-Frequency Up to D D D D D D CONTENTS Device Ratings Electrical Characteristics Terminal Information Application Information Design Example Additional References 100 kHz to 1 MHz Voltage Mode Controller Internal Gate Drive Outputs for High-Side and Synchronous N-Channel MOSFETs Externally Synchronizable Programmable Short-Circuit Protection Thermal Shutdown 16-Pin PowerPADt Package (θJC = 2°C/W) Programmable Closed-Loop Soft-Start 2 3 5 7 22 29 DESCRIPTION The TPS40056 is part of a family of high-voltage, wide input, synchronous, step-down converters. The TPS40056 offers design flexibility with a variety of user programmable functions, including soft-start, operating frequency, high-side current limit, and loop compensation. The TPS40056 is also synchronizable to an external supply. It incorporates MOSFET gate drivers for external N-channel high-side and synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction. The externally programmable short circuit protection provides pulse-by-pulse current limit, as well as hiccup mode operation utilizing an internal fault counter for longer duration overloads. APPLICATIONS D DDR Tracking Regulators D Power Modules D Networking Equipment D Industrial Servers SIMPLIFIED APPLICATION DIAGRAM + VIN TPS40056PWP 1 SYNC 2 RT 3 BP5 4 EA_REF HDRV 13 5 SGND 6 SS BP10 11 7 VFB LDRV 10 8 COMP PGND PAD − VTRKIN ILIM 16 VIN 15 BOOST 14 SW 12 + VTT 9 − UDG−03080 !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ Copyright 2006, Texas Instruments Incorporated www.ti.com 1 SLVS612 − APRIL 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA −40°C to 85°C PACKAGE PART NUMBER Plastic HTSSOP(PWP)(1) TPS40056PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40056PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(2) TPS40056 VIN Input voltage range, VIN UNIT 45 VFB, SS, SYNC, EA_REF −0.3 to 6 SW −0.3 to 45 SW, transient < 50 ns Output voltage range, VO COMP, RT, SS Output current, IOUT RT V −2.5 −0.3 to 6 µA 200 Operating junction temperature range, TJ −40 to 125 Storage temperature, Tstg −55 to 150 °C C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 (2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN Input voltage, VI 10 Operating free-air temperature, TA −40 PWP PACKAGE(3)(4) (TOP VIEW) SYNC RT BP5 EA_REF SGND SS/SD VFB COMP 1 2 3 4 5 6 7 8 THERMAL PAD 16 15 14 13 12 11 10 9 ILIM VIN BOOST HDRV SW BP10 LDRV PGND (3) For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002. (4) PowerPADt heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins. 2 www.ti.com NOM MAX 40 85 UNIT V °C SLVS612 − APRIL 2006 ELECTRICAL CHARACTERISTICS TA = −40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, fSW = 500 kHz, VEA_REF = 1.25 V, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range, VIN OPERATING CURRENT IDD Quiescent current 10 Output drivers not switching, VFB = 1.3 V 40 V 1.5 3.0 mA BP5 VBP5 Ouput voltage OSCILLATOR/RAMP GENERATOR ILOAD = 1 mA 4.5 5.0 5.5 V fOSC VRAMP Accuracy 9 V ≤ VIN ≤ 40 V 520 580 640 kHz PWM ramp voltage(1) VPEAK−VVAL VIH VIL High-level input voltage, SYNC ISYNC Input current, SYNC 2.0 2 5 Low-level input voltage, SYNC Pulse width, SYNC VRT 0.8 V 5 10 µA 2.50 2.58 50 RT voltage 2.38 Maximum duty cycle VFB = 0 V, fSW ≤ 600 kHz VFB = 0 V, 600 kHz ≤ fSW ≤ 1 MHz Minumum duty cycle VFB ≥ EA_REF + 0.05 V V ns V 90% 85% 0% SOFT START ISS VSS Soft-start source current 1.65 tDSCH tSS Discharge time CSS = 220 pF Soft-start time CSS = 220 pF, Soft-start clamp voltage 2.35 3.05 3.7 0 V ≤ VSS ≤ 1.6 V µA V 1.6 2.2 2.8 100 155 205 9.0 9.6 10.3 µss BP10 VBP10 Ouput voltage ERROR AMPLIFIER VEA_REF Error amplifier reference input voltage(1)(2) 10 V ≤ VIN ≤ 40 V 0.2 2.5 Input offset voltage 0.5 V ≤ VFB ≤ 2.25 V −6 6 V V mV Input offset voltage 0.2 V ≤ VFB ≤ 0.5 V −10 0 GBW Gain bandwidth 0.2 V ≤ VFB ≤ 0.5 V 1.5 3.5 MHz GBW Gain bandwidth 0.5 V ≤ VFB ≤ 2.25 V 2.5 5.0 MHz AVOL IOH Open loop gain 60 80 dB High-level output source current 1.5 4.0 IOL VOH Low-level output sink current 2.0 4.0 VOL IBIAS Low-level output voltage ISOURCE = 500 µA ISINK = 500 µA Input bias current VFB = 1.2 V (1) (2) High-level output voltage 3.2 10 MV mA 3.5 0.20 0.35 100 200 V nA Ensured by design. Not production tested. Common mode range extends to ground, but not tested below 200 mV. www.ti.com 3 SLVS612 − APRIL 2006 ELECTRICAL CHARACTERISTICS TA = −40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, fSW = 500 kHz, VEA_REF = 1.25 V all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 10 12 UNIT CURRENT LIMIT ISINK Current limit sink current Propagation delay to output tON tOFF VOS 8 VILIM = 11.7 V, VSW = (VILIM − 0.5 V) VILIM = 11.7 V, VSW = (VILIM − 2 V) Switch leading-edge blanking pulse time(1) 250 ns 100 Off time during a fault Offset voltage SW vs. ILIM µA 300 7 −70 cycles VILIM = 11.6 V, VILIM = 11.6 V, TA = 25°C 0°C ≤ TA ≤ 85°C −100 −40 −125 −30 VILIM = 11.6 V, −40°C ≤ TA ≤ 85°C −125 −15 mV OUTPUT DRIVER tLRISE tLFALL Low-side driver rise time tHRISE tHFALL High-side driver rise time Low-side driver fall time High-side driver fall time CLOAD = 2200 pF CLOAD = 2200 pF, (HDRV − SW) VOH High-level ouput voltage, HDRV IHDRV = −0.1 A (HDRV − SW) VOL Low-level ouput voltage, HDRV IHDRV = 0.1 A (HDRV − SW) VOH High-level ouput voltage, LDRV ILDRV = −0.1 A VOL Low-level ouput voltage, LDRV ILDRV = 0.1 A BOOST −1.5 V 48 96 24 48 48 96 36 72 ns BOOST −1.0 V 0.75 BP10 −1.4 V V BP10 − 1.0 V 0.5 Minimum controllable pulse width(1) 100 150 ns 90 125 165 165 210 260 19 20 21 V 25 µA SS/SD SHUTDOWN VSD VEN Shutdown threshold voltage Outputs off Device active threshold voltage mV BOOST REGULATOR VBOOST Output voltage SW NODE VIN = 12.0 V ILEAK Leakage current(1) THERMAL SHUTDOWN Shutdown temperature(1) Hysteresis(1) TSD 165 °C 20 UVLO Input voltage UVLO threshold 8.20 Input voltage UVLO hysteresis (1) 4 8.75 1.0 Ensured by design. Not production tested. www.ti.com 9.25 V SLVS612 − APRIL 2006 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION BOOST 14 O Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input voltage. A 0.1-µF ceramic capacitor should be connected from this pin to the SW pin. BP5 3 O 5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with an external dc load of 1 mA or less. BP10 11 O 10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF ceramic capacitor. This pin may be used with an external dc load of 1 mA or less. COMP 8 O Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve large signal transient response. HDRV 13 O Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW (MOSFET off). ILIM 16 I Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage drop (VIN −SW) across the high side MOSFET during conduction. EA_REF 4 I Non-inverting input to the error amplifier and used as the reference for the feedback loop. LDRV 10 O Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET off). PGND 9 − Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the lower MOSFET(s). RT 2 I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency. SGND 5 − Signal ground reference for the device. SS/SD 6 I Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS pin reaches the internal reference voltage , EA_REF V. Pulling this pin low disables the controller. SW 12 I This pin is connected to the switched node of the converter and used for overcurrent sensing. SYNC 1 I Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency. If synchronization is not used, connect this pin to SGND. VFB 7 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the EA_REF reference voltage. VIN 15 I Supply voltage for the device. www.ti.com 5 SLVS612 − APRIL 2006 FUNCTIONAL BLOCK DIAGRAM ILIM 16 BP10 VIN 15 RT 2 SYNC 1 RAMP 10 V Regulator BP5 7 Reference Voltages COMP 8 0.7 VREF 7 1.5 VREF 7 7 CL 3−Bit Up/Down Fault Counter N−channel Driver Restart Fault 12 SW + + + 0.7 V 7 Fault 7 SS/SD 6 7 7 13 HDRV 7 3.5 VREF 7 BP5 7 CLK 7 7 EA_REF 4 VFB 7 BP10 14 BOOST + Clock Oscillator 1.5 VREF 7 BP5 3 11 S BP10 7 Q CL R Q + 0.7 VREF N−channel Driver CLK 7 10 LDRV 9 PGND Restart 5 SGND 6 www.ti.com UDG−03081 SLVS612 − APRIL 2006 APPLICATION INFORMATION The TPS40056 allows the user to optimize the PWM controller to the specific application. The TPS40056 is the controller of choice for synchronous buck designs, the output of which is required to track another voltage. It has two quadrant operation and can source or sink output current, providing the best transient response. SW NODE RESISTOR AND DIODE The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output current which flows during this dead time. This negative voltage could affect the operation of the controller, especially at low input voltages. Therefore, a resistor ( 3.3 Ω to 4.7 Ω) and Schottky diode must be placed between the lower MOSFET drain and pin 12, SW, of the controller as shown in Figure 10. The Schottky diode must have a voltage rating to accommodate the input voltage and ringing on the SW node of the converter. A 30-V Schottky such as a BAT54 or a 40-V Schottky such as a Zetex ZHCS400 or Vishay SD103AWS are adequate. These components are shown in Figure 10 as RSW and D2. SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS40056 has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by a single resistor (RT) to ground. The clock frequency is related to RT, in kΩ by Equation (1). RT + ǒ f SW 1 17.82 10 *6 Ǔ * 23 kW (1) UVLO OPERATION The TPS40056 uses fixed UVLO protection. The fixed UVLO monitors the input voltage. The UVLO circuit holds the soft-start low until the input voltage has exceeded the undervoltage threshold. TRACKING CONFIGURATION (VOUT TRACKING VIN) Setting the output, VOUT to track another voltage, VTRKIN, is simply a matter of selecting the proper voltage divider(s) R4,R5,R1 and R6 as shown in Figure 1. The voltage on the EA_REF input should be in the range of 0.2 V to 2.5 V. If the output voltage is less than 2.5 V, resistor R6 can be omitted. For example in the DDR case, if the voltage VTRKIN ramps up to 2.5 V and it is desired to have VOUT to track it and come up to 1.25 V, set R4=R5 and omit R6. In general, the output voltage, VOUT, in terms of VTRKIN and the two voltage dividers is shown in Equation (2). V OUT + V TRKIN ) R1Ǔ V ǒR4 R5 Ǔ ǒR6 R6 ) R5 www.ti.com (2) 7 SLVS612 − APRIL 2006 TPS40056PWP R4 4 EA_REF VTRKIN R5 5 SGND HDRV 13 + VOUT SW 12 R3 6 SS BP10 11 7 VFB LDRV 10 8 COMP PGND 9 R1 − R6 UDG−06020 Figure 1. Tracking Configuration, VOUT Tracks VTRKIN BP10 AND BP5 vs INPUT VOLTAGE SWITCHING FREQUENCY vs TIMING RESISTANCE 600 10 9 BP10 8 VOUT − Output Voltage − V RT − Timing Resistance − kΩ 500 400 300 200 7 BP5 6 5 4 3 2 100 1 0 0 0 200 400 600 800 1000 fSW − Switching Frequency − kHz 4 6 8 10 VIN − Input Voltage − V Figure 3 Figure 2 8 2 www.ti.com 12 14 SLVS612 − APRIL 2006 APPLICATION INFORMATION BP5 AND BP10 INTERNAL VOLTAGE REGULATORS Start-up characteristics of the BP5 and BP10 regulators are shown in Figure 2. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs. SELECTING THE INDUCTOR VALUE The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good compromise is to select the inductance value such that the converter doesn’t enter discontinuous mode until the load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in equation (3). L+ ǒVIN * VOǓ DI V IN VO f SW (Henries) (3) where:. D VO is the output voltage D ∆I is the peak-to-peak inductor current CALCULATING THE OUTPUT CAPACITANCE The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any output voltage deviation requirement during a load transient. The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output ripple is described in equation (4). DV + DI ƪ ESR ) ǒ 8 1 CO f SW Ǔƫ V P*P (4) The output ripple voltage is typically between 90% and 95% due to the ESR component. The output capacitance requirement typically increases in the presence of a load transient requirement. During a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the inductor. www.ti.com 9 SLVS612 − APRIL 2006 APPLICATION INFORMATION Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in equation (5). EL + 1 2 I 2 (Joules) L (5) where: I2 + ƪ ǒI OH Ǔ 2 * ǒI OLǓ ƫ ǒ(Amperes)2Ǔ 2 (6) where: D IOH is the output current under heavy load conditions D IOL is the output current under light load conditions Energy in the capacitor is described in equation (7). EC + 1 2 V 2 (Joules) C (7) where: V2 + ƪ ǒV Ǔ * ǒ V Ǔ ƫ 2 2 f ǒVolts2Ǔ i (8) where: D Vf is the final peak capacitor voltage D Vi is the initial capacitor voltage Substituting equation (6) into equation (5), then substituting equation (8) into equation (7), then setting equation (7) equal to equation (5), and then solving for CO yields the capacitance described in equation (9). L CO + ƪ ǒI Ǔ * ǒ I Ǔ ƫ ƪ ǒV Ǔ * ǒV Ǔ ƫ 2 OL 2 f 10 2 OH (Farads) 2 i (9) www.ti.com SLVS612 − APRIL 2006 APPLICATION INFORMATION PROGRAMMING SOFT START TPS40056 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on CSS is fed into a separate non-inverting input to the error amplifier (in addition to FB and EA_REF). The loop is closed on the lower of the CSS voltage or the the external reference voltage EA_REF. Once the CSS voltage rises above the external reference voltage, regulation is based on the external reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-CO time constant as described in equation (10). t START w 2p ǸL C O (seconds) (10) There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the higher the input current required during start-up. This relationship is describe in more detail in the section titled, Programming the Current Limit which follows. The soft-start capacitance, CSS, is described in equation (11). For applications in which the VIN supply ramps up slowly, (typically between 50 ms and 100 ms) it may be necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO tripping. The soft-start time should be longer than the time that the VIN supply transitions between 8 V and 9 V. C SS + 2.3 mA 0.7 V t START (Farads) (11) PROGRAMMING CURRENT LIMIT The TPS40056 uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 3 for typical overcurrent protection waveforms. The minimum current limit setpoint (ILIM) depends on tSTART, CO, VO, and the load current at turn-on (IL). I LIM + ƪ ǒC O V OǓ t START ƫ ) I L (Amperes) (12) www.ti.com 11 SLVS612 − APRIL 2006 APPLICATION INFORMATION The current limit programming resistor (RILIM) is calculated using equation (13). Care must be taken in choosing the values used for VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level, the minimum value of ISINK and the maximum value of VOS must be used. R ILIM + I OC R DS(on)[max] I SINK ) V OS I SINK (W) (13) where: D ISINK is the current into the ILIM pin and is 8.6 µA, minimum D IOC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current D VOS is the overcurrent comparator offset and is 30 mV, maximum HDRV CLOCK tBLANKING VILIM VVIN−VSW SS 7 CURRENT LIMIT TRIPS (HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP) 7 SOFT-START CYCLES UDG−02136 Figure 4. Typical Current Limit Protection Waveforms SYNCHRONIZING TO AN EXTERNAL SUPPLY The TPS40056 can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS40056 to freely run at the frequency programmed by RT. 12 www.ti.com SLVS612 − APRIL 2006 APPLICATION INFORMATION LOOP COMPENSATION Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40056 includes no voltage feedforward control, the gain of the PWM modulator must be included. The modulator gain is described in Figure 5. A MOD + V IN VS A MOD(dB) + 20 or log ǒ Ǔ V IN VS (14) Duty dycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage, D+ VO V + C V IN VS or VO V + IN VC VS (15) Calculate the Poles and Zeros For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole is located at the frequency calculated in equation (16). f LC + 1 2p ǸL (Hertz) CO (16) There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at the frequency calculated in equation (17). fZ + 2p 1 ESR CO (Hertz) (17) Calculate the value of RBIAS to set the output voltage, VOUT. R BIAS + V EA_REF R1 V OUT * V EA_REF W (18) The maximum crossover frequency (0 dB loop gain) is calculated in equation (19). fC + f SW (Hertz) 4 (19) Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this frequency, the control to output gain has a –2 slope (−40 dB/decade), while the Type III topology has a +1 slope (20 dB/decade), resulting in an overall closed loop –1 slope (−20 dB/decade). Figure 5 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated. www.ti.com 13 SLVS612 − APRIL 2006 APPLICATION INFORMATION MODULATOR GAIN vs SWITCHING FREQUENCY PWM MODULATOR RELATIONSHIPS ESR Zero, + 1 Modulator Gain − dB AMOD = VIN / VS VS VC Resultant, − 1 D = VC / VS LC Filter, − 2 100 1k 10 k 100 k fSW − Switching Frequency − Hz Figure 6 Figure 5 A Type III topology, shown in Figure 7, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 8. The two zeros are used to compensate the L-CO double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier’s gain roll-off used to roll-off the overall gain at higher frequencies. C2 (optional) C1 R3 −1 R2 +1 0 dB C3 VFB R1 −1 7 8 VOUT RBIAS COMP GAIN −90° + 180° PHASE −270° EA_REF UDG−03099 Figure 7. Type III Compensation Configuration 14 Figure 8. Type III Compensation Gain and Phase www.ti.com SLVS612 − APRIL 2006 APPLICATION INFORMATION The poles and zeros for a type III network are described in equations (20). f Z1 + 2p 1 R2 C1 f P1 + 2p 1 R2 C2 (Hertz) f Z2 + 2p 1 R1 C3 (Hertz) f P2 + 2p 1 R3 C3 (Hertz) (20) (Hertz) The value of R1 is somewhat arbitraty, but influences other component values. A value between 50 kΩ and 100 kΩ usually yields reasonable values. The unity gain frequency is described in equation (21) fC + 1 2p R1 C2 G (Hertz) (21) where G is the reciprocal of the modulator gain at fC. The modulator gain as a function of frequency at fC, is described in equation (22). AMOD(f) + AMOD ǒ Ǔ f LC fC 2 and G+ 1 AMOD(f) (22) Minimum Load Resistance Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current which must be considered when sizing R2. Too small a value does not allow the output to swing over its full range. R2 (MIN) + V C (max) I SOURCE (min) + 3.45 V + 1725 W 2 mA (23) CALCULATING THE BOOST AN BP10 BYPASS CAPACITOR The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance is described in equation (24). C BOOST + Qg (Farads) DV (24) The 10-V reference pin, BP10V needs to provide energy for both the synchronous MOSFET and the high-side MOSFET via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in equation (25). C BP10 + ǒQgHS ) QgSRǓ DV (Farads) (25) www.ti.com 15 SLVS612 − APRIL 2006 APPLICATION INFORMATION dv/dt Induced Turn−On MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through currents. Therefore, the SR MOSFET should be chosen so that the CGD capacitance is smaller than the CGS capacitance. High Side MOSFET Power Dissipation The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The high-side MOSFET conduction losses are defined by equation (26). P COND + ǒI RMSǓ 2 R DS(on) ǒ1 ) TCR ƪTJ * 25ƫǓ (Watts) (26) where: D TCR is the temperature coefficient of the MOSFET RDS(on) The TCR varies depending on MOSFET technology and manufacturer but is typically ranges between .0035 ppm/_C and .010 ppm/_C. The IRMS current for the high side MOSFET is described in equation (27). I RMS + I O Ǹd ǒAmperesRMSǓ (27) The switching losses for the high-side MOSFET are descibed in equation (28). P SW(fsw) + ǒV IN I OUT t SWǓ f SW (Watts) where: D IO is the DC output current D tSW is the switching rise time, typically < 20 ns D fSW is the switching frequency Typical switching waveforms are shown in Figure 8. 16 www.ti.com (28) SLVS612 − APRIL 2006 APPLICATION INFORMATION ID2 IO ID1 d } ∆I 1−d BODY DIODE CONDUCTION BODY DIODE CONDUCTION SW 0 ANTI−CROSS CONDUCTION SYNCHRONOUS RECTIFIER ON HIGH SIDE ON UDG−02139 Figure 9. Inductor Current and SW Node Waveforms The maximum allowable power dissipation in the MOSFET is determined by equation (29). PT + ǒT J * T AǓ q JA (Watts) (29) where: P T + P COND ) P SW(fsw) (Watts) (30) and θJA is the package thermal impedance. Synchronous Rectifier MOSFET Power Dissipation The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be found using equation (32) and the RMS current through the synchronous rectifier MOSFET is described in equation (31). I RMS + I O Ǹ1 * d ǒAmperesRMSǓ (31) The body-diode conduction losses are due to forward conduction of the body diode during the anti−cross conduction delay time. The body diode conduction losses are described by equation (32). P DC + 2 IO VF t DELAY f SW (Watts) (32) where: D VF is the body diode forward voltage D tDELAY is the total delay time just before the SW node rises. www.ti.com 17 SLVS612 − APRIL 2006 APPLICATION INFORMATION The 2-multiplier is used because the body-diode conducts twice each cycle (once on the rising edge and once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a reverse blocking state. The reverse recovery losses are described in equation (33). P RR + 0.5 Q RR V IN f SW (Watts) (33) where: D QRR is the reverse recovery charge of the body diode The total synchronous rectifier MOSFET power dissipation is described in equation (34). P SR + P DC ) P RR ) P COND (Watts) (34) TPS40056 POWER DISSIPATION The power dissipation in the TPS40056 is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance, refer to [2] can be calculated from equation (35). PD + Qg V DR f SW (Watts) (35) And the total power dissipation in the TPS40056, assuming the same MOSFET is selected for both the high-side and synchronous rectifier is described in equation (36). PT + ǒ 2 PD ) IQ V DR Ǔ V IN (Watts) (36) or P T + ǒ2 f SW ) I QǓ Qg V IN (Watts) (37) where: D IQ is the quiescent operating current (neglecting drivers) The maximum power capability of the device’s PowerPad package is dependent on the layout as well as air flow. The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow. θJA = 36.51°C/W The maximum allowable package power dissipation is related to ambient temperature by equation (29). Substituting equation (29) into equation (37) and solving for fSW yields the maximum operating frequency for the TPS4005x. The result is described in equation (38). ǒƪ ƫ ǒT J*T AǓ * IQ ǒq JA V DDǓ f SW + 18 ǒ2 Q gǓ Ǔ (Hz) (38) www.ti.com SLVS612 − APRIL 2006 LAYOUT CONSIDERATIONS The PowerPADt package The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the area is 5 mm x 3.4 mm [3]. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally Enhanced Package[3] and the mechanical illustration at the end of this document for more information on the PowerPAD package. X: Minimum PowerPAD = 1.8 mm Y: Minimum PowerPAD = 1.4 mm Thermal Pad 4,50 mm 6,60 mm 4,30 mm 6,20 mm X 1 Y 10 Figure 10. PowerPAD Dimensions MOSFET Packaging MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on proper layout and thermal management. The θJA specified in the MOSFET data sheet refers to a given copper area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch of 2-ounce copper on a G−10/FR−4 board. Lower thermal impedances can be achieved at the expense of board area. Please refer to the selected MOSFET’s data sheet for more information regarding proper mounting. www.ti.com 19 SLVS612 − APRIL 2006 LAYOUT CONSIDERATIONS Grounding and Circuit Layout Considerations The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor. Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The SGND plane should only make a single point connection to the PGND plane. Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). The SW pin Schottky diode, D2 in Figure 10, should be placed close to the TPS40056 with short, wide traces to pins 9 and 12. 20 www.ti.com SLVS612 − APRIL 2006 DESIGN EXAMPLE D D D D D D D Input Voltage: 10 Vdc to 14.4 Vdc Output voltage: 1.25 V ±1% (1.2375 ≤ VO ≤1.2625) Output current: 8 A (maximum, steady state), 10 A (surge, 10ms duration, 10% duty cycle maximum) Output ripple: 33 mVP-P at 8 A Output load response: 0.1 V => 10% to 90% step load change, from 1 A to 7 A Operating temperature: −40°C to 85°C fSW=170 kHz 1. Calculate maximum and minimum duty cycles d MIN + V O(min) + 1.2375 + 0.086 14.4 V IN(max) d MAX + V O(max) V IN(min) + 1.2625 + 0.126 10 (39) 2. Select switching frequency The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater than 400 ns (see Electrical Characteristics table). Therefore V O(min) V IN(max) + t ON T SW or (40) ȡǒ VO(min) Ǔȣ ȧ VIN(max) ȧ 1 +f + ȧ TON ȧ SW T SW ȧ ȧ Ȣ Ȥ (41) Using 450 ns to provide margin, f SW + 0.086 + 191 kHz 450 ns (42) Since the oscillator can vary by 10%, decrease fSW, by 10% f SW + 0.9 191 kHz + 172 kHz and therefore choose a frequency of 170 kHz. 3. Select ∆I In this case ∆I is chosen so that the converter enters discontinuous mode at 20% of nominal load. DI + I O 2 0.2 + 8 2 0.2 + 3.2 A www.ti.com (43) 21 SLVS612 − APRIL 2006 DESIGN EXAMPLE 4. Calculate the power losses Power losses in the high-side MOSFET (Si7860DP) at 14.4-VIN where switching losses dominate can be calculated from equation (27). I RMS + I O Ǹd + 8 Ǹ0.086 + 2.35 A (44) substituting (27) into (26) yields P COND + 2.35 2 (1 ) 0.007 0.008 (150 * 25)) + 0.083 W (45) and from equation (28), the switching losses can be determined. P SW(fsw) + ǒV IN t SWǓ IO f SW + 14.4 V 8A 20 ns 170 kHz + 0.39 W (46) The MOSFET junction temperature can be found by substituting equation (30) into equation (29) T J + ǒP COND ) P SWǓ q JA ) T A + (0.083 ) 0.39) 40 ) 85 + 90 C O (47) 5. Calculate synchronous rectifier losses The synchronous rectifier MOSFET has two loss components, conduction, and diode reverse recovery losses. The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead time associated with the anti-cross conduction delay. The IRMS current through the synchronous rectifier from (31) I RMS + I O Ǹ1 * d + 8 Ǹ1 * 0.126 + 7.48 A RMS (48) The synchronous MOSFET conduction loss from (26) is: P COND + 7.48 2 (1 ) 0.007(150 * 25)) + 0.83 W 0.008 (49) The body diode conduction loss from (32) is: P DC + 2 IO V FD t DELAY f SW + 2 8.0 A 0.8 V 100 ns 170 kHz + 0.218 W (50) The body diode reverse recovery loss from (33) is: P RR + 0.5 Q RR V IN f SW + 0.5 30 nC 14.4 V 170 kHz + 0.037 W (51) The total power dissipated in the synchronous rectifier MOSFET from (34) is: P SR + P RR ) P COND ) P DC + 0.037 ) 0.83 ) 0.218 + 1.085 W (52) The junction temperature of the synchronous rectifier at 85°C is: T J + P SR q JA ) T A + (1.085) 40 ) 85 + 128 oC (53) In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode conduction and reverse recovery periods. 22 www.ti.com SLVS612 − APRIL 2006 DESIGN EXAMPLE 6. Calculate the inductor value The inductor value is calculated from equation (3). L+ (14.4 * 1.25 V) 1.25 V + 2.1 mH 14.4 V 3.2 A 170 kHz (54) A 2.9-µH Coev DXM1306−2R9 or 2.6-µH Panasonic ETQ−P6F2R9LFA can be used. 7. Setting the switching frequency The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be found from equation (1), with fSW in kHz. RT + ǒ f SW 1 17.82 10 *6 Ǔ * 23 kW + 307 kW N use 309 kW (55) 8. Calculating the output capacitance (CO) In this example the output capacitance is determined by the load response requirement of ∆V = 0.1 V for a 1 A to 7 A step load. CO can be calculated using (9) CO + ǒ(8 A)2 * (1 A)2Ǔ + 761 mF ǒ(1.25)2 * (1.15)2Ǔ 2.9 m (56) Using (4) we can calculate the ESR required to meet the output ripple requirements. ǒ 33 mV + 3.2 A ESR ) 8 1 761 mF Ǔ 170 kHz ESR + 10.3 mW * 1.0 mW + 9.3 mW (57) (58) For this design example two (2) Panasonic SP EEFUEOD471R capacitors, (2.0 V, 470 µF, 12 mΩ) are used. 9. Calculate the soft-start capacitor (CSS) This design requires a soft−start time (tSTART) of 1 ms. CSS can be calculated on (11) C SS + 2.3 mA 0.7 V 1 ms + 3.29 nF + 3300 pF www.ti.com (59) 23 SLVS612 − APRIL 2006 DESIGN EXAMPLE 10. Calculate the current limit resistor (RILIM) The current limit set point depends on tSTART, VO,CO and ILOAD at start-up as shown in equation (12). For this design, I LIM u 940 mF 1.25 V ) 8.0 A + 9.2 A 1 ms (60) For this design, set ILIM for 11.0 ADC minimum. From equation (13), with IOC equal to the DC output surge current plus one-half the ripple current of 3.2 A and RDS(on) is increased 30% (1.3 * 0.008) to allow for MOSFET heating. (0.03) R ILIM + 12.6 A 0.0104W ) + 15.24 kW * 3.5 kW + 11.74 kW ^ 11.8 W 8.6 mA 8.6 mA (61) 11. Calculate loop compensation values Calculate the DC modulator gain (AMOD) from equation (14) A MOD + 12 + 6.0 2 A MOD(dB) + 20 log (6) + 15.6 dB (62) Calculate the output filter L-CO poles and CO ESR zeros from (16) and (17) f LC + 1 2p ǸL CO 1 + 2p Ǹ2.9 mH 940 mF + 3.05 kHz (63) and fZ + 2p 1 ESR CO + 2p 1 0.006 940 mF + 28.2 kHz (64) Select the close-loop 0 dB crossover frequency, fC. For this example fC = 20 kHz. Select the double zero location for the Type III compensation network at the output filter double pole at 3.05 kHz. Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 28.2 kHz. The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain AMOD at the crossover frequency from equation (22). A MOD(f) + A MOD ǒ Ǔ f LC fC 2 +6 kHzǓ ǒ3.05 20 kHz 2 + 0.14 (65) And also from equation (22). G+ 1 + 1 + 7.14 0.14 A MOD(f) (66) Choose R1 = 100 kΩ 24 www.ti.com SLVS612 − APRIL 2006 DESIGN EXAMPLE The poles and zeros for a type III network are described in equations (20) and (21). f Z2 + 2p 1 R1 C3 f P2 + 2p 1 R3 C3 fC + 2p R1 C2 f P1 + 2p 1 R2 C2 f Z1 + 2p 1 R2 C1 N C3 + 2p 1 100 kW 3.05 kHz + 522 pF, choose 560 pF N R3 + 2p 1 560 pF 28.2 kHz + 10.08 kW, choose 10 kW 1 G N C2 + 1 2p 100 kW N R2 + 2p 1 10 pF N C1 + 2p 1 562 kW 7.14 28.2 kHz 20 kHz + 11.1 pF, choose 10 pF + 564 kW, choose 562 kW 3.05 kHz + 92.9 pF, choose 100 pF (67) (68) (69) (70) (71) Calculate the value of RBIAS from equation (17) with R1 = 100 kΩ. Since the output of 1.25-V is within the EA_REF input specification of 0.5 V to 1.5 V, an RBIAS resistor is not required. CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount of droop allowed on the bypass cap. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage droop on the BOOST pin from equation (24) is: C BOOST + Qg + 18 nC + 36 nF DV 0.5 V (72) and the BP10V capacitance from (25) is C BP(10 V) + Q gHS ) Q gSR DV + 2 Qg + 36 nC + 72 nF DV 0.5 V (73) For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1.0-µF capacitor is used for the BP10V bypass. Figure 10 shows component selection for the 10-V to 14.4-V to 1.25-V at 8 A dc-to-dc converter specified in the design example. REFERENCES 1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM−1400 Topic 2. 2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief: TI Literature No. SLMA002 www.ti.com 25 26 + www.ti.com C1 10 pF 562 kΩ R2 C2 3300 pF PWP PGND COMP 8 9 LDRV 10 BP10 11 VFB SS 6 SW 12 HDRV 13 BOOST 14 VIN 15 ILIM 16 7 SGND 5 EA_REF BP5 3 4 RT SYNC TPS40056PWP 2 1 330 µF CSS 1.0 µF 165 kΩ RT 330 µF 100 pF R5 10 kΩ R4 10 kΩ VTRKIN − VIN D2 0.1 µF 1.0 µF 50 V 100 pF Si7860DP 3.3 Ω RSW Si7860DP 1.0 µF 11.8 kΩ D1 2.9 µH 22 µF 50 V 560 pF C3 R3 10 kΩ 22 µF 50 V R1 100 kΩ 470 µF 470 µF VTT − + SLVS612 − APRIL 2006 UDG−03100 Figure 11. 12-V to 1.25-V at 8-A DC-to-DC Converter (DDR) Design Example SLVS612 − APRIL 2006 Center Power Pad Solder Stencil Stencil Thicknes s X 0.1m m 2.5 0.127m m 2.31 0.152m m 2.15 0.178m m 2.05 www.ti.com Opening Y 2.65 2.46 2.3 2.15 27 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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