Evaluation board available. NX2309 SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER PRELIMINARY DATA SHEET Pb Free Product DESCRIPTION The NX2309 controller IC is a combination synchronous Buck and LDO controller IC designed to convert single 12V supply to low cost dual on board supply applications. The synchronous controller is used for high current high efficiency step down DC to DC converter applications while the LDO controller in conjunction with an external low cost N ch MOSFET can be used as a very low drop out regulator in applications such as converting 3.3V to 2.5V output. Internal UVLO keeps both regulators off until the supply voltage exceeds 9V where independent internal digital soft starts get initiated to ramp up both outputs.The switching section has fixed hiccup current limit by sensing the Rdson of synchronous MOSFET. The LDO controller has Feedback Under Voltage Lock Out as a short circuit protection.Other features includes: 12V gate drive capability , Adaptive dead band control. FEATURES n 12V PWM controller plus LDO controller n Fixed hiccup current limit by sensing Rdson of MOSFET n 12V high side and low side driver n Fixed internal 300kHz for switching controller n Dual Independent Digital Soft Start Function n Adaptive Deadband Control n Shut Down switching via pulling down COMP pin n Pb-free and RoHS compliant APPLICATIONS n n n n PCI Graphic Card on board converters Mother board On board DC to DC applications On board Single Supply 12V DC to DC such as 12V to 3.3V, 2.5V or 1.8V Set Top Box and LCD Display TYPICAL APPLICATION R14 10 C12 1uF VOUT2 +1.2V/2A M3 IRFR3706 VCC D1 MBR0530T1 LDO OUT C9 47uF C10 150pF BST LDO FB C8 150uF 25mohm R8 5k R9 10k COMP C13 200pF R5 5.36k NX2309 VOUT1 +1.8V C4 0.1uF HDRV C2 180uF M1 IRFR3709Z L2 1.5uH C7 4SEPC560M 560uF,7mohm M2 IRFR3709Z R2 1.43k FB VIN1 +12V C3 47uF SW LDRV C5 6.8nF L1 1uH VOUT1 +1.8V/10A R3 10k C6 2.7nF GND R4 8k Figure1 - Typical application of NX2309 ORDERING INFORMATION Device NX2309CUTR NX2309CMTR Rev. 2.0 12/19/05 Temperature 0 to 70oC 0 to 70oC Package MSOP - 10L MLPD - 10L Frequency 300kHz 300kHz Pb-Free Yes Yes 1 NX2309 ABSOLUTE MAXIMUM RATINGS(NOTE1) Vcc to PGND & BST to SW voltage .................... -0.3V to 16V BST to PGND Voltage ...................................... -0.3V to 35V SW to PGND .................................................... -2V to 35V All other pins .................................................... -0.3V to 6.5V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 10-LEAD PLASTIC MSOP 10-LEAD PLASTIC MLPD θ JA ≈ 52o C /W θJA ≈ 200o C/W BST 1 BST 1 10 SW 10 SW HDrv 2 9 COMP Gnd 3 8 FB LDrv 4 7 LDO_FB LDrv 4 7 LDO_FB 6 LDO_OUT VCC 5 6 LDO_OUT Vcc 5 HDrv 2 NC 3 Gnd (PAD) 9 COMP 8 FB ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc =12V, VBST-VSW =12V, and T A = 0 to 70oC. Typical values refer to TA = 25oC. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range VCC Supply Current (Static) SYM Test Condition VREF VCC ICC (Static) Outputs not switching ICC CL=3300PF (Dynamic) Supply Voltage(VBST) VBST Voltage Range VBST to VSW Under Voltage Lockout VCC-Threshold VCC-Hysteresis Rev. 2.0 12/19/05 TYP MAX 0.8 0.2 10V<=VCC<=14V VCC Supply Current (Dynamic) VBST Supply Current Min Units V % 5 V mA 17 mA 7 14 7 14 V VBST CL=3300PF (Dynamic) 12 mA VCC_UVLO VCC Rising VCC_Hyst VCC Falling 6.6 0.3 V V 2 NX2309 PARAMETER SYM Oscillator Frequency FS Ramp-Amplitude Voltage VRAMP Max Duty Cycle Min Duty Cycle Error Amplifiers Open Loop Gain Transconductance gm Input Bias Current Ib EN & SS Soft Start time Tss Comp SD threshold High Side Driver, Hdrv, BST, SW (CL=3300pF) Output Impedance , Sourcing Rsource(Hdrv) Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Test Condition Min TYP MAX Units 0 KHz V % % 100 dB umho nA 300 1.1 95 50 65 2000 6.8 0.2 mS V I=200mA 3.6 ohm I=200mA 1 ohm THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going High, 10% to 10% H) 30 20 50 ns ns ns Rsource(Ldrv) I=200mA 2.2 ohm Rsink(Ldrv) I=200mA 1 ohm 30 20 50 ns ns ns Rsink(Hdrv) Low Side Driver , Ldrv, PVcc, Pgnd(CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current N Rise Time Fall Time Deadband Time LDO Controller FB Pin- Bias Current High Output Voltage Low Output Voltage High Output Source Current Low Output Sink Current Open Loop Gain FB Under Voltage trip point Fixed OCP OCP Voltage Threshold Rev. 2.0 12/19/05 TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 50 nA V V mA mA db % 240 mV 100 11.1 0.2 1.9 0.9 GBNT(NOTE 2) 50 3 NX2309 NOTE1: In actual circuit application, the ENSW pin is used to program converter start up and hysteresis threshold voltage. NOTE2: This parameter is guaranteed by design but not tested in production(GBNT). PIN DESCRIPTIONS PIN # PIN SYMBOL 5 VCC Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. The maximum rating of this pin is 16V. 1 BST This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as close as possible to and connected to this pin and SW pin. 3 GND Power ground. 8 FB 9 COMP 10 SW 2 HDRV High side gate driver output. 4 LDRV Low side gate driver output. 6 LDO_FB LDO controller feedback input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage.If the LDOFB pin is pulled below 0.4V, an internal comparator after a delay pulls down LDOOUT pin and initiates the HICCUP circuitry. During the startup this latch is not activated, allowing the LDOFB pin to come up and follow the soft started Vref voltage. 7 LDO_OUT LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum rating of this pin is 16V. Rev. 2.0 12/19/05 PIN DESCRIPTION This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.2V, both drivers are turned off and internal soft start is reset. This pin is connected to source of high side FETs and provide return path for the high side driver. It is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. LDRV can only go high if SW is below 1V threshold . 4 NX2309 BLOCK DIAGRAM VCC Bias Regulator Bias Generator 1.25V 0.8V UVLO BST POR 7.2/6.8V START HDRV COMP 0.2V SW OC Control Logic START 0.8V VCC PWM OSC Digital start Up ramp S R LDRV Q OC FB 0.6V CLAMP COMP 1.3V CLAMP 240mV Hiccup Logic START 0.4 OCP comparator GND LDOFB POR LDO digital start up LDOOUT Figure 2 - Simplified block diagram of the NX2309 Rev. 2.0 12/19/05 5 NX2309 APPLICATION INFORMATION IRIPPLE = Symbol Used In Application Information: VIN - Input voltage VOUT - Output voltage IOUT - Output current = VIN -VOUT VOUT 1 × × LOUT VIN FS ...(2) 12V-1.8V 1.8V 1 × × = 3.4A 1.5uH 12V 300kHz Output Capacitor Selection DVRIPPLE - Output voltage ripple Output capacitor is basically decided by the FS - Switching frequency amount of the output voltage ripple allowed during steady DIRIPPLE - Inductor current ripple state(DC) load condition as well as specification for the load transient. The optimum design may require a couple VIN=12V of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load VOUT=1.8V condition is determined by equation(3). Design Example Power stage design requirements: IOUT =10A ∆VRIPPLE = ESR × ∆IRIPPLE + DVRIPPLE <=25mV DVTRAN<=100mV @ 5A step ∆IRIPPLE 8 × FS × COUT ...(3) Where ESR is the output capacitors' equivalent FS=300kHz series resistance,COUT is the value of output capacitors. Output Inductor Selection such as Aluminum Electrolytic,POSCAP and OSCON Typically when large value capacitors are selected The selection of inductor value is based on induc- types are used, the amount of the output voltage ripple tor ripple current, power rating, working frequency and is dominated by the first term in equation(3) and the efficiency. Larger inductor value normally means smaller second term can be neglected. ripple current. However if the inductance is chosen too For this example, OSCON are chosen as output large, it brings slow response and lower efficiency. Usu- capacitors, the ESR and inductor current typically de- ally the ripple current ranges from 20% to 40% of the termines the output voltage ripple. output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations: L OUT = VIN -VOUT VOUT 1 × × IRIPPLE VIN FS IRIPPLE =k × IOUTPUT ESR desire = ∆VRIPPLE 25mV = = 7.3mΩ ∆IRIPPLE 3.4A ...(4) If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 25mV output ripple, OSCON ...(1) where k is between 0.2 to 0.4. Select k=0.4, then 12V-1.8V 1.8V 1 LOUT = × × 0.4 × 10A 12V 300kHz LOUT =1.3uH Choose LOUT=1.5uH, then coilcraft inductor DO5010P-152HC is a good choice. 4SEPC560M with 7mΩ are chosen. N = E S R E × ∆ IR I P P L E ∆ VR IPPLE ...(5) Number of Capacitor is calculated as N= 7m Ω × 3.4A 25mV N =0.95 The number of capacitor has to be round up to a integer. Choose N =1. Current Ripple is calculated as Rev. 2.0 12/19/05 6 NX2309 If ceramic capacitors are chosen as output ca- put inductor is smaller than the critical inductance, the pacitors, both terms in equation (3) need to be evalu- voltage droop or overshoot is only dependent on the ESR ated to determine the overall ripple. Usually when this of output capacitor. For low frequency capacitor such type of capacitors are selected, the amount of capaci- as electrolytic capacitor, the product of ESR and ca- tance per single unit is not sufficient to meet the tran- pacitance is high and L ≤ L crit is true. In that case, the sient specification, which results in parallel configura- transient spec is mostly like to dependent on the ESR tion of multiple capacitors. of capacitor. For example, one 100uF, X5R ceramic capacitor with 2mΩ ESR is used. The amount of output ripple is Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following 3.4A 8 × 300kHz × 100uF = 6.8mV + 14.1mV = 20.9mV ∆VRIPPLE = 2mΩ × 3.4A + N= Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × C E × ∆Vtran ...(9) where 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT if L ≥ L crit ...(10) is specified as ∆V droop < ∆V tran @step load DISTEP For example, assume voltage droop during tran- During the transient, the voltage droop during the transient is composed of two sections. One section is sient is 100mV for 5A load step. dependent on the ESR of capacitor, the other section is If the OSCON 4SEPC560M (560uF, 7mohm ESR) is used, the crticial inductance is given as a function of the inductor, output capacitance as well as input, output voltage. For example, for the over- L crit = shoot when load from high load to light load with a DISTEP transient load, if assuming the bandwidth of 7mΩ × 560µF × 1.8V = 1.42µH 5A system is high enough, the overshoot can be estimated as the following equation. ∆Vovershoot VOUT = ESR × ∆Istep + × τ2 2 × L × COUT ...(6) where τ is the a function of capacitor,etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT if L ≥ L crit The selected inductor is 1.5uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitor is τ= ...(7) = where L crit = ESR × COUT × VOUT ESR E × C E × VOUT = ...(8) ∆Istep ∆Istep where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected outRev. 2.0 12/19/05 ESR E × C E × VOUT = ∆Istep N= L × ∆I step VOUT − ESR E × C E 1.5µH × 5A − 7mΩ × 560µF = 0.25us 1.8V ESR E × ∆I step ∆Vtran + VOUT × τ2 2 × L × C E × ∆ Vtran 7mΩ × 5A 1.8V + × (0.25us) 2 100mV 2 × 1.5µH × 560µF × 100mV = 0.35 = 7 NX2309 The number of capacitors has to satisfied both ripple and transient requirement. Overall, we choose N=1. FZ1 = 1 2 × π × R 4 × C2 ...(11) FZ2 = 1 2 × π × (R 2 + R3 ) × C3 ...(12) FP1 = 1 2 × π × R3 × C3 ...(13) It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP es- FP2 = pecially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors 1 ...(14) C × C2 2 × π × R4 × 1 C1 + C2 where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. The transfer function of type III compensator for transconductance amplifier is given by: Ve 1 − gm × Z f = VOUT 1 + gm × Zin + Z in / R1 For the voltage amplifier, the transfer function of compensator is Ve −Z f = VOUT Zin To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time, are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than cross- Zin Zf C1 Vout over frequency. Otherwise type III compensator should be chosen. R3 A. Type III compensator design C3 R2 caused by output capacitors is higher than the cross- R4 Fb For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero C2 gm Ve R1 Vref over frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier. Rev. 2.0 12/19/05 Figure 3 - Type III compensator using transconductance amplifier 8 NX2309 Case 1: FLC<FO<FESR(for most ceramic or low 2. Set R2 equal to 10kΩ. ESR POSCAP, OSCON) R1= R 2 × VREF 10k Ω × 0.8V = = 8k Ω VOUT -VREF 1.8V-0.8V Gain(db) Choose R1=8.06kΩ. 3. Set zero FZ2 = FLC and Fp1 =FESR, calculate C3. power stage FLC 40dB/decade C3 = 1 1 1 ) ×( 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 10kΩ 5.5kHz 40.6kHz =2.5nF = loop gain FESR Choose C3=2.7nF. 4. Calculate R 4 with the crossover frequency at 1/ 20dB/decade 10~ 1/5 of the switching frequency. Set FO=30kHz. R4 = compensator VOSC 2 × π × FO × L × × Cout Vin C3 1.1V 2 × π × 30kHz × 1.5uH × × 560uF 12V 2.7nF =5.38kΩ = FZ1 FZ2 FO FP1 FP2 Choose R4=5.36kΩ. 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). Figure 4 - Bode plot of Type III compensator (FLC<FO<FESR) Typical design example of type III compensator in which the crossover frequency is selected as FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the following steps. and ESR zero FESR. = 1 2 × π × 0.75 × 5.5kHz × 5.36kΩ = 7.1nF = 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. 1 2 × π × L OUT × COUT 1 2 × π × 1.5uH × 560uF = 5.5kHz FESR = 1 2 × π × FZ1 × R 4 Choose C2=6.8nF. 1. Calculate the location of LC double pole F LC FLC = C2 = 1 2 × π × ESR × C OUT C1 = 1 2 × π × R 4 × FP2 1 2 × π × 5.36kΩ × 150kHz = 197pF = Choose C1=200pF. 7. Calculate R3 by equation (13) with Fp1 =FESR. 1 2 × π × 7m Ω × 560uF = 40.6kHz = Rev. 2.0 12/19/05 9 NX2309 R3 = 1 2 × π × FP1 × C3 FESR = 1 2 × π × 40.6kHz × 2.5nF = 1.45kΩ = 1 2 × π × ESR × COUT 1 2 × π × 15mΩ × 2000uF = 5.3kHz = Choose R3 =1.43kΩ. Gain(db) Case 2: FLC<FESR<FO(for electrolytic capacitors) 2. Set R2 equal to 15kΩ. R1= power stage FLC 40dB/decade FESR R 2 × VREF 15k Ω × 0.8V = = 12k Ω VOUT -VREF 1.8V-0.8V Choose R1=12kΩ. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate C3 . C3 = loop gain 1 1 1 ×( ) 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 15k Ω 1.8kHz 5.3kHz =2.4nF = 20dB/decade Choose C3=2.7nF. 5. Calculate R3 . compensator R3 = 1 2 × π × FP1 × C 3 1 2 × π × 5.3kHz × 2.7F = 11.1k Ω = FZ1 FZ2 FP1 FO FP2 Figure 5 - Bode plot of Type III compensator (FLC<FESR<FO) If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which the crossover frequency is selected as FLC<FESR<FO and F O<=1/10~1/5Fs is shown as the following steps. Here two SANYO MV-WG1000 with 30 mΩ is chosen as output capacitor, output inductor is 2.2uH. See figure 18. Choose R3 =11kΩ. 6. Calculate R4 with FO=30kHz. R4 = VOSC 2 × π × FO × L R 2 × R 3 × × Vin ESR R2 + R3 1.1V 2 × π × 30kHz × 2.2uH 15k Ω × 11k Ω × × 12V 15m Ω 15k Ω + 11k Ω =16k Ω = Choose R4=16kΩ. 7. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). 1. Calculate the location of LC double pole F LC C2 = and ESR zero FESR. FLC = = 1 2 × π × LOUT × COUT 1 2 × π × 2.2uH × 2000uF = 1.8kHz Rev. 2.0 12/19/05 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 1.8kHz × 16k Ω = 4.2nF = Choose C2=4.7nF. 8. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. 10 NX2309 1 2 × π × R 4 × FP2 1 2 × π × 16k Ω × 150kHz = 66pF = Choose C1=68pF. power stage Gain(db) C1 = 40dB/decade loop gain B. Type II compensator design If the electrolytic capacitors are chosen as power 20dB/decade stage output capacitors, usually the Type II compensator can be used to compensate the system. For this type of compensator, FO has to satisfy compensator FLC<FESR<<FO<=1/10~1/5Fs. Gain Case 1: Type II compensator can be realized by simple FZ FLC FESR RC circuit as shown in figure 14. R3 and C1 introduce a FO FP zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The following equations show the compensator pole zero location and constant gain. Gain= Fz = R3 R2 1 2 × π × R3 × C1 Fp ≈ 1 2 × π × R 3 × C2 Figure 6 - Bode plot of Type II compensator C2 Vout R3 C1 R2 Fb Ve ... (15) R1 ... (16) ... (17) Vref Figure 7 - Type II compensator with transconductance amplifier(case 1) The following parameters are used as an example for type II compensator design, three 1500uF with 19mohm Sanyo electrolytic CAP 6MV1500WGL are used as output capacitors. Coilcraft DO5010P152HC 1.5uH is used as output inductor. See figure 19. The power stage information is that: VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz. 1.Calculate the location of LC double pole F LC and ESR zero FESR. Rev. 2.0 12/19/05 11 NX2309 FLC = Case 2: 1 2 × π × L OUT × COUT 1 = 2 × π × 1.5uH × 4500uF = 1.94kHz FESR = 1 2 × π × ESR × COUT 1 = 2 × π × 6.33m Ω × 4500uF = 5.6kHz 2.Set crossover frequency FO=30kHz>>FESR. 3. Set R2 equal to10kΩ. Based on output voltage, Type II compensator can also be realized by simple RC circuit without feedback as shown in figure 15. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain. Gain=gm × Fz = R1 × R3 R1 +R 2 1 2 × π × R3 × C1 Fp ≈ 1 2 × π × R 3 × C2 ... (18) ... (19) ... (20) using equation 21, the final selection of R 1 is 20kΩ. 4.Calculate R3 value by the following equation. R3= V O S C 2 × π × FO × L × × R2 V in ESR 1.1V 2 × π × 3 0 k H z × 1 .5uH × × 10kΩ 12V 6.33m Ω =37.2kΩ Vout R2 = Fb gm R1 R3 Vref Choose R 3 =37.4kΩ. Ve C2 5. Calculate C1 by setting compensator zero FZ C1 at 75% of the LC double pole. 1 2 × π × R3 × Fz C1= 1 2 × π × 37.4kΩ × 0.75 × 1.94kHz =2.9nF = Choose C1=2.7nF. 6. Calculate C 2 by setting compensator pole Fp at half the swithing frequency. 1 C2= π × R 3 × Fs 1 π × 3 7 .4k Ω × 1 5 0 k H z =57pF Figure 8 - Type II compensator with transconductance amplifier(case 2) The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 2.5V, output inductor is 2.2uH, output capacitors are two 680uF with 41mΩ electrolytic capacitors. See figure 20. 1.Calculate the location of LC double pole F LC and ESR zero FESR. = Choose C2=56pF. FLC = = 1 2 × π × L OUT × COUT 1 2 × π × 2.2uH × 1360uF = 2.9kHz Rev. 2.0 12/19/05 12 NX2309 FESR = 1 2 × π × ESR × COUT 1 = 2 × π × 20.5m Ω × 1360uF = 5.7kHz 2.Set R2 equal to10kΩ. Using equation 18, the final selection of R1 is 4.7kΩ. 3. Set crossover frequency at 1/10~ 1/5 of the 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation applies to figure 9, which shows the relationship between Vout R2 Fb swithing frequency, here FO=30kHz. 4.Calculate R3 value by the following equation. R3 = R1 VOSC 2 × π × FO × L 1 VOUT × × × Vin RESR gm VREF 1.1V 2 × π × 30kHz × 2.2uH 1 × × 12 20.5m Ω 2mA/V 2.5V × 0.8V =2.9k Ω VOUT , VREF and voltage divider.. Vref Figure 9 - Voltage divider = R 2 × VR E F V O U T -V R E F R 1= ...(21) where R 2 is part of the compensator, and the Choose R3 =2.87kΩ. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. C1 = 1 2 × π × R3 × Fz 1 2 × π × 2.87kΩ × 0.75 × 2.9kHz =25nF = Choose C1=27nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency. C2= 1 π × R 3 × Fs 1 π × 2 .87k Ω × 150kH z =369pF = Choose C2=390pF. value of R1 value can be set by voltage divider. See compensator design for R1 and R2 selection. Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as: IRMS = IOUT × D × 1- D D= VOUT VIN ...(22) VIN = 12V, VOUT=1.8V, IOUT=10A, using equation (19), the result of input RMS current is 3.6A. For higher efficiency, low ESR capacitors are recommended. Output Voltage Calculation Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at Rev. 2.0 12/19/05 One Sanyo OS-CON 16SVP180M 16V 180uF 20mΩ with 3.64A RMS rating are chosen as input bulk capacitors. 13 NX2309 Power MOSFETs Selection The NX2309 requires two N-Channel power This power dissipation should not exceed maximum power dissipation of the driver device. MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, Over Current Limit Protection maximum current rating, MOSFET on resistance and Over current Limit for step down converter is power dissipation. The main consideration is the power achieved by sensing current through the low side loss contribution of MOSFETs to the overall converter efficiency. In this design example, two IRFR3706 are used.They have the following parameters: VDS=30V, ID MOSFET. For NX2309, the current limit is decided by =75A,RDSON =9mΩ,QGATE =23nC. the over current occurs. The over current limit can be There are two factors causing the MOSFET power Conduction loss is simply defined as: ...(23) where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to IRFR3706 datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total 1 × VIN × IOUT × TSW × FS 2 ISET = 240mV 240mV = = 17A RDSON 1.4 × 9mΩ LDO Selection Guide NX2309 offers a LDO controller. The selection of MOSFET to meet LDO is more straight forward. The selection is that the Rdson of MOSFET should meet the dropout requirement. For example. VLDOIN =1.8V VLDOOUT =1.2V ILoad =2A The maximum Rdson of MOSFET should be switching loss can be approximated. PSW = calculated by the following equation. The MOSFET RDSON is calculated in the worst case situation, then the current limit for MOSFET IRFR3706 is PHCON =IOUT 2 × D × RDS(ON) × K PTOTAL =PHCON + PLCON FET is on, and the voltage on SW pin is below 240mV, ISET = 240mV/R DSON loss:conduction loss, switching loss. PLCON =IOUT 2 × (1 − D) × RDS(ON) × K the RDSON of the low side mosfet. When synchronous R RDSON = (VLDOIN − VLDOOUT ) × I LOAD ...(24) = (1.8V − 1.2V) / 2A = 0.3Ω Most of MOSFETs can meet the requirement. More and TF which can be found in mosfet datasheet, and FS important is that MOSFET has to be selected right pack- is switching frequency. Swithing loss PSW is frequency age to handle the thermal capability. For LDO, maxi- dependent. mum power dissipation is given as Also MOSFET gate driver loss should be consid- PLOSS = (VLDOIN − VLDOOUT ) × I LOAD ered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(25) = (1.8V − 1.2V) × 2A = 1.2W Select IR MOSFET IRFR3706 with 9mΩ RDSON is sufficient. LDO Compensation where QHGATE is the high side MOSFETs gate The diagram of LDO controller including VCC regu- charge,QLGATE is the low side MOSFETs gate charge,VHGS lator is shown in above figure 9. For low frequency ca- is the high side gate source voltage, and VLGS is the low side gate source voltage. Rev. 2.0 12/19/05 14 NX2309 pacitor such as electrolytic, POSCAP, OSCON, etc, The compensation parameter can be calculated as follows. CC = g × ESR 1 × m 2 × π × FO × R f1 1+gm × ESR Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. where FO is the desired loop gain. There are two sets of components considered in the layout which are power components and small sig- + LDO input nal components. Power components usually consist of Vref input capacitors, high-side MOSFET, low-side MOSFET, Rf1 inductor and output capacitors. A noisy environment is ESR Rf2 Rc Rload Cc Co generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Figure 10 - NX2309 LDO controller. Layout guidelines: 1. First put all the power components in the top Typically, F O has to be higher than zero caused by layer connected by wide, copper filled areas. The input ESR. FO is typically around several tens kHz to a few capacitor, inductor, output capacitor and the MOSFETs hundred kHz. For this example, we select Fo=100kHz. should be close to each other as possible. This helps to gm is the forward trans-conductance of MOSFET. reduce the EMI radiated by the power loop due to the For IRFR3706, gm=53. Select Rf1=5kohm. Output capacitor is Sanyo POSCAP 4TPE150MI high switching currents through them. 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic with 150uF, ESR=18mohm. cap which usually is 1uF need to be practically touch- 1 53 × 18m Ω CC = × =155pF 2 × π × 100kHz × 5kΩ 1+53 × 18m Ω ing the drain pin of the upper MOSFET, a plane connec- Choose CC=150pF. For electrolytic or POSCAP, RC is typically selected tion is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of to be zero. Rf2 is determined by the desired output voltage the high-side MOSFET need to be connected thru a plane R f 2 = R f 1 × VREF /(VLDOOUT − VREF ) ans as close as possible. A snubber nedds to be placed = 5kΩ × 0.8V /(1.2V − 0.8) = 10kΩ Choose Rf2=10kΩ. as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the Current Limit for LDO output capacitors and input capacitors. Current limit of LDO is achieved by sensing the 6. Hdrv and Ldrv pins should be as close to LDO feedback voltage. When LDO_FB pin is below 0.4V, MOSFET gate as possible. The gate traces should be the IC goes into hiccup mode. The IC will turn off all the wide and short. A place for gate drv resistors is needed channel for 2048 cycles and start to restart system again. to fine tune noise if needed. Rev. 2.0 12/19/05 15 NX2309 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. Rev. 2.0 12/19/05 16