TI V62/07612-03NE

SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Meet or Exceed the Requirements of ANSI
TIA/EIA-644-1995 Standard
Signaling Rates up to 400 Mbps
Bus-Terminal ESD Exceeds 12 kV
Operates From a Single 3.3-V Supply
Low-Voltage Differential Signaling With
Typical Output Voltages of 350 mV and a
100-Ω Load
Propagation Delay Times
– Driver: 1.7 ns Typ
– Receiver: 3.7 ns Typ
Power Dissipation at 200 MHz
– Driver: 25 mW Typical
– Receiver: 60 mW Typical
LVTTL Input Levels Are 5-V Tolerant
Receiver Maintains High Input Impedance
With VCC < 1.5 V
Receiver Has Open-Circuit Fail Safe
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
SN65LVDS179
D OR DGK PACKAGE
(TOP VIEW)
VCC
R
D
GND
1
8
2
7
3
6
4
5
A
B
Z
Y
D
2
Z
A
7
R
B
SN65LVDS180
D OR PW PACKAGE
(TOP VIEW)
NC
R
RE
DE
D
GND
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
SN65LVDS050
D OR PW PACKAGE
(TOP VIEW)
1B
1A
1R
RE
2R
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1D
1Y
1Z
DE
2Z
2Y
2D
1B
1A
1R
1DE
2R
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1D
1Y
1Z
2DE
2Z
2Y
2D
9
5
D
10
4
DE
12
2
11
R
15
1D
14
13
12
DE
10
9
2D
3
1R
11
2
1
4
RE
6
5
2R
15
7
14
13
4
1DE
2
3
1R
9
2D
1
10
11
12
2DE
6
5
2R
Y
Z
3
RE
1D
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Y
6
8
SN65LVDS051
D OR PW PACKAGE
(TOP VIEW)
(1)
5
3
7
A
B
1Y
1Z
2Y
2Z
1A
1B
2A
2B
1Y
1Z
1A
1B
2Y
2Z
2A
2B
DESCRIPTION/ORDERING INFORMATION
The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and
receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The
TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of
247 mV into a 100-Ω load, and receipt of 100-mV signals with up to 1 V of ground potential difference between
a transmitter and receiver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media
may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
application specific characteristics.)
The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these
devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not
put the differential outputs into a high-impedance state, but rather disconnects the input and reduces the
quiescent power used by the device. (For these functions with a high-impedance driver output, see the
SN65LVDM series of devices.) All devices are characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS (1)
TA
PACKAGE
SMALL OUTLINE (DGK)
SMALL OUTLINE (PW)
SMALL OUTLINE (D)
-55°C TO 125°C
SN65LVDS050MDREP (2)
SN65LVDS050MPWREP (2)
SN65LVDS051MDREP (2)
SN65LVDS051MPWREP (2)
SN65LVDS179MDREP (2)
SN65LVDS179MDGKREP
SN65LVDS180MDREP (2)
(1)
(2)
2
SN65LVDS180MPWREP (2)
For the most current packaging and odering infomation, see the Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Product Preview
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
FUNCTION TABLES
BLK
SN65LVDS179 Receiver (1)
INPUTS
OUTPUT
R
VID = VA – VB
(1)
VID ≥ 100 mV
H
– 100 mV < VID < 100 mV
?
VID ≥ 100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
SN65LVDS179 Driver (1)
INPUT
D
OUTPUTS
Y
Z
H
L
L
H
H
L
Open
L
H
(1)
H = high level, L = low level
SN65LVDS180, SN65LVDS050, and SN65LVDS051
Receiver (1)
INPUTS
VID = VA – VB
RE
OUTPUT
R
VID ≥ 100 mV
L
H
– 100 mV < VID < 100 mV
L
?
VID ≤– 100 mV
L
L
Open
L
H
X
H
Z
(1)
H = high level, L = low level, Z = high impedance, X = don't care
SN65LVDS180, SN65LVDS050, and SN65LVDS051
Driver (1)
INPUTS
(1)
OUTPUTS
D
DE
Y
Z
L
H
L
H
H
H
H
L
Open
H
L
H
X
L
OFF
OFF
H = high level, L = low level, OFF = No Output, X = don't care
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
VCC
300 kΩ
50 Ω
5Ω
10 kΩ
D or
RE
Input
Y or Z
Output
50 Ω
DE
Input
7V
300 kΩ
7V
7V
VCC
VCC
300 kΩ
300 kΩ
5Ω
A Input
7V
4
R Output
B Input
7V
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7V
SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
4
D, R, DE, and RE
–0.5
6
Y, Z, A, and B
–0.5
4
Supply voltage range (2)
VCC
Voltage range
Y, Z, A, B, and GND (3)
Electrostatic discharge
V
Class 3, A: 7 kV, B: 500 V
See Dissipation Rating
Table
Storage temperature range
– 65
Lead temperature 1,6 mm (1/16 in) from case for 10 s
(2)
(3)
V
Class 3, A: 12 kV, B: 600 V
All
Continuous power dissipation
(1)
UNIT
150
°C
250
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
Tested in accordance with MIL-STD-883C Method 3015.7
Dissipation Ratings Table
(1)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR
ABOVE TA =
25°C (1)
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
DGK
424 mW
3.4 mW/°C
220 mW
84mW
PW(14)
736mw
5.9 mW/°C
383 mW
146mW
PW(16)
839mw
6.7 mW/°C
437 mW
169mW
D(8)
635mw
5.1 mW/°C
330 mW
125mW
D(14)
987mw
7.9 mW/°C
513 mW
197mW
D(16)
1110mw
8.9 mW/°C
577 mW
220mW
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air
flow.
Recommended Operating Conditions
MIN
NOM
MAX
3.3
3.6
VCC
Supply voltage
3
VIH
High-level input voltage
2
VIL
Low-level input voltage
|VID|
Magnitude of differential input voltage
|VOD(dis)|
Magnitude of differential output voltage with disabled driver
VOY or VOZ
Driver output voltage
VIC
Common-mode input voltage (see Figure 5)
V
V
0.8
0.1
0
ŤV Ť
ID
2
UNIT
V
0.6
V
520
mV
2.4
V
ŤV Ť
2.4 *
ID
2
V
VCC – 0.8
TA
(1)
Operating free-air
temperature (1)
–55
125
°C
Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
Device Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS179
SN65LVDS180
Supply
current
ICC
SN65LVDS050
MIN TYP (1) MAX
No receiver load, Driver RL = 100 Ω
9
12
Driver and receiver enabled, No receiver load,
Driver RL = 100 Ω
9
12
Driver enabled, Receiver disabled, RL = 100 Ω
5
7
Driver disabled, Receiver enabled, No load
1.5
2
Disabled
0.5
1
Drivers and receivers enabled, No receiver loads,
Driver RL = 100 Ω
12
20
Drivers enabled, Receivers disabled, RL = 100 Ω
10
16
3
6
Drivers disabled, Receivers enabled, No loads
SN65LVDS051
(1)
Disabled
0.5
1
Drivers enabled, No receiver loads, Driver RL = 100 Ω
12
20
3
6
Drivers disabled, No loads
UNIT
mA
mA
mA
mA
All typical values are at 25°C and with a 3.3-V supply.
Driver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOD|
Differential output voltage magnitude
∆|VOD|
Change in differential output voltage magnitude
between logic states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage
between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
IIH
High-level input current
IIL
Low-level input current
IOS
Short-circuit output current
DE
D
DE
D
RL = 100 Ω,
See Figure 1 and
Figure 2
MIN
TYP
MAX
247
340
454
–50
1.125
See Figure 3
50
1.2
–50
1.375
mV
150
–20
2
20
–0.5
–10
2
10
VOY or VOZ = 0 V
3
10
VOD = 0 V
3
10
DE = 0 V,
VOY = VOZ = 0 V
6
IO(OFF)
Off-state output current
CIN
Input capacitance
DE = VCC,
VOY = VOZ = 0 V,
VCC < 1.5 V
–1
1
3
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V
mV
50
VIL = 0.8 V
mV
50
–0.5
VIH = 5 V
UNIT
µA
µA
mA
µA
pF
SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
Receiver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
VIT+
Positive-going differential input voltage threshold
VIT–
Negative-going differential input voltage threshold
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (A or B inputs)
II(OFF)
Power-off input current (A or B inputs)
VCC = 0 V
±20
µA
IIH
High-level input current (enables)
VIH = 5 V
±10
µA
IIL
Low-level input current (enables)
VIL = 0.8 V
±10
µA
IOZ
High-impedance output current
VO = 0 or 5 V
±10
µA
CI
Input capacitance
See Figure 5 and Table 1
mV
–100
IOH = –8 mA
2.4
IOH = –4 mA
2.8
V
IOL = 8 mA
VI = 0
VI = 2.4 V
0.4
–2
–11
–1.2
–3
–20
5
V
µA
pF
Driver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
1.7
4.5
ns
tPHL
Propagation delay time, high- to low-level output
1.7
4.5
ns
tr
Differential output signal rise time
0.8
1.2
ns
tf
Differential output signal fall time
0.8
1.2
ns
tsk(p)
Pulse skew (|tPHL – tPLH|) (2)
300
tsk(o)
Channel-to-channel output skew (3)
150
ten
Enable time
4.3
10
ns
tdis
Disable time
3.1
10
ns
(1)
(2)
(3)
RL = 100 Ω, CL = 10 pF,
See Figure 2
See Figure 4
ps
ps
All typical values are at 25°C and with a 3.3-V supply.
tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
Receiver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
3.7
4.5
ns
tPHL
Propagation delay time, high- to low-level output
3.7
4.5
ns
tsk(p)
Pulse skew (|tPHL – tPLH|) (2)
tr
Output signal rise time
0.7
1.5
ns
tf
Output signal fall time
0.9
1.5
ns
tPZH
Propagation delay time, high-impedance to high-level output
2.5
ns
tPZL
Propagation delay time, high-impedance to low-level output
2.5
ns
tPHZ
Propagation delay time, high-level to high-impedance output
7
ns
tPLZ
Propagation delay time, low-level to high-impedance output
4
ns
(1)
(2)
CL = 10 pF,
See Figure 6
See Figure 7
0.3
ns
All typical values are at 25°C and with a 3.3-V supply.
tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
Driver
IOY
Driver Enable
Y
II
A
IOZ
VOD
V
VOY
Z
OY
)V
OZ
2
VI
VOC
VOZ
Figure 1. Driver Voltage and Current Definitions
Driver Enable
Y
100 Ω
±1%
VOD
Input
Z
CL = 10 pF
(2 Places)
2V
1.4 V
0.8 V
Input
tPHL
tPLH
100%
80%
Output
VOD(H)
0V
VOD(L)
20%
0%
tf
A.
tr
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
8
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
49.9 Ω, ±1% (2 Places)
Driver Enable
3V
Y
0V
Input
Z
VOC
VOC(PP)
CL = 10 pF
(2 Places)
VOC(SS)
VOC
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
49.9 Ω, ±1% (2 Places)
Y
0.8 V or 2 V
Z
DE
1.2 V
CL = 10 pF
(2 Places)
VOY
2V
1.4 V
0.8 V
DE
VOY or VOZ
ten
ten
~1.4 V
1.25 V
1.2 V
D at 2 V and input to DE
1.2 V
1.15 V
~1 V
D at 0.8 V and input to DE
tdis
VOZ or VOY
A.
VOZ
tdis
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Receiver
A
V
IA
)V
IB
VID
2
R
VIA
VIC
B
VO
VIB
Figure 5. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
(V)
10
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMON-MODE
INPUT VOLTAGE
(V)
VIA
VIB
VID
VIC
1.25
1.15
100
1.2
1.15
1.25
–100
1.2
2.4
2.3
100
2.35
2.3
2.4
–100
2.35
0.1
0
100
0.05
0
0.1
–100
0.05
1.5
0.9
600
1.2
0.9
1.5
–600
1.2
2.4
1.8
600
2.1
1.8
2.4
–600
2.1
0.6
0
600
0.3
0
0.6
–600
0.3
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
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SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
VID
VIA
VIB
CL
10 pF
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
−0.4 V
tPHL
VO
tPLH
VOH
2.4 V
1.4 V
0.4 V
VOL
tf
A.
tr
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 6. Timing Test Circuit and Waveforms
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
B
1.2 V
500 Ω
A
Inputs
A.
CL
10 pF
RE
+
−
VO
VTEST
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
2.5 V
VTEST
A
1V
2V
RE
1.4 V
0.8 V
tPZL
tPZL
tPLZ
2.5 V
1.4 V
R
VOL +0.5 V
VOL
0V
VTEST
A
1.4 V
2V
RE
1.4 V
0.8 V
tPZH
R
tPZH
tPHZ
VOH −0.5 V
VOH
1.4 V
0V
Figure 7. Enable/Disable Time Test Circuit and Waveforms
12
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SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
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SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
DISABLED DRIVER OUTPUT CURRENT
vs
OUTPUT VOLTAGE
Disabled Driver Output Current − mA
40
VCC = 3.3 V
TA = 25°C
DE = 0 V
30
VOZ = 0 V
20
VOZ = 1.2 V
10
VOZ = VOY
0
−10
VOZ = 2.4 V
−20
−30
0
0.5
1
1.5
2
VO − Output Voltage − V
2.5
3
Figure 8.
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
VCC = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
4
3
2
1
0
0
2
4
6
VCC = 3.3 V
TA = 25°C
3
2.5
2
1.5
1
0.5
0
−4
IOL − Low-Level Output Current − mA
Figure 9.
−3
−2
−1
0
IOH − High-Level Output Current − mA
Figure 10.
Submit Documentation Feedback
13
SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
4
VCC = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Votlage − V
VCC = 3.3 V
TA = 25°C
4
3
2
1
0
0
10
20
30
40
50
IOL − Low-Level Output Current − mA
3
2
1
0
−80
60
−60
−40
−20
IOH − High-Level Output Current − mA
Figure 11.
Figure 12.
DRIVER
DRIVER
HIGH- TO LOW-LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW- TO HIGH-LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.5
2
t PLH − Low-To-High Propagation Delay Time − ns
t PHL − High-To-Low Propagation Delay Time − ns
2.5
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
1.5
−50
−30
−10
50
30
70
TA − Free-Air Temperature − °C
10
90
2
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
1.5
−50
Figure 13.
14
0
−30
−10
50
10
30
70
TA − Free-Air Temperature − °C
Figure 14.
Submit Documentation Feedback
90
SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
RECEIVER
RECEIVER
HIGH- TO LOW-LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW- TO HIGH-LEVEL PROPAGATION DELAY TIME
vs
FREE−AIR TEMPERATURE
4.5
VCC = 3.3 V
4
VCC = 3 V
3.5
VCC = 3.6 V
3
2.5
−50
−30
−10
50
30
70
TA − Free−Air Temperature − °C
10
90
t PLH − Low-To-High Level Propagation Delay Time − ns
t PLH − High-To-Low Level Propagation Dealy Time − ns
TYPICAL CHARACTERISTICS (continued)
4.5
VCC = 3 V
4
VCC = 3.3 V
3.5
VCC = 3.6 V
3
2.5
−50
Figure 15.
−30
−10
50
30
70
TA − Free-Air Temperature − °C
10
90
Figure 16.
Submit Documentation Feedback
15
SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common-mode output and balanced interface for very low noise
emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL
speeds without the power and dual supply requirements.
Transmission Distance − m
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
Data Rate − Hz
Figure 17. Data Transmission Distance Versus Rate
16
Submit Documentation Feedback
100M
SN65LVDS179-EP,, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B – SEPTEMBER 2003 – REVISED JANUARY 2007
APPLICATION INFORMATION (continued)
Fail Safe
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV
and within its recommended input common-mode voltage range. However, TI's LVDS receiver is different in how
it handles the open-input circuit situation.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 18. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level, regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt
100 Ω Typ
Y
B
VIT ≈ 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as
it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could
defeat the pullup currents from the receiver and the fail-safe feature.
Submit Documentation Feedback
17
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDS179MDGKREP
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/07612-03NE
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS179-EP :
• Catalog: SN65LVDS179
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN65LVDS179MDGKREP MSOP
DGK
8
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
5.3
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65LVDS179MDGKREP
MSOP
DGK
8
2500
358.0
335.0
35.0
Pack Materials-Page 2
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