TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 D D D D D D D D D This data sheet is applicable to TMS418160As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section. Organization . . . 1 048576 by 16 Bits Single 5-V Power Supply (± 10% Tolerance) 1 024-Cycle Refresh in 16 ms Performance Ranges: ACCESS ACCESS ACCESS TIME TIME TIME tRAC tCAC tAA MAX MAX MAX ’418160A-50 50 ns 13 ns 25 ns ’418160A-60 60 ns 15 ns 30 ns ’418160A-70 70 ns 18 ns 35 ns READ/ WRITE CYCLE MIN 90 ns 110 ns 130 ns Enhanced Page-Mode Operation With xCAS-Before-RAS ( xCBR) Refresh 3-State Unlatched Output Low Power Dissipation High-Reliability Plastic 42-Lead 400-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DZ Suffix) Ambient Temperature Range 0°C to 70°C DZ PACKAGE ( TOP VIEW ) VDD DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 NC NC W RAS NC NC A0 A1 A2 A3 VDD 1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 35 9 34 10 33 11 32 12 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS description The TMS418160A is a 16 777 216-bit dynamic random-access memory (DRAM) device organized as 1 048 576 words of 16 bits. It employs state-of-the-art technology for high performance, reliability, and low power at low cost. This device features maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. PIN NOMENCLATURE A[0 :9] DQ[0:15] LCAS UCAS NC OE RAS VDD VSS W Address Inputs Data In / Data Out Lower Column-Address Strobe Upper Column-Address Strobe No Internal Connection Output Enable Row-Address Strobe 5-V Supply Ground Write Enable The TMS418160A is offered in a 42-lead plastic surface-mount SOJ package (DZ suffix). This package is designed for operation from 0° to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 logic symbol† RAM 1M × 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 17 18 19 20 23 24 25 26 27 28 20D10/21D0 A 0 1 048 575 20D19/21D9 C20[ROW] G23/[REFRESH ROW] RAS LCAS 14 24[PWR DWN] C21 G24 31 & 31 23C22 C21 G34 UCAS 30 & 31 23C32 Z31 24,25EN27 W 13 OE 29 DQ0 2 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 3 4 5 7 8 9 10 33 34 DQ9 35 DQ10 DQ11 36 38 DQ12 39 DQ13 40 DQ14 41 DQ15 23,21D 34,25EN37 25 A,22D ∇26,27 A, Z26 A,32D ∇36,37 A, Z36 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 functional block diagram RAS UCAS LCAS W OE Timing and Control A0 A1 10 Column Decode Sense Amplifiers Column Address Buffers 256K Array 256K Array A9 Row Address Buffers 32 10 256K Array 32 256K Array R o w D e c o d e 256K Array 32 32 I/O Buffers 16 of 32 Selection DataIn Reg. DataOut Reg. 16 16 DQ0 – DQ15 256K Array 10 operation dual xCAS Two xCAS pins (LCAS and UCAS) are provided to give independent control of the 16 data I/O pins (DQ0– DQ15), with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. Each xCAS going low enables its corresponding DQx pin. In write cycles, data-in setup and hold time (tDS and tDH) and write-command setup and hold time (tWCS, tCWL and tWCH) must be satisfied for each individual xCAS to ensure writing into the storage cells of the corresponding DQ pins. Different modes of operation for upper and lower bytes in one cycle are not allowed, such as the example shown in Figure 1. RAS Delayed write UCAS Early write LCAS W Figure 1. Illegal Dual-xCAS Operation POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 enhanced page mode Page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the xCAS page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without intervening RAS cycles. Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the first xCAS latches the column addresses. This performance improvement is referred to as enhanced-page mode. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode because data retrieval begins as soon as the column address is valid rather than when xCAS transitions low. A valid column address may be presented immediately after tRAH (row-address hold time) has been satisfied, usually well in advance of the falling edge of xCAS. In this case, data is obtained after tCAC maximum (access time from xCAS low) if tAA maximum (access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined by tCPA. address: A0 – A9 Twenty address bits are required to decode each of the 1 048 576 storage cell locations. Twelve row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits are set up on A0 through A7 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the column-address buffers. The column address is latched on the first xCAS falling edge with address setup and hold parameters referenced to that edge. In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time (see parameter tCP) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum hold time, tCLCH. During tCLCH, at least one xCAS must be brought low before the other xCAS is taken high. write enable ( W) Read- or write mode is selected through W. A logic high on W selects the read mode and a logic low selects the write mode. Data in is disabled when the read mode is selected. When W goes low prior to xCAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation independent of the state of OE. This permits early-write operations to be completed with OE grounded. data in (DQ0 – DQ15) Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to a xCAS falling edge and the data is strobed into the on-chip data latch for the corresponding DQs with setup-and-hold times referenced to this xCAS signal. In a delayed-write- or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and hold times referenced to this signal. Also, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines (see parameter tOED). 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 data out (DQ0 – DQ15) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access-time-interval tCAC (which begins with the negative transition of xCAS) as long as tRAC (access time from RAS) and tAA (access time from column address) are satisfied. The delay time from xCAS low to valid data out is measured from each individual xCAS to its corresponding DQx pin. output enable (OE) OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS and xCAS to be brought low (until either OE or xCAS is brought high) for the output buffers to go into the low-impedance state. RAS-only refresh A refresh operation must be performed once every 16 ms to retain data. This can be achieved by strobing each of the 1 024 rows (A0 – A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally. xCAS-before-RAS (xCBR) refresh xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive xCBR refresh cycles, xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs, followed by a minimum of eight initialization cycles, is required after power up to the full VDD level. These eight initialization cycles must include at least one refresh (RAS-only or xCBR) cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 absolute maximum ratings over ambient temperature range (unless otherwise noted)† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VDD VSS Supply voltage VIH VIL High-level input voltage 2.4 6.5 V Low-level input voltage (see Note 2) –1 0.8 V Supply voltage 0 V V TA Ambient temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TEST CONDITIONS† PARAMETER VOH High-level output voltage VOL Low-level output voltage II Input current (leakage) IO Output current (leakage) VDD = 5.5 V, xCAS high ICC1‡§ Average read- or write-cycle current VDD = 5.5 V, ICC2 Average standby current IOH = – 5 mA ’418160A - 50 MIN ’418160A - 60 MAX 2.4 IOL = 4.2 mA VDD = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VDD MIN MAX 2.4 ’418160A - 70 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V ± 10 ± 10 ± 10 µA VO = 0 V to VDD, ± 10 ± 10 ± 10 µA Minimum cycle 180 160 150 mA VIH = 2.4 V ( TTL), After one memory cycle, RAS and xCAS high 2 2 2 mA VIH = VDD – 0.2 V (CMOS), After one memory cycle, RAS and xCAS high 1 1 1 mA ICC3§ Average refresh current (RAS-only refresh or xCBR) VDD = 5.5 V, RAS cycling, Minimum cycle, xCAS high (RAS only), RAS low after xCAS low (xCBR) 180 160 150 mA ICC4‡¶ Average page current VDD = 5.5 V, RAS low, 110 90 80 mA tPC = MIN, xCAS cycling † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL ¶ Measured with a maximum of one address change during each page cycle, tPC capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT Ci(A) Input capacitance, A0 – A9 5 pF Ci(OE) Input capacitance, OE 7 pF Ci(RC) Input capacitance, xCAS and RAS 7 pF 7 pF 7 pF Ci(W) Input capacitance, W CO Output capacitance# # LCAS and UCAS = VIH to disable outputs NOTE 3: VDD = 5 V ± 10%, and the bias on pins under test is 0 V. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 4) ’418160A - 50 PARAMETER MIN MAX ’418160A - 60 MIN MAX ’418160A - 70 MIN MAX UNIT tAA tCAC Access time from column address 25 30 35 ns Access time from xCAS 13 15 18 ns tCPA tRAC Access time from xCAS precharge 30 35 40 ns Access time from RAS 50 60 70 ns tOEA tCLZ Access time from OE 18 ns Delay time, xCAS to output in the low-impedance state 0 0 0 ns tOH tOHO Output data hold time from xCAS 3 3 3 ns Output data hold time from OE 3 3 3 tOFF tOEZ Output buffer turn-off delay from xCAS (see Note 5) 0 13 0 15 0 18 ns Output buffer turn-off delay from OE (see Note 5) 0 13 0 15 0 18 ns 13 15 ns NOTES: 4. With ac parameters, it is assumed that tT = 5 ns. 5. tOFF and tOEZ are specified when the output is no longer driven. Data-in should not be enabled until one of the applicable maximum specifications is satsified. ac timing requirements (see Note 4) ’418160A - 50 ’418160A - 60 ’418160A - 70 MIN MIN MIN MAX MAX MAX UNIT tRC tWC Cycle time, read 90 110 130 ns Cycle time, write 90 110 130 ns tRWC tPC Cycle time, read-write 131 155 181 ns Cycle time, page-mode read or write (see Note 6) 35 40 45 ns tPRWC tRASP Cycle time, page-mode read-write 76 85 96 ns Pulse duration, RAS active, page mode (see Note 7) 50 100 000 60 100 000 70 100 000 ns tRAS tCAS Pulse duration, RAS active, nonpage mode (see Note 7) 50 10 000 60 10 000 70 10 000 ns Pulse duration, xCAS active (see Note 8) 13 10 000 15 10 000 18 10 000 ns tRP tWP Pulse duration, RAS (precharge) 30 40 50 ns Pulse duration, write command 10 10 10 ns tASC tASR Setup time, column address 0 0 0 ns Setup time, row address 0 0 0 ns tDS tRCS Setup time, data-in (see Note 9) 0 0 0 ns Setup time, read command 0 0 0 ns tCWL tRWL Setup time, write command before xCAS precharge 13 15 18 ns Setup time, write command before RAS precharge 13 15 18 ns 0 0 0 ns 10 10 10 ns tWCS Setup time, write command before xCAS active (early-write only) tWRP Setup time, write before RAS active (CBR refresh only) NOTES: 4. With ac parameters, it is assumed that tT = 5 ns. 6. To assure tPC min, tASC should be ≥ to tCP . 7. In a read-write cycle, tRWD and tRWL must be observed. 8. In a read-write cycle, tCWD and tCWL must be observed. 9. Referenced to the later of xCAS or W in write operations 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 ac timing requirements (see Note 4) (continued) ’418160A - 50 MIN MAX ’418160A - 60 MIN MAX ’418160A - 70 MIN MAX UNIT tCAH tDH Hold time, column address 10 10 15 ns Hold time, data-in (see Note 9) 10 10 15 ns tRAH tRCH Hold time, row address 8 10 10 ns Hold time, read command referenced to xCAS (see Note 10) 0 0 0 ns tRRH Hold time, read command referenced to RAS (see Note 10) 0 0 0 ns tWCH Hold time, write command during xCAS active (early-write only) 10 10 15 ns tCLCH tRHCP Hold time, xCAS low to xCAS high 5 5 5 ns Hold time, RAS active from xCAS precharge 30 35 40 ns tOEH tROH Hold time, OE command 13 15 18 ns Hold time, RAS referenced to OE 10 10 10 ns tWRH tCP Hold time, write after RAS active (CBR refresh only) 10 10 10 ns 8 10 10 ns Delay time, column address to write command (read-write operation only) 48 55 63 ns tCHR tCRP Delay time, xCAS referenced to RAS (xCBR refresh only) 10 10 10 ns 5 5 5 ns tCSH tCSR Delay time, RAS active to xCAS precharge 50 60 70 ns 5 5 5 ns tCWD tOED Delay time, xCAS to write command (read-write operation only) 36 40 46 ns Delay time, OE to data in 13 15 18 ns tRAD tRAL Delay time, RAS to column address (see Note 11) 13 Delay time, column address to RAS precharge 25 30 35 ns tCAL tRCD Delay time, column address to xCAS precharge 25 30 35 ns Delay time, RAS to xCAS (see Note 11) 18 tRPC tRSH Delay time, RAS precharge to xCAS active 5 5 5 ns Delay time, xCAS active to RAS precharge 13 15 18 ns tRWD Delay time, RAS to write command (read-write operation only) 73 85 98 ns tCPW Delay time, xCAS precharge to write command (read-write operation only) 53 60 68 ns tAWD tREF tT Delay time, xCAS precharge Delay time, xCAS precharge to RAS Setup time, xCAS referenced to RAS (xCBR refresh only) Refresh time interval 37 15 20 16 Transition time NOTES: 4. 9. 10. 11. 25 2 30 30 45 15 20 16 2 30 2 35 52 ns ns 16 ms 30 ns With ac parameters, it is assumed that tT = 5 ns. Referenced to the later of xCAS or W in write operations Either tRRH or tRCH must be satisfied for a read cycle. The maximum value is specified only to assure access time. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION VTH VDD RL R1 Output Under Test Output Under Test R2 CL = 100 pF (see Note A) CL = 100 pF (see Note A) (a) LOAD CIRCUIT (b) ALTERNATE LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance. DEVICE ’418160A VDD ( V ) 5 R1 (Ω ) R2 (Ω ) 828 295 VTH ( V ) 1.31 RL (Ω ) Figure 2. Load Circuits for Timing Parameters 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 218 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tRC tRAS RAS tT tRP tRCD tCAS UCAS tCLCH (see Note A) tCAS LCAS tCP tCRP tCSH tRSH tRAD tRAH tASC tCAL tASR Address tRAL Row Column Don’t Care tRRH tCAH tRCS W tRCH tCAC (see Note B) tAA Don’t Care Don’t Care tOFF tOH tCLZ Valid Data Out DQ0 – DQ15 See Note C tRAC tOHO tROH OE NOTES: A. B. C. D. Don’t Care tOEZ Don’t Care tOEA To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. tCAC is measured from xCAS to its corresponding DQx. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. xCAS order is arbitrary. Figure 3. Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tWC tRAS RAS tT tRP tRCD tCAS UCAS tCLCH (see Note A) LCAS tCP tASR tCRP tCSH tRSH tRAH tASC tCAL Address Row tRAL Column Don’t Care tCAH tCWL (see Note C) tRAD tRWL W Don’t Care Don’t Care tWP tDS DQ0 – DQ15 Don’t Care tDH Don’t Care Valid Data In tOED tOEH Don’t Care OE NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. xCAS order is arbitrary. C. tCWL must be satisfied for each xCAS to write properly to each byte. Figure 4. Write-Cycle Timing 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tWC tRAS RAS tT tRP tRCD tCSH tCRP tCAS UCAS tRSH tCLCH (see Note A) LCAS tRAD tCP tASR tCAS tRAH tASC tCAL tRAL Address (see Note C) (see Note C) W Column Row Don’t Care tCAH tWCS tWCS tWCH (see Note C) tWCH Don’t Care Don’t Care (See Note C) (see Note E) tCWL See Note E tRWL tWP DQ8 – DQ15 Don’t Care Valid Data In Don’t Care tDS (see Note D) tDH DQ0 – DQ7 Don’t Care Valid Data In tDS (see Note D) tDH (see Note D) Don’t Care OE NOTES: A. B. C. D. E. Don’t Care To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. xCAS order is arbitrary. tWCS and tWCH must be satisfied for each xCAS. tDS and tDH of a DQ input are referenced to the corresponding xCAS. tCWL must be satisfied for each xCAS to write properly to each byte. Figure 5. Early-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tRWC tRAS RAS tRP tT tCRP tRCD tCAS tASR xCAS tCP tRAH tCAH tRAD Address tT tASC Row Don’t Care Column tCWL tRCS tRWL tRWD tWP tCAC tCLZ DQ0 – DQ15 tDS tAA tDH Data Out See Note A tRAC tOEA OE Don’t Care tAWD tCWD W tOHO Data In tOEZ Don’t Care tOEH tOED Don’t Care Don’t Care NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Read-Write-Cycle Timing 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tRP tRASP RAS tRCD tCRP tCAS UCAS tRHCP tRSH tCLCH (see Note A) tPC tCSH tCAS tCP tASR LCAS tRAH tCAL tASC tRAL tCAH Address Row Column Don’t Care Column Don’t Care tRAD W tRRH tRCH Don’t Care Don’t Care tCAC (see Note B) tOH tAA tAA tCPA (see Note C) tRCS tRAC tCLZ tOFF See Note D Valid Out DQ8 – DQ15 See Note D tOEZ Valid Out DQ0 – DQ7 Valid Out tOEA tOHO tOHO OE Don’t Care tOEA Don’t Care NOTES: A. B. C. D. E. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. tCAC is measured from xCAS to its corresponding DQx. Access time is tCPA-, tAA-, or tCAC-dependent. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing specifications are not violated. F. xCAS order is arbitrary. Figure 7. Enhanced-Page-Mode Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tRP tRASP RAS tRSH tCAS UCAS tRHCP tPC tCLCH (see Note A) tRCD tCP tCSH LCAS tCRP tCAS tASR tCAH tASC tCAL tRAH Address tRAL Don’t Care Column Row tRAD tCWL tCWL (see Note D) tWP tDS W Don’t Care Column tRWL tDS Don’t Care Don’t Care Don’t Care tDH DQ8 – DQ15 Valid In Don’t Care tDH DQ0 – DQ7 Valid In Valid In Don’t Care tOED OE NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing specifications are not violated. C. xCAS order is arbitrary. D. tCWL must be satisfied for each xCAS to ensure proper writing to each byte. Figure 8. Enhanced-Page-Mode Write-Cycle Timing 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tRP tRASP RAS tRSH tCAS UCAS tRHCP tPC tCLCH (see Note A) tRCD tCP tCSH LCAS tCRP tCAS tASR tCAH tASC tCAL tRAH Address tRAL Don’t Care Column Row tRAD tCWL tCWL (see Note F) tWCS (see Note D) W Don’t Care Column tRWL tWCH (see Note D) Don’t Care Don’t Care Don’t Care tDS (see Note E) DQ8 – DQ15 Don’t Care Valid In tDH (see Note E) DQ0 – DQ7 Valid In Valid In Don’t Care OE NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing specifications are not violated. C. xCAS order is arbitrary. D. tWCS and tWCH must be satisfied for each xCAS. E. tDS and tDH for a DQ is referenced to the corresponding xCAS. F. tCWL must be satisfied for each xCAS. Figure 9. Enhanced-Page-Mode Early Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tRP tRASP RAS tCSH tRCD tRSH tCRP tPRWC tCAS UCAS tCP tCLCH (see Note A) tCAS LCAS tASR tASC tCPW tCAH tRAD Address Row Column Column tCWD tAWD tRAH tWP tCWL tRWL tRWD W tCAC tAA tRCS tDS tAA tRAC tCPA (see Note B) tDH (see Note C) tCLZ Valid In DQ0 – DQ15 Valid Out tOEA tOEH Valid Out Valid In tOEH tOEZ tOED OE NOTES: A. B. C. D. E. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Access time is tCPA-, tAA-, or tCAC-dependent. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. xCAS order is arbitrary. A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are not violated. F. tCAC is measured from xCAS to its corresponding DQx. Figure 10. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tRC tRAS RAS tRP tCRP tT xCAS See Note A Don’t Care tASR Address Don’t Care tRPC tRAH Don’t Care Row Row Don’t Care W Hi-Z DQ0 – DQ15 Don’t Care OE NOTE A: All xCAS must be high. Figure 11. RAS-Only Refresh-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION Refresh Cycle Refresh Cycle Memory Cycle tRP tRP tRAS tRAS RAS tCHR tCAS xCAS tCAH tASC tRAH tASR Address Row Col Don’t Care tWRH tRRH tWRH tWRH tWRP tWRP tRCS tWRP W tRAC tCAC tAA tOFF Valid Data Out DQ0 – DQ15 tCLZ tOEZ tOEA OE Figure 12. Hidden-Refresh-Cycle (Read) Timing 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION Refresh Cycle Memory Cycle Refresh Cycle tRP tRAS tRP tRAS RAS tCHR tCAS xCAS tCAH tASC tRAH tASR Row Address Don’t Care Col tWRH tWCS tWRP tWP W tWCH tDH tDS DQ0 – DQ15 Don’t Care Valid Data Don’t Care OE Figure 13. Hidden-Refresh-Cycle ( Write) Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tRC tRP tRAS RAS tCSR tRPC tCHR tT xCAS tWRP tWRH Don’t Care W Address Don’t Care OE Don’t Care DQ0 – DQ15 Hi-Z NOTE A: Any xCAS can be used. If both LCAS and UCAS are used, both must satisfy tCSR and tCHR. Figure 14. Automatic-xCBR-Refresh-Cycle Timing 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 MECHANICAL DATA DZ (R-PDSO-J42) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE 1.080 (27,43) 1.070 (27,18) 42 22 0.445 (11,30) 0.435 (11,05) 0,405 (10,29) 0.395 (10,03) 1 21 0.032 (0,81) 0.026 (0,66) 0.148 (3,76) 0.128 (3,25) 0.106 (2,69) NOM Seating Plane 0.004 (0,10) 0.020 (0,51) 0.016 (0,41) 0.007 (0,18) M 0.380 (9,65) 0.360 (9,14) 0.008 (0,20) NOM 0.050 (1,27) 4040094-6 / C 4/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125). device symbolization TI -SS Speed ( - 50, - 60, - 70) TMS418160A DZ Package Code W E Y M LLLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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