TI TAS3204

TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
1 Introduction
1.1 Features
•
•
•
•
•
•
•
•
•
High-Quality Audio Performance:
102-dB ADC/105-dB DAC (Typical) DNR
Eight-Channel Programmable Audio DSP
(Four-Channel Digital and Four-Channel
Analog)
Three Differential Stereo Analog Inputs
Multiplexed to Two Stereo Input ADCs
Two Differential Stereo Output DACs
Two Serial Audio Inputs (Four Channels) and
Two Serial Audio Outputs (Four Channels)
135-MHz Maximum Speed, >2800 Processing
Cycles Per Sample at 48 kHz
512×Fs XTAL Input in Master Mode,
512×Fs MCLK_IN in Slave Mode
48-kHz Sample Rate in Master Mode
44.1 or 48-kHz Sample Rate in Slave Mode
•
•
•
•
•
•
•
•
•
•
•
48-Bit Data Path and 28-Bit Coefficients
768 Words of 48-Bit Data Memory
1022 Words of 28-Bit Coefficient Memory
3K Words of 55-Bit Program RAM
Hardware Single-Cycle Multiplier (28×48)
2812 Instructions Per Fs
5.88K Words of 24-Bit Delay Memory
(122.5 ms at 48 kHz)
Data Formats: Left Justified, Right Justified,
and I2S
Two I2C Ports for Slave or Master Download
Single 3.3-V Power Supply
Graphical Development Environment Provided
for Audio Processing; e.g., EQ, Algorithm
Development, Etc.
1.2 Applications
•
•
•
MP3 Docking Systems
Digital Televisions
Mini-Component Audio
TAS3204
SDIN1
SDIN2
Input
SAP
4
2
Differential
Analog
In
2
2
2 Stereo 2
ADC
2 Stereo 2
ADC
MCLK_IN
LRCLK_IN
SCLK_IN
MCLK_OUTx
LRCLK_OUT
SCLK_OUT
I2C Port #1
I2C Port #2
3
PLL
and
Clock
Control
I2C
Interface
Digital Audio
Processor Core
48-Bit Data Path
28-Bit Coefficients
76-Bit MAC
4 Output
SAP
2
3K Code RAM
2
1K Upper Data RAM
768 Lower Data RAM
1.2K Coeff. RAM
Boot ROM
SDOUT1
SDOUT2
Stereo
DAC
2
Stereo
DAC
2
Differential
Analog
Out
Volume
Update
8051 MCU
8-Bit Microprocessor
256 IRAM
2K ERAM
16K Code RAM
10K Code ROM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Contents
1
2
3
4
5
6
7
8
2
Introduction ............................................... 1
8.1
Absolute Maximum Ratings ......................... 37
1.1
Features .............................................. 1
8.2
Package Dissipation Ratings ........................ 37
1.2
Applications ........................................... 1
8.3
Recommended Operating Conditions ............... 37
................................. 3
2.1
Analog Input/MUX/Stereo ADCs ..................... 4
2.2
Stereo DACs .......................................... 4
2.3
Analog Reference System ............................ 4
2.4
Power Supply ......................................... 4
2.5
Clocks, Digital PLL, and Serial Data Interface ....... 4
2.6
I2C Control Interface .................................. 6
2.7
8051 Microcontroller ................................. 6
2.8
Audio Digital Signal Processor Core ................. 6
Physical Characteristics ............................... 7
3.1
Terminal Assignments ................................ 7
3.2
Ordering Information .................................. 7
3.3
Terminal Descriptions ................................ 8
3.4
Reset (RESET) - Power-Up Sequence ............. 10
3.5
Voltage Regulator Enable (VREG_EN) ............. 10
3.6
Power-On Reset (RESET) .......................... 10
3.7
Power Down (PDN) ................................. 10
3.8
I2C Bus Control (CS0) ............................... 11
3.9
Programmable I/O (GPIO) .......................... 11
3.10 Input and Output Serial Audio Ports ................ 12
8.4
Electrical Characteristics ............................ 38
8.5
Audio Specifications ................................. 38
8.6
Timing Characteristics............................... 41
Functional Description
8.6.1
Serial Audio Port, Slave Mode ..................... 42
Serial Audio Port Master Mode Signals
(TAS3204) ........................................... 43
8.6.4 Pin-Related Characteristics of the SDA and SCL
I/O Stages for F/S-Mode I 2C-Bus Devices .......... 44
8.6.6 Reset Timing ........................................ 46
9
Algorithm and Software Development Tools for
TAS3204 .................................................. 18
Clock Controls .......................................... 19
Microprocessor Controller .......................... 21
............
.............................
6.3
I2C Slave Mode Operation ..........................
6.4
I2C Master-Mode Device Initialization ..............
Digital Audio Processor (DAP) Arithmetic Unit .
7.1
DAP Instructions Set ................................
7.2
DAP Data Word Structure ...........................
Electrical Specifications ..............................
6.1
8051 Microprocessor Addressing Mode
22
6.2
General I2C Operations
23
Contents
33
35
10
......................
9.1
Clock Control Register (0x00)
9.2
Microcontroller Clock Control Register .............. 48
9.3
9.4
Status Register (0x02) .............................. 49
I2C Memory Load Control and Data Registers (0x04
and 0x05) ............................................ 50
9.5
Memory Access Registers (0x06 and 0x07)
9.6
9.7
Device Version (0x08) ............................... 52
Analog Power Down Control (0x10 and 0x11),
ESFR (0xE1 and 0xE2) ............................. 52
9.8
Analog Input Control (0x12), ESFR (0xE3)
9.9
9.10
Dynamic Element Matching (0x13), ESFR (0XE4).. 53
Current Control Select (0x14, 0x15, 0x17, 0x18),
ESFR (0xE5, 0xE6, 0xE7, 0xE9) .................... 54
DAC Control (0x1A, 0x1B, 0x1D), ESFR (0xEB,
0xEC, 0xEE)......................................... 58
........
.........
........
9.13 ADC Input Gain Control (0x1F), ESFR (0xFA) ......
9.14 MCLK_OUT Divider (0x21 and 0x22) ...............
9.15 Digital Cross Bar (0x30 to 0x3F) ....................
9.16 Extended Special Function Registers (ESFR) Map .
Application Information ...............................
10.1 Schematics ..........................................
10.2 Recommended Oscillator Circuit ....................
9.12
27
37
I2C Register Map ........................................ 47
9.11
24
34
Master Clock ....................................... 41
8.6.2
8.6.3
ADC and DAC Reset (0x1E), ESFR (0xFB)
48
51
53
60
60
61
61
63
68
68
69
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
2 Functional Description
The TAS3204 is an audio system-on-a-chip (SOC) designed for mini/micro systems, multimedia-speaker,
and MP3 player docking systems. It includes analog interface functions: three multiplex (MUX) stereo
inputs with two stereo analog-to-digital converters (ADCs), two stereo digital-to-analog converters (DACs)
with analog outputs consisting of differential stereo line drivers. Four channels of serial digital audio
processing are also provided. The TAS3204 has a programmable audio digital signal processor (DSP) that
preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle
28×48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM.
The TAS3204 is composed of eight functional blocks:
1. Analog input/mux/stereo ADC
2. Two stereo DACs
3. Analog reference system
4. Power supply
5. Clocks, digital pll, and serial data interface
6. I2C control interface
7. 8051 microcontroller
8. Audio DSP – digital audio processing
512Fs XTAL
DPLL
Oscillator
8051 Microprocessor Core
Master
Master/Slave
External
RAM 2K
MCLK_IN
512Fs
Internal
RAM 256
Slave
Control
Registers
Interface
8-Bit
MCU
SCL2/SDA2
GPIO1/2
Volume
Update
Code
RAM 16K
Clock
SCL1/SDA1
I2C
Control
Divider
LRCLK_IN
Clock
SCLK_IN
Generation
DSP
Control
LRCLK_OUT
SCLK_OUT
Data RAM
Output Cross
Bar Mixer
Data
Path
1K Upper Mem
768 Lower Mem
Code
RAM 3K
256Fs
SDOUT1/2
DSP Core
Coefficient
RAM 1.2K
Serial Audio Port
Input
Cross
Bar
Mixer
SDIN1/2
Memory
Interface
128Fs
Two Stereo
DAC
Three
Differential
Stereo
Two Differential
Stereo Analog
Outputs
Two Stereo
ADC
Power
Supply
Analog Inputs
Legend
Clocks
Digital Data
Analog Data
AVDD
DVDD
Internal Connection
External Connection
Figure 2-1. Expanded Functional Block Diagram
Submit Documentation Feedback
Functional Description
3
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
2.1 Analog Input/MUX/Stereo ADCs
These modules allow three differential analog stereo inputs to be sent to either of two ADCs to be
converted to digital data. The input multiplexers include a preamplifier. This amplifier is driving the ADCs,
and it is digitally controlled with changes synchronized with the sample clock of the ADC. Minimal
crosstalk between selected channels and unselected channels is maintained. When inputs are not needed
they are configured for minimal noise. Also included in this module are two fully differential over sampled
stereo ADCs. The ADCs are sigma-delta modulators with 256 times over-sampling ratio. Because of the
over-sampling nature of the audio ADCs and integrated digital decimation filters, requirements for analog
anti-aliasing filtering are relaxed. Filter performance for the ADCs are specified under physical
characteristics.
2.2 Stereo DACs
This module includes two stereo audio DACs, each of which consists of a digital interpolation filter, digital
sigma-delta modulator and an analog reconstruction filter. Each DAC can operate a maximum of 48 kHz.
Each DAC upsamples the incoming data by 128 and performs interpolation filtering and processing on this
data before conversion to a stereo analog output signal. The sigma-delta modulator always operates at a
rate of 128Fs, which ensures that quantization noise generated within the modulator stays low within the
frequency band below Fs/2.4 at all sample rates. The digital interpolation filters for interpolation from Fs to
8×Fs are included in the audio DSP upper memory (reserved for analog processing), while interpolation
from 8×Fs to 128Fs is done in a dedicated hardware sample and hold filter. The TAS3204 includes two
stereo line driver outputs. All line drivers are capable of driving up to a 10-kΩ load. Each stereo output can
be in power-down mode when not used. Popless operation is achieved by conforming to start and stop
sequences in the device controller code.
2.3 Analog Reference System
This module provides all internal references needed by the analog modules. It also provides bias currents
for all analog blocks. External decoupling capacitors are needed along with an external 1%-tolerance
resistor to set the internal bias currents. It includes a band-gap reference and several voltage buffers and
a tracking current reference. The TAS3204 also uses an internally generated mid supply that is used to
rereference all analog inputs and is present on all analog outputs. VMID is the analog mid supply and can
be used when buffered externally to rereference the analog inputs and outputs. The voltage reference
REXT requires a 22-kΩ 1% resistor to ground. The reference system can be powered down separately.
2.4 Power Supply
The power supply contains supply regulators that provide analog and digital regulated power for various
sections of the TAS3204. Only one external 3.3-V supply is required. All other voltages are generated on
chip from the external 3.3-V supply.
2.5 Clocks, Digital PLL, and Serial Data Interface
These modules provide the timing and serial data interface for the TAS3204. The clocking system for the
device is illustrated in Figure 2-2. The TAS3204 can be either clock master or clock slave depending on
the configuration. However, master mode is the primary mode of operation.
4
Functional Description
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
DPLL
×5.5
135-MHz DCLK
Microprocessor Clock
÷4
MCLK_OUT
÷2
Programmable
Divider
MCLK_OUT2
Programmable
Divider
MCLK_OUT3
From DAP
Parallel
Data
24.576 MHz
512Fs
Crystal
MCLKI
SDIN
Oscillator
÷2
24.576 MHz
256Fs
÷2
128Fs
÷2
64Fs
÷64
Serial
Audio Port
Transmitter
LRCLK
Re-Creation
SDOUT
To DAP
Parallel
Data
Serial
Audio Port
Receiver
LRCLK_OUT
SCLK_OUT
Master/
Slave
Figure 2-2. Clock Generation
DISCLAIMER: Analog performance is not ensured in slave mode, as the analog performance depends
upon the quality of the MCLK_IN. The TAS3204 is not robust with respect to MCLK_IN errors (glitches,
etc.); if the MCLK_IN frequency changes under operation, the device must be reset.
Master mode operation:
• External 512Fs crystal oscillator is used to generate all internal clocks plus all clocks for external
asynchronous sampling rate converter (ASRC) output (if external ASRC is present).
• LRCLK_OUT is fixed at 48 kHz (Fs).
• SCLK_OUT is fixed at 64Fs.
• MCLK_OUT is fixed at 256Fs. In master mode, the external ASRC converts incoming serial audio data
to 48-kHz sample rate synchronous to the internally generated serial audio data clocks.
• In master mode, all clocks generated for the TAS3204 are derived from the 24.576-MHz crystal. The
internal oscillator drives the crystal and generates the main clock to digital PLL (DPLL), master clock
outputs, 256Fs clock to the ADC, and 128Fs clock to the DAC. The DPLL generates internal clocks for
the DAP and the 8051 microprocessor.
Slave mode operation:
• MCLK_IN (512Fs), SCLK_IN (64Fs), and LRCLK_IN (Fs) are supplied externally. Clock generation is
similar to the master mode with the exception of the ADC and the DAC blocks. MCLK_IN signal is
divided down and sent directly to the ADC and the DAC blocks. Therefore, audio performance
depends on the MCLK_IN signal.
• DSP, MCU, and I2C clocks are still derived from external crystal oscillator.
• MCLK_OUT, SCLK_OUT, and LRCLK_OUT are passed through from clock inputs (MCLK_IN,
SCLK_IN, and LRCLK_IN).
• Internal analog clocks for ADC and DACs are derived from external MCLK_IN input, so analog
performance depends on MCLK_IN quality (i.e., jitter, phase noise, etc.). Degradation in analog
performance is to be expected.
• Sample rate change/clock change
Submit Documentation Feedback
Functional Description
5
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
– Sample rate change on the fly should be handled by customer system controller. The TAS3204
device does not include any internal clock error or click/pop detection/management.
– Customer-specific DAP filter coefficients must be uploaded by customer system controller on
changing sample rate.
In slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of 44.1 kHz
or 48 kHz.
2.6 I2C Control Interface
The TAS3204 has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and providing
status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to download
programs and data from external memory such as an EEPROM. See Section 6 for more information. I2C
interface is not 5-V tolerant.
2.7 8051 Microcontroller
The 8051 microcontroller receives and distributes I2C write data. It retrieves and outputs data as
requested from the I2C bus controller. It performs most processing tasks requiring multi-frame processing
cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I2C
commands, a fixed boot program ROM, and a programmable RAM. The microprocessor's boot program
cannot be altered. The microcontroller has specialized hardware for a master and slave interface
operation, volume updates, and a programmable interval-timer interrupt.
2.8 Audio Digital Signal Processor Core
The audio digital signal processor core arithmetic unit is a fixed-point computational engine consisting of
an arithmetic unit and data and coefficient memory blocks. The audio processing structure, which can
include mixers, multiplexers, volume, bass and treble, equalizers, dynamic range compression, or
third-party algorithms, is running in the DAP. The 8051 microcontroller has access to DAP resources such
as coefficient RAM and is able to support the DAP with certain tasks; for example, a volume ramp. The
primary blocks of the audio DSP core are:
• 48-bit data path with 76-bit accumulator
• DSP controller
• Memory interface
• Coefficient RAM (1K×28)
• Data RAM – 24-bit upper memory (1K×24), 48-bit lower memory (768×48)
• Program RAM (3K×55)
The DAP is discussed in detail in the following sections.
6
Functional Description
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
3 Physical Characteristics
3.1 Terminal Assignments
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
I2C2_SCL
I2C2_SDA
RESET
SDIN1/GPIO3
SDIN2/GPIO4
SCLK_IN
LRCLK_IN
DVDD3
DVSS3
VR_DIG
SDO1
SDO2
SCLK_OUT
LRCLK_OUT
RESERVED
VREG_EN
PAG PACKAGE
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MCLK_OUT1
MCLK_OUT2
MCLK_OUT3
DVDD2
DVSS2
MCLK_IN
XTAL_OUT
XTAL_IN
AVDD3
VR_ANA
AVSS_ESD
AVSSO
AOUT1RP
AOUT1RM
AOUT1LP
AOUT1LM
AIN2LM
AIN2RP
AIN2RM
AIN3LP
AIN3LM
AIN3RP
AIN3RM
AVDD1
VMID
VREF
REXT
AVDD2
AOUT2LM
AOUT2LP
AOUT2RM
AOUT2RP
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I2C1_SCL
I2C1_SDA
GPIO2
GPIO1
MUTE
CS0
PDN
DVSS1
DVDD1
VR_PLL
AVSSI
AIN1LP
AIN1LM
AIN1RP
AIN1RM
AIN2LP
3.2 Ordering Information
TA
PLASTIC 64-PIN PQFP (PN)
0°C to 70°C
TAS3204PAG
Submit Documentation Feedback
Physical Characteristics
7
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
3.3 Terminal Descriptions
TERMINAL
(1)
(2)
(3)
8
NAME
NO.
INPUT/
OUTPUT (1)
PULLUP/
PULLDOWN (2)
AIN1LM
13
Analog Input
Pull to VMID (3)
AIN1LP
12
Analog Input
AIN1RM
15
Analog Input
AIN1RP
14
Analog Input
AIN2LM
17
Analog Input
AIN2LP
16
Analog Input
AIN2RM
19
Analog Input
AIN2RP
18
Analog Input
AIN3LM
21
Analog Input
AIN3LP
20
Analog Input
DESCRIPTION
Analog input, channel 1, left, – input
Analog input, channel 1, left, + input
Pull to VMID (3)
Analog input, channel 1, right, – input
Analog input, channel 1, right, + input
Pull to VMID (3)
Analog input, channel 2, left, – input
Analog input, channel 2, left, + input
Pull to
VMID (3)
Analog input, channel 2, right, – input
Analog input, channel 2, right, + input
Pull to VMID (3)
Analog input, channel 3, left, – input
Analog input, channel 3, left, + input
Pull to
VMID (3)
AIN3RM
23
Analog Input
AIN3RP
22
Analog Input
Analog input, channel 3, right, – input
AOUT1LM
33
Analog Output
Analog output, channel 1, left, – output
Analog input, channel 3, right,+ input
AOUT1LP
34
Analog Output
Analog output, channel 1, left, + output
AOUT1RM
35
Analog Output
Analog output, channel 1, right, – output
AOUT1RP
36
Analog Output
Analog output, channel 1, right, + output
AOUT2LM
29
Analog Output
Analog output, channel 2, left, – output
AOUT2LP
30
Analog Output
Analog output, channel 2, left, + output
AOUT2RM
31
Analog Output
Analog output, channel 2, right, – output
AOUT2RP
32
Analog Output
Analog output, channel 2, right,+ output
AVDD1
24
Power
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
AVSS1
11
Power
Analog supply ground
AVDD2
28
Power
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
AVSS2
37
Power
Analog supply ground
AVDD3
40
Power
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
AVSS3
38
Power
Analog supply ground
CS0
6
Digital Input
I2C secondary address
DVDD1
9
Power
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
DVSS1
8
Power
Digital supply ground
DVDD2
45
Power
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
DVSS2
44
Power
Digital supply ground
DVDD3
57
Power
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
DVSS3
56
Power
Digital supply ground
GPIO1
4
Digital IO
General-purpose I/O pin. When booting from internal ROM, the
TAS3204 streams audio when GPIO1 is low; otherwise it mutes.
GPIO2
3
Digital IO
General-purpose I/O pin
I2C1_SCL
1
Digital Input
Slave I2C serial control data interface input/output. Normally connected
to system micro.
I = input; O = output
All pullups are 20-µA weak pullups, and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.
Pull to VMID when analog input is in single-ended mode.
Physical Characteristics
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
TERMINAL
NAME
NO.
INPUT/
OUTPUT (1)
I2C1_SDA
2
Digital I/O
I2C2_SCL
64
Digital Input
I2C2_SDA
63
Digital I/O
LRCLK_IN
58
Digital Input
LRCLK_OUT
51
Digital Output
MCLK_IN
43
Digital Input
MCLK_OUT1
48
Digital Output
12.288 MHz clock output. This output is valid even when reset is LOW.
MCLK_OUT2
47
Digital Output
The frequency for this clock is 6.144 MHz/(n+1) where n is programable
in the range 0 to 255. Default value is 1.024 MHz. This output is valid
even when reset is LOW.
MCLK_OUT3
46
Digital Output
The frequency for this clock is 512 kHz/(n+1) where n is programmable
in the range 0 to 255. Default value is 512 kHz. This output is valid
even when reset is LOW.
MUTE
5
Digital Input
PDN
7
Digital Input
RESERVED
50
N/A
Pulldown
RESET
62
Digital Input
Pullup
REXT
27
Analog Output
SCLK_IN
59
Digital Input
SCLK_OUT
52
Digital Output
SDIN1/GPIO3
61
Digital I/O
Pullup
Serial data input #1 for I2S interface or programmable for GPIO #3
SDIN2/GPIO4
60
Digital I/O
Pullup
Serial data input #2 for I2S interface or programmable for GPIO #4
SDOUT1
54
Digital Output
Serial data output #1 for I2S interface
SDOUT2
53
Digital Output
Serial data output #2 for I2S interface
VMID
25
Analog Output
Analog mid supply reference. This pin must be decoupled with a 0.1-µF
low-ESR capacitor and an external 10-µF filter cap. (4)
VR_ANA
VR_DIG
(4)
39
55
PULLUP/
PULLDOWN (2)
DESCRIPTION
Slave I2C serial clock input. Normally connected to system micro.
Master I2C serial control data interface input/output. Normally
connected to EEPROM.
Master I2C serial clock input. Normally connected to EEPROM.
Pulldown
Serial data input left/right clock for I2S interface
Serial data output left/right clock for I2S interface
Pulldown
Pulldown
MCLK input is used in slave mode. MCLK_IN must be locked to
LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs).
This pin needs to be programmed as mute pin in the application code.
In has no function in default after reset.
Power down, active LOW. After successful boot, its function is defined
by the boot code.
Connect to ground.
System reset input, active low. A system reset is generated by applying
a logic LOW to this terminal.
Requires a 22-kΩ (1%) external resistor to ground to set analog
currents. Trace capacitance must be kept low.
Serial data input bit clock for I2S interface
Serial data output bit clock for I2S interface
Power
Voltage reference for analog supply. A pin-out of the internally
regulated 1.8 V power. A 0.1-µF low ESR capacitor and a 4.7-µF filter
capacitor must be connected between this terminal and AVSS_PLL.
This terminal must not be used to power external devices. (4)
Power
Voltage reference for digital supply. A pin-out of the internally regulated
1.8 V power. A 0.1-µF low ESR capacitor and a 4.7-µF filter capacitor
must be connected between this terminal and DVSS. This terminal
must not be used to power external devices. (4)
Voltage reference for DPLL supply. A pin-out of internally regulated
1.8-V power supply. A 0.1-µF low-ESR capacitor and a 4.7-µF filter
capacitor must be connected between this terminal and DVSS. This
terminal must not be used to power external devices. (4)
VR_PLL
10
Power
VREF
26
Analog Output
VREG_EN
49
Digital Input
Voltage regulator enable. When enabled LOW, this input causes the
power-supply regulators to be enabled.
XTAL_IN
41
Digital Input
Crystal input. A 24.576-MHz (512Fs) crystal should be used.
XTAL_OUT
42
Digital Output
Band gap output. A 0.1-µF low ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used
to power external devices. (4)
Crystal output.
If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling.
Submit Documentation Feedback
Physical Characteristics
9
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
3.4 Reset (RESET) - Power-Up Sequence
The RESET pin is an asynchronous control signal that restores all TAS3204 components to the default
configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051 starts
initialization. A valid XTAL_IN must be present when clearing the RESET pin to initiate a device reset. A
reset can be initiated by applying a logic 0 on RESET.
As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus
operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain
in that state until device initialization has completed.
The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and
setting the default register values. Once these are complete, the TAS3204 enables its master I2C interface
and disables its slave I2C interface.
Using the master interface, the TAS3204 automatically tests to see if an external I2C EEPROM is at
address "1010x". The value x can be chip selects, other information, or don't care, depending on the
EEPROM selected.
If a memory is present and it contains the correct header information and one or more blocks of
program/memory data, the TAS3204 begins to load the program, coefficient and/or data memories from
the external EEPROM. If an external EEPROM is present, the download is considered complete when an
end of program header is read by the TAS3204. At this point, the TAS3204 disables the master I2C
interface, enable the slave I2C interface, and start normal operation. After a successful download, the
micro program counter is reset, and the downloaded micro and DAP application firmware controls
execution.
If no external EEPROM is present or if an error occurs during the EEPROM read, TAS3204 disables the
master I2C interface and enables the slave I2C interface initialization to load the slave default
configuration. In this default configuration, the TAS3204 streams audio from input to output if the GPIO1
pin is asserted LOW; if the GPIO1 pin is asserted HIGH, the ADC and the DAC are muted.
Note: The master and slave interfaces do not operate simultaneously.
3.5 Voltage Regulator Enable (VREG_EN)
Setting the VREG_EN high shuts down all voltage regulators in the device. Internal register settings are
lost in this power down mode. A full power-up/reset/program-load sequence must be completed before the
device is operational.
3.6 Power-On Reset (RESET)
On power up, it is recommended that the TAS3204 RESET be held LOW until DVDD has reached 3.3 V.
This can be done by programming the system controller or by using an external RC delay circuit. The
1-kΩ and 1-µF values provide a delay of approximately 200 µs. The values of R and C can be adjusted to
provide other delay values as necessary.
3.7 Power Down (PDN)
The TAS3204 supports a number of power-down modes.
PDN can be used to put the device into power saving standby mode. PDN is user-firmware definable. Its
default configuration is to stop all clocks, power down all analog circuitry, and ramp down volume for all
digital inputs. This mode is used to minimize power consumption while preserving register settings. If there
is no EEPROM or if the EEPROM has an invalid image–i.e., an unsuccessful boot from the EEPROM–and
PDN is pulled low, the TAS3204 is in powerdown mode. After a successful boot, PDN is defined by the
boot code.
10
Physical Characteristics
Submit Documentation Feedback
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
Individual power down DAC and ADC – Each stereo DAC and ADC can be powered down individually. To
avoid audible artifacts at the outputs, the sequences defined in the TI document TAS3108/TAS3108IA
Firmware Programmer's Guide (SLEU067) must be followed. The control signals for these operations are
defined as ESFR. The feature is made available to the board controller via the I2C interface.
Power down of analog reference – The analog reference can be powered down if all DAC and ADC are
powered down. This operation is handled by the device controller through the ESFRs, and is made
available to the board controller via the I2C interface.
3.8
I2C Bus Control (CS0)
The TAS3204 has a control to specify the slave and master I2C address. This control permits up to two
TAS3204 devices to be placed in a system without external logic. GPIO pins are level sensitive. They are
not edge triggered.
See Section 6.3 for a complete description of this pin.
3.9
Programmable I/O (GPIO)
The TAS3204 has four GPIO pins and two general purpose input pins that are 8051 firmware
programmable.
GPIO1 and GPIO2 pins are single function I/O pins. Upon power up, GPIO1 is an input. If there is an
unsuccessful boot and GPIO1 is pulled high externally, the DAC output is disabled. If there is an
unsuccessful boot and the GPIO1 is pulled low externally, the DAC output is enabled. If there is a
successful boot, GPIO1 is pulled low by the internal microprocessor, and its function is defined by the boot
code in the EEPROM.
GPIO3 and GPIO4 pins are dual function I/O pins. These pins can be used as SDIN1 and SDIN2
respectively.
Mute and power down functions have to be programmed in the EEPROM boot code. These are
general-purpose input pins and can be programmed for functions other than mute and power down.
For more information, see the Texas Instruments document TAS3108/TAS3108IA Firmware Programmer's
Guide (SLEU067).
3.9.1
No EEPROM is Present or a Memory Error Occurs
Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the
TAS3204 is in one of two modes, depending on the setting of GPIO1.
• GPIO1 is logic HIGH
With GPIO1 held HIGH during initialization, the TAS3204 comes up in the default configuration with the
serial data outputs not active. Once the TAS3204 has completed the default initialization procedure,
after the status register is updated and the I2C slave interface is enabled, then GPIO1 is an output and
is driven LOW. Following the HIGH-to-LOW transition of the GPIO pin, the system controller can
access the TAS3204 through the I2C interface and read the status register to determine the load
status.
If a memory-read error occurs, the TAS3204 reports the error in the status register (I2C subaddress
0x02).
• GPIO1 is logic LOW
With GPIO1 held LOW during initialization, the TAS3204 comes up in an I/O test configuration. In this
case, once the TAS3204 completes its default test initialization procedure, the status register is
updated, the I2C slave interface is enabled, and the TAS3204 streams audio unaltered from input to
output as SDIN1 to SDOUT1, SDIN2 to SDOUT2, etc.
Submit Documentation Feedback
Physical Characteristics
11
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
In this configuration, GPIO1 is an output signal that is driven LOW. If the external logic is no longer
driving GPIO1 low after the load has completed (~100 ms following a reset if no EEPROM is present),
the state of GPIO1 can be observed.
Then the system controller can access the TAS3204 through the I2C interface and read the status
register to determine the load status.
If the GPIO1 state is not observed, the only indication that the device has completed its initialization
procedure is the fact that the TAS3204 streams audio and the I2C slave interface has been enabled.
3.9.2
GPIO Pin Function After Device Is Programmed
Once the TAS3204 has been programmed, either through a successful boot load or via slave I2C
download, the operation of GPIO can be programmed to be an input and/or output.
3.10 Input and Output Serial Audio Ports
Serial data is input on SDIN1/SDIN2 on the TAS3204, allowing up to four channels of digital audio input.
The TAS3204 supports serial data in 16-, 20-, or 24-bit data in left, right, and I2S serial data formats. The
parameters for the clock and serial data interface input formats are I2C configurable.
Serial data is output on SDOUT1 and SDOUT2, allowing up to four channels of digital audio output.
SDOUT port supports the same formats as the SDIN port. Output data rate is the same data rate as the
input. The SDOUT output uses the SCLK_OUT and LRCLK_OUT signals to provide synchronization.
The TAS3204 supported data formats are listed in Table 3-1.
Table 3-1. Supported Data Formats
Input SAP (SDIN1, SDIN2)
2-channel
Output SAP (SDOUT1, SDOUT2)
I2S
2-channel I2S
2-channel left-justified
2-channel left-justified
2-channel right-justified
2-channel right-justified
Table 3-2. Serial Data Input and Output Formats
Mode
2-channel
12
Input
Control
IM[3:0]
Output
Control
OM[3:0]
Serial Format
Word Lengths
0000
0000
Left-justified
16, 20, 24
0001
0001
Right-justified
16, 20, 24
0010
0010
I2S
16, 20, 24
Physical Characteristics
Data
Rates
(kHz)
MAX
SCLK
(MHz)
32–48
3.072
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Output Port
Word Size
Input Port
Word Size
Î
Î
Î
Î
15
0x00
31
S
Slave Addr
Ack
Subaddr
Ack
24
xxxxxxxx
23
Ack
14 13
XX
16
xxxxxxxx
11 10
15
Ack
8
IW[2:0] OW[2:0] DWFMT (Data Word Format)
8
7
DWFMT
Ack
7
4
0
IOM
Ack
3
0
IM[3:0]
OM[3:0]
Input Port
Format
Output Port
Format
R0003-01
Figure 3-1. Serial Data Controls
Table 3-3. Serial Data Input and Output Data Word Sizes
IW1, OW1
IW0, OW0
FORMAT
0
0
Reserved
0
1
16-bit data
1
0
20-bit data
1
1
24-bit data
Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass
updates.
Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet
operation. However, care must be taken to ensure that the mute command has completed before the SAP
is commanded to reconfigure. Similarly, the TAS3204 should not be commanded to unmute until after the
SAP has completed a reconfiguration. The reason for this is that an SAP configuration change while a
volume or bass or treble update is taking place can cause the update not to be completed properly.
When the TAS3204 is transmitting serial data, it uses the negative edge of SCLK to output a new data bit.
The TAS3204 samples incoming serial data on the rising edge of SCLK.
Submit Documentation Feedback
Physical Characteristics
13
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
3.10.1 2-Channel I 2S Timing
In 2-channel I2S timing, LRCLK is LOW when left-channel data is transmitted and HIGH when
right-channel data is transmitted. SCLK is a bit clock running at 64 × fS which clocks in each bit of the
data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data
on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS3204 masks unused trailing data-bit positions.
2-Channel I2S (Philips Format) Stereo Input/Output
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-04
Figure 3-2. I2S 64fS Format
14
Physical Characteristics
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
3.10.2 2-Channel Left-Justified Timing
In 2-channel left-justified timing, LRCLK is HIGH when left-channel data is transmitted and LOW when
right-channel data is transmitted. SCLK is a bit clock running at 64 × fS, which clocks in each bit of the
data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written
MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused trailing data-bit
positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
LRCLK
LRCLK
Right Channel
Left Channel
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
Figure 3-3. Left-Justified 64fS Format
Submit Documentation Feedback
Physical Characteristics
15
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
3.10.3 2-Channel Right-Justified Timing
In 2-channel right-justified (RJ) timing, LRCLK is HIGH when left-channel data is transmitted and LOW
when right-channel data is transmitted. SCLK is a bit clock running at 64 × fS which clocks in each bit of
the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK
toggles. In the RJ mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The
data is written MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused
leading data-bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
LRCLK
Right Channel
Left Channel
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 3-4. Right-Justified 64fS Format
3.10.4 SAP Input to SAP Output—Processing Flow
All SAP data format options other than I2S result in a two-sample delay from input to output. If I2S
formatting is used for both the input SAP and the output SAP, the polarity of LRCLK must be inverted.
However, if I2S format conversions are performed between input and output, the delay becomes either 1.5
samples or 2.5 samples, depending on the processing clock frequency selected for the audio DSP core
relative to the sample rate of the incoming data.
The I2S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use
the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core
operate on sample windows that are 180° out of phase with respect to the sample window used by the
output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint
of the sample period used by the audio DSP core to process the data. If the processing cycle completes
all processing tasks before the midpoint of the processing sample period, the output SAP outputs this
processed data. However, if the processing time extends past the midpoint of the processing sample
period, the output SAP outputs the data processed during the previous processing sample period. In the
former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output
is 2.5 samples.
16
Physical Characteristics
Submit Documentation Feedback
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
The delay from input to output can thus be either 1.5 or 2.5 sample times when data format conversions
are performed that involve the I2S format. However, which delay time is obtained for a particular
application is determinable and fixed for that application, providing care is taken in the selection of
MCLK_IN/XTAL_IN with respect to the incoming sample clock, LRCLK.
Submit Documentation Feedback
Physical Characteristics
17
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
4 Algorithm and Software Development Tools for TAS3204
The TAS3204 algorithm and software development tool set is a combination of classical development
tools and graphical development tools. The tool set is used to build, debug, and execute programs in both
the audio DSP and 8051 sections of the TAS3204.
Classical development tooling includes text editors, compilers, assemblers, simulators, and source-level
debuggers. The 8051 can be programmed exclusively in ANSI C.
The 8051 tool set is an off-the-shelf tool set, with modifications as specified in this document. The 8051
tool set is a complete environment with an IDE, editor, compiler, debugger, and simulator.
The audio DSP core is programmed exclusively in assembly. The audio DSP tool set is a complete
environment with an IDE, context-sensitive editor, assembler, and simulator/debugger.
Graphical development tooling provides a means of programming the audio DSP core and 8051 through a
graphical drag-and-drop interface using modular audio software components from a component library.
The graphical tooling produces audio DSP assembly and 8051 ANSI C code as well as coefficients and
data. The classical tools can also be used to produce the executable code.
In addition to building applications, the tool set supports the debug and execution of audio DSP and 8051
code on both simulators and EVM hardware.
18
Algorithm and Software Development Tools for TAS3204
Submit Documentation Feedback
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
5 Clock Controls
Clock management for the TAS3204 consists of two control structures:
• Master clock management
– Oversees the selection of the clock frequencies for the 8051 microprocessor, the I2C controller, and
the audio DSP core
– The master clock (MCLK_IN or XTAL_IN) is the source for these clocks.
– In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the
DPLL output drives the microprocessor and audio DSP clocks.
– Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the
microprocessor and audio DSP clocks.
• Serial audio port (SAP) clock management
– Oversees SAP master/slave mode
– Controls output of SCLKOUT, and LRCLK in the SAP master mode
Input pin MCLK_IN or XTAL_IN provides the master clock for the TAS3204. Within the TAS3204, these
two inputs are combined by an OR gate and, thus, only one of these two sources can be active at any one
time. The source that is not active must be logic 0.
The TAS3204 only supports dynamic sample-rate changes between any of the supported sample
frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the
TAS3204 remains in normal operation and the register contents are preserved. To avoid producing audio
artifacts during the sample-rate changes, a volume or mute control can be included in the application
firmware that mutes the output signal during the sample-rate change. The fixed-frequency clock can be
provided by a crystal attached to XTAL_IN and XTAL_OUT or an external 3.3-V fixed-frequency TTL
source attached to MCLK_IN.
When the TAS3204 is used in a system in which the master clock frequency (fMCLK) can change, the
TAS3204 must be reset during the frequency change. In these cases, the procedure shown in Figure 5-1
should be used.
Submit Documentation Feedback
Clock Controls
19
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Enable Mute and
Wait for Completion
RESET Pin = Low
Change fMCLK
Are
Clocks
Stable?
No
Yes
RESET Pin = High
After
TAS3204
Initializes,
Re-initialize
I2C Registers
Figure 5-1. Master Clock Frequency (fMCLK) Change Procedure
When the serial audio port (SAP) is in the master mode, the SAP uses the XTAL_IN master clock to drive
the serial port clocks SCLK_OUT and LRCLK. When the SAP is in the slave mode, MCLK_IN, SCLK_IN,
and LRCLK_IN are input clocks. SCLK_OUT and LRCLK_OUT are derived from SCLK_IN and
LRCLK_IN, respectively.
See Clock Register (0x00), Section 9.1, for information on programming the clock register.
Table 5-1. TAS3204 MCLK and LRCLK Common Values (MCLK = 24.576 MHz or MCLK = 22.579 MHz)
MCLK/
LRCLK
Ratio
(× fS)
MCLK
Freq
(MHz)
SCLKIN
Rate
(× fS)
FS Sample
Rate (kHz)
Ch Per
SDIN
44.1
2
512
22.579
64
48
2
256
24.576
64
SCLK_IN
Freq
(MHz)
SCLK_OUT
Rate
(× fS)
Ch Per
SDOUT
LRCLK
(FS)
PLL
Multiplier
FDSPCLK
(MHz)
fDSPCLK/fS
2.822
64
2
64
5.5
124.2
2816
3.072
64
2
64
5.5
135.2
2816
N/A
64
2
64
5.5
135.2
2816
Slave Mode, 2 Channels In, 2 Channels Out
Master Mode, 2 Channels In, 2 Channels Out
48
20
2
Clock Controls
256
24.576
N/A
Submit Documentation Feedback
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
6 Microprocessor Controller
The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus
controllers the required I2C read data, and participates in most processing tasks requiring multiframe
processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing
I2C commands, a fixed boot-program ROM, and a program RAM. The microprocessor boot program
cannot be altered. The microprocessor controller has specialized hardware for master and slave interface
operation, volume updates, and a programmable interval timer interrupt. For more information see the
TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
The TAS3204 has a slave-only I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kbps and 400-kbps data-transfer rates for multiple 4-byte write and read operations
(maximum is 20 bytes). The slave I2C control interface is used to program the registers of the device and
to read device status.
The TAS3204 also has a master-only I2C interface that is compatible with the I2C bus protocol and
supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes).
The master I2C interface is used to load program and data from an external I2C EEPROM.
On power up of the TAS3204, the slave interface is disabled and the master interface is enabled.
Following a reset, the TAS3204 disables the slave interface and enables the master interface. Using the
master interface, the TAS3204 automatically tests to see if an I2C EEPROM is at address 1010x. The
value x can be chip select, other information, or don’t cares, depending on the EEPROM selected. If a
memory is present and it contains the correct header information and one or more blocks of
program/memory data, the TAS3204 loads the program, coefficient, and/or data memories from the
EEPROM. If a memory is present, the download is complete when a header is read that has a zero-length
data segment. At this point, the TAS3204 disables the master I2C interface, enables the slave I2C
interface, and starts normal operation.
If no memory is present or if an error occurred during the EEPROM read, TAS3204 disables the master
I2C interface, enables the slave I2C interface, and loads the unprogrammed default configuration. In this
default configuration, the TAS3204 streams audio from input to output if the GPIO pin is LOW. The master
and slave interfaces do not operate simultaneously.
In the slave mode, the I2C bus is used to:
• Load the program and coefficient data
– Microprocessor program memory
– Microprocessor extended memory
– Audio DSP core program memory
– Audio DSP core coefficient memory
– Audio DSP core data memory
• Update coefficient and other control values
• Read status flags
Once the microprocessor program memory has been loaded, it cannot be updated until the TAS3204 has
been reset.
The master and slave modes do not operate simultaneously.
When acting as an I2C master, the data transfer rate is fixed at 375 kHz, assuming MCLK_IN or
XTAL_IN = 24.576 MHz.
When acting as an I2C slave, the data transfer rate is determined by the master device on the bus.
The I2C communication protocol for the I2C slave mode is shown in Figure 6-1.
Submit Documentation Feedback
Microprocessor Controller
21
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Start
(By Master)
Read or Write
(By Master)
Stop
(By Master)
Slave Address
(By Master)
S
0
1
1
0
1
Data Byte
(By Transmitter)
C
S
0
0
R
/
W
A
C
K
M
S
B
Data Byte
(By Transmitter)
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
S
(1)
Acknowledge
(By TAS3204)
MSB
SDA
MSB-1 MSB-2
Acknowledge
(By Receiver)
Acknowledge
(By Receiver)
LSB
SCL
Start Condition
SDA ↓While SCL = 1
Stop Condition
SDA ↑While SCL = 1
Figure 6-1. I2C Slave-Mode Communication Protocol
6.1 8051 Microprocessor Addressing Mode
The 256 bytes of internal data memory address space is accessible using indirect addressing instructions
(including stack operations). However, only the lower 128 bytes are accessible using direct addressing.
The upper 128 bytes of direct address Data Memory space are used to access Extended Special Function
Registers (ESFRs).
6.1.1
Register Banks
There are four directly addressable register banks, only one of which may be selected at one time. The
register banks occupy Internal Data Memory addresses from 00 hex to 1F hex.
6.1.2
Bit Addressing
The 16 bytes of Internal Data Memory that occupy addresses from 20 hex to 2F hex are bit addressable.
SFRs that have addresses of the form 1XXXX000 binary are also bit addressable.
6.1.3
External Data Memory
External data memory occupies a 2K × 8 address space. This space contains the External Special
Function Data Registers (ESFRs). The ESFR permit access and control of the hardware features and
internal interfaces of the TAS3204.
22
Microprocessor Controller
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
6.1.4
Extended Special Function Registers
ESFRs provide signals needed for the M8051 to control the different blocks in the device. ESFR is an
extension to the M8051. Figure 6-2 shows how these registers are arranged.
8051 MCU
Internal
Data
Memory
Bus
DESTIN_DO
DESTIN_A
Address
Decoder
SFRWE
D
Control Out
D
WE
WE
CCLK
CCLK
SFRWA
ESFRDI
Control In
CCLK
Figure 6-2. Extended Special Function Registers
6.1.5
Memory Mapped Registers for DAP Data Memory
The following memory mapped registers are used for communication with the digital audio processor.
Table 6-1. Memory Mapped Registers
Address
Register
Comment
0x0300
Dither Seed
Sets the dither seed value
0x0301
PC Start
Sets the starting address of the
DAP
0x0302
Reserved
Reserved
Note that TAS3204 has the same memory mapped registers distinction of upper and lower memory for
these registers.
6.2 General I2C Operations
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated
circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data are
transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte
transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer
operation begins with the master device driving a start condition on the bus and ends with the master
device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the
clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start,
and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time
of the clock period. The master generates the 7-bit slave address and the read/write (R/W) bit to open
communication with another device and then waits for an acknowledge condition. The slave holds SDA
LOW during acknowledge clock period to indicate an acknowledgement. When this occurs, the master
transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus
R/W bit (one byte). All compatible devices share the same signals via a bidirectional bus using a
wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the
HIGH level for the bus.
Submit Documentation Feedback
Microprocessor Controller
23
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When
the last word transfers, the master generates a stop condition to release the bus. Figure 6-3 shows the
TAS3204 read and write operation sequences.
As shown in Figure 6-3, an I2C read transaction requires that the master device first issue a write
transaction to give the TAS3204 the subaddress to be used in the read transaction that follows. This
subaddress assignment write transaction is then followed by the read transaction. For write transactions,
the subaddress is supplied in the first byte of data written, and this byte is followed by the data to be
written. For I2C write transactions, the subaddress must always be included in the data written. There
cannot be a separate write transaction to supply the subaddress, as was required for read transactions. If
a subaddress-assignment-only write transaction is followed by a second write transaction supplying the
data, erroneous behavior results. The first byte in the second write transaction is interpreted by the
TAS3204 as another subaddress replacing the one previously written.
TAS3204
Subaddress
(By Master)
Data
(By TAS3204)
TAS3204
Address
Data
(By TAS3204)
TAS3204
Address
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
TAS3204
Subaddress
(By Master)
TAS3204
Address
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Figure 6-3. I2C Subaddress Access Protocol
6.3
I2C Slave Mode Operation
The I2C slave mode is the mode that is used to change configuration parameters during operation and to
perform program and coefficient downloads from a master device. The coefficient download operation in
slave mode can be used to replace the I2C master-mode EEPROM download. The TAS3204 supports
both random and sequential I2C transactions. The TAS3204 I2C slave address is 011010xy, where the first
six bits are the TAS3204 device address and bit x is CS0, which is set by the TAS3204 internal
microprocessor at power up. Bit y is the R/W bit. The pulldown resistance of CS0 creates a default 00
address when no connection is made to the pin. Table 6-1 and Table 6-3 show all the legal addresses for
I2C slave and master modes.
The number of data bytes plus the two bytes checksum must be evenly divisible by the word size.
The size field is equal to (header + payload + end checksum).
24
Microprocessor Controller
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
The checksum is contained in the last two data transfer bytes. These are bytes 7 and 8. On single word
transfers (DAP data, DAP instruction), the checksum is always contained in a 8 byte frame that follows the
last data word, last two bytes. For multiword data register transfers data (micro program, micro external
data, and coefficient RAM), the checksum is included in the same byte transfer as data. To meet the
requirement above, the number of words that are transferred contain modulo 8 + 6 in the case of micro
program and data memory, and modulo 2 + 1 in the case of coefficient memory. When the slave I2C
download is used to replace or update sections of micro program, micro data, or DAP coefficient memory,
it is necessary to take these transfer size restrictions into consideration when determining program, data,
and coefficient placements.
The multi word transfers always store first word on the bus at a lower RAM address and increment such
that the last word in the transfer is stored with the highest target RAM address. Consecutive I2C frame
transfers increment target address such that the data in the last transfer is last in target memory address
space.
When the first I2C slave download register is written by the system controlle, the TAS3204 updates the
status register by setting a error bit to indicate an error for the memory type that is being loaded. This
error bit is reset when the operation complete and a valid checksum has been received. For example
when the micro program memory is being loaded, the TAS3204 sets a micro program memory error
indication in the status register at the start of the sequence. When the last byte of the micro program
memory and checksum is received, the TAS3204 clears the micro program memory error indication. This
enables the TAS3204 to preserve any error status indications that occur as a result of incomplete
transfers of data/ checksum error during a series of data and program memory load operations.
The checksum is always contained in the last two bytes of the data block. The I2C slave download is
terminated when a termination header with a zero-length byte-count file is received.
The status register always reflects status of EEPROM boot attempts, unless the user writes to the slave
control register. A write to the slave boot control register causes the EEPROM status register to reflect
slave boot attempt status.
NOTE
Once the micro program memory has been loaded, further updates to this memory are
prohibited until the device is reset. The TAS3204 I2C block does respond to the broadcast
address (00h).
Table 6-2. Slave Addresses
Submit Documentation Feedback
Base Address
CS0
R/W
Slave Address
0110 10
0
0
0x68
0110 10
0
1
0x69
0110 10
1
0
0x6A
0110 10
1
1
0x6B
Microprocessor Controller
25
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 6-3. Master Addresses
Base Address
CS0
R/W
Master Address
1010 00
0
0
0xA0
1010 00
0
1
0xA1
1010 00
1
0
0xA2
1010 00
1
1
0xA3
The following is an example use of the I2C master address to access an external EEPROM. The TAS3204
can address up to two EEPROMs depending on the state of CS0. Initially, the TAS3204 comes up in I2C
master mode. If it finds a memory such as the 24C512 EEPROM, it reads the headers and data as
previously described. In this I2C master mode, the TAS3204 addresses the EEPROMs as shown in
Table 6-4 and Table 6-5.
Table 6-4. EEPROM Address I2C TAS3204 Master Mode = 0xA1/A0
MSB
1
0
1
0
0
A0
(EEPROM)
CS0
R/W
0
0
1/0
Table 6-5. EEPROM Address I2C TAS3204 Master Mode = 0xA3/A2
MSB
1
0
1
0
0
A0
(EEPROM)
CS0
R/W
0
1
1/0
Random I2C Transactions
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. For
random I2C read commands, the TAS3204 responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a given subaddress
does not use all 32 bits, the unused bits are read as logic 0. I2C write commands, however, are treated in
accordance with the data assignment for that address space. If a write command is received for a mixer
subaddress, for example, the TAS3204 expects to see five 32-bit words. If fewer than five data words
have been received when a stop command (or another start command) is received, the data received is
discarded.
Sequential I2C Transactions
The TAS3204 also supports sequential I2C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS3204. For I2C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written to. As was true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data
is discarded.
Sequential read transactions do not have restrictions on outputting only complete subaddress data sets.
If the master does not issue enough data-received acknowledges to receive all the data for a given
subaddress, the master device simply does not receive all the data.
26
Microprocessor Controller
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
If the master device issues more data-received acknowledges than required to receive the data for a given
subaddress, the master device simply receives complete or partial sets of data, depending on how many
data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both
sequential and random, can impose wait states.
6.3.1
Multiple-Byte Write
Multiple data bytes are transmitted by the master device to slave as shown in Figure 6-4. After receiving
each data byte, the TAS3204 responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
2
A5
A4
A1
A3
Subaddress
I C Device Address and
Read/Write Bit
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
Other Data Bytes
First Data Byte
Last Data Byte
Stop
Condition
T0036-02
Figure 6-4. Multiple-Byte Write Transfer
6.3.2
Multiple-Byte Read
Multiple data bytes are transmitted by the TAS3204 to the master device as shown in Figure 6-5. Except
for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A0 ACK
A5
Subaddress
A6
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 6-5. Multiple-Byte Read Transfer
6.4 I2C Master-Mode Device Initialization
I2C master-mode operation is enabled following a reset or power-on reset. Master-mode I2C transactions
do not start until the I2C bus is idle.
The TAS3204 uses the master mode to download from EEPROM the memory contents for the
microprocessor program memory, microprocessor extended memory, audio DSP core program memory,
audio DSP core coefficient memory, and audio DSP core data memory.
The TAS3204, when operating as an I2C master, can execute a complete download of any internal
memory or any section of any internal memory without requiring any wait states.
When the TAS3204 operates as an I2C master, the TAS3204 generates a repeated start without an
intervening stop command while downloading program and memory data from EEPROM. When a
repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to
transfer large blocks of data quickly.
The TAS3204 queries the bus for an I2C EEPROM at address 1010xxx. The value xxx can be chip select,
other information, or don’t cares, depending on the EEPROM selected.
Submit Documentation Feedback
Microprocessor Controller
27
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
The first action of the TAS3204 as master is to transmit a start condition along with the device address of
the I2C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the
address byte, and the TAS3204 sends a subaddress byte, which the EEPROM acknowledges. Most
EEPROMs have at least 2-byte addresses and acknowledge as many as are appropriate. At this point, the
EEPROM sends a last acknowledge and becomes a slave transmitter. The TAS3204 acknowledges each
byte repeatedly to continue reading each data byte that is stored in memory.
The memory load information starts with reading the header and data information that starts at
subaddress 0 of the EEPROM. This information must then be stored in sequential memory addresses with
no intervening gaps. The data blocks are contiguous blocks of data that immediately follow the header
locations.
The TAS3204 memory data can be stored and loaded in (almost) any order. Additionally, this addressing
scheme permits portions of the TAS3204 internal memories to be loaded.
I2C EEPROM Memory Map
Block Header 1
Data Block 1
Block Header 2
Data Block 2
w
w
w
Block Header N
Data Block N
M0040−01
Figure 6-6. EEPROM Address Map
The TAS3204 sequentially reads EEPROM memory and loads its internal memory unless it does not find
a valid memory header block, is not able to read the next memory location because the end of memory
was reached, detects a checksum error, or reads an end-of-program header block. When it encounters an
invalid header or read error, the TAS3204 attempts to read the header or memory location three times
before it determines that it has an error. If the TAS3204 encounters a checksum error it attempts to reread
the entire block of memory two more times before it determines that it has an error.
Once the microprocessor program memory has been loaded, it cannot be reloaded until the TAS3204 has
been reset.
If an error is encountered, TAS3204 terminates its memory-load operation, loads the default configuration,
and disables further master I2C bus operations.
If an end-of-program data block is read, the TAS3204 has completed the initial program load.
28
Microprocessor Controller
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
The I2C master mode uses the starting and ending I2C checksums to verify a proper EEPROM download.
The first 16-bit data word received from the EEPROM, the I2C checksum at subaddress 0x00, is stored
and compared against the 16-bit data word received for the last subaddress, the ending I2C checksum,
and the checksum that is computed during the download. These three values must be equal. If the read
and computed values do not match, the TAS3204 sets the memory read error bits in the status register
and repeats the download from the EEPROM two more times. If the comparison check fails the third time,
the TAS3204 sets the microprocessor program to the default value.
Table 6-6 shows the format of the EEPROM or other external memory load file. Each line of the file is a
byte (in ASCII format). The checksum is the summation of all the bytes (with beginning and ending
checksum fields = 00). The final checksum inserted into the checksum field is the lowest significant four
bytes of the checksum.
Example:
Given the following example 8051 data or program block (must be a multiple of 4 bytes for these blocks):
10h
20h
30h
40h
50h
60h
70h
80h
The checksum = 10h + 20h + 30h + 30h + 40h + 50h + 60h + 70h + 80h = 240h, so
the values put in the checksum fields are MS byte = 02h and LS byte = 40h.
If the checksum is >FFFFh, then the 2-byte checksum field is the least-significant 2 bytes.
For example, if the checksum is 1D 45B6h, the checksum field is MS byte = 45h and LS byte = B6h.
Table 6-6. TAS3204 Memory Block Structures
STARTING
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
12-Byte Header Block
0
Checksum code MS byte
2 bytes
Checksum of bytes 2 through N + 12.
If this is a termination header, this value is 00 00
2 bytes
Must be 0x001F for the TAS3204 to load as part of
initialization. Any other value terminates the initialization
memory load sequence.
Memory to be loaded
1 byte
0x00 – Microprocessor program memory or termination
header
0x01 – Microprocessor external data memory
0x02 – Audio DSP core program memory
0x03 – Audio DSP core coefficient memory
0x04 – Audio DSP core data memory
0x05–06 – Audio DSP upper program memory
0x07 – Audio DSP Upper Coefficient Memory
0x08–FF – Reserved for future expansion
0x00
1 byte
Unused
2 bytes
If this is a termination header, this value is 0000.
Checksum code LS byte
Header ID byte 1 = 0x00
2
4
Header ID byte 2 = 0x1F
5
6
Start TAS3204 memory address MS byte
Start TAS3204 memory address LS byte
Submit Documentation Feedback
Microprocessor Controller
29
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING
BYTE
DATA BLOCK FORMAT
Total number of bytes transferred MS byte
8
Total number of bytes transferred LS byte
SIZE
NOTES
2 bytes
12 + data bytes + last checksum bytes. If this is a
termination header, this value is 0000.
10
0x00
1 bytes
Unused
11
0x00
1 bytes
Unused
Data Block for Microprocessor Program or Data Memory (Following 12-Byte Header)
Data byte 1 (LS byte)
Data byte 2
12
Data byte 3
4 bytes
1–4 microprocessor bytes
4 bytes
5–8 microprocessor bytes
Data byte 4 (MS byte)
Data byte 5
Data byte 6
16
Data byte 7
Data byte 8
•
•
•
Data byte 4×(Z – 1) + 1
N+8
Data byte 4×(Z – 1) + 2
Data byte 4×(Z – 1) + 3
4 bytes
Data byte 4×(Z – 1) + 4 = N
0x00
N + 12
0x00
Checksum code MS byte
4 bytes
Repeated checksum bytes 2 through N + 11
Checksum code LS byte
Data Block for Audio DSP Core Coefficient Memory (Following 12-Byte Header)
Data byte 1 (LS byte)
Data byte 2
12
Data byte 3
Coefficient word 1 (valid data in D27–D0) D7–D0
4 bytes
Data byte 4 (MS byte)
D15–D8
D23–D16
D31–D24
Data byte 5
Data byte 6
16
Data byte 7
4 bytes
Coefficient word 2
4 bytes
Coefficient word Z
4 bytes
Repeated checksum bytes 2 through N + 11
Data byte 8
•
•
•
Data byte 4×(Z – 1) + 1
N+8
Data byte 4×(Z – 1) + 2
Data byte 4×(Z – 1) + 3
Data byte 4×(Z – 1) + 4 = N
0x00
N + 12
0x00
Checksum code MS byte
Checksum code LS byte
30
Microprocessor Controller
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
Data Block for Audio DSP Core Data Memory (Following 12-Byte Header)
Data byte 1 (LS byte)
Data word 1 D7–D0
Data byte 2
Data byte 3
12
Data byte 4
D15–D8
6 bytes
D23–D16
D31–D24
Data byte 5
D39–D32
Data byte 6 (MS byte)
D47–D40
Data byte 7
Data byte 8
Data byte 9
18
Data byte 10
6 bytes
Data 2
6 bytes
Data Z
6 bytes
Repeated checksum bytes 2 through N + 11
Data byte 11
Data byte 12
•
•
•
Data byte 6×(Z – 1) + 1
Data byte 6×(Z – 1) + 2
N+6
Data byte 6×(Z – 1) + 3
Data byte 6×(Z – 1) + 4
Data byte 6×(Z – 1) + 5
Data byte 6×(Z – 1) + 6 = N
0x00
0x00
0x00
N + 12
0x00
Checksum code MS byte
Checksum code LS byte
Data Block for Audio DSP Core Program Memory (Following 12-Byte Header)
Program byte 1 (LS byte)
Program word 1 (valid data in D53–D0) D7–D0
Program byte 2
D15–D8
Program byte 3
12
Program byte 4
D23–D16
7 bytes
D31–D24
Program byte 5
D39–D32
Program byte 6
D47–D40
Program byte 7 (MS byte)
D55–D48
Program byte 8
Program byte 9
Program byte 10
19
Program byte 11
7 bytes
Program word 2
Program byte 12
Program byte 14
Program byte 15
•
•
•
Submit Documentation Feedback
Microprocessor Controller
31
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
Program byte 7×(Z – 1) + 1
Program byte 7×(Z – 1) + 2
Program byte 7×(Z – 1) + 3
N+5
Program byte 7×(Z – 1) + 4
7 bytes
Program word Z
7 bytes
Repeated checksum bytes 2 through N + 11
2 bytes
First 2 bytes of termination block are always 0x0000.
2 bytes
Second 2 bytes are always 0x001F.
Program byte 7×(Z – 1) + 5
Program byte 7×(Z – 1) + 6
Program byte 7×(Z – 1) + 7 = N
0x00
0x00
0x00
N + 12
0x00
0x00
Checksum code MS byte
Checksum code LS byte
20-Byte Termination Block (Last Block of Entire Load Block)
BLAST – 19
BLAST – 17
0x00
0x00
0x00
0x1F
BLAST – 15
0x00
1 byte
BLAST – 14
0x00
1 byte
•
Last 16 bytes must each be 0x00.
•
•
BLAST
32
Microprocessor Controller
0x00
1 byte
Submit Documentation Feedback
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
7 Digital Audio Processor (DAP) Arithmetic Unit
The DAP arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and
coefficient memory blocks. The primary features of the DAP are:
• Two pipe parallel processing architecture
– 48-bit data path with 76-bit accumulator
– Hardware single cycle multiplier (28×48)
– Three 48-bit general-purpose data registers and one 28-bit coefficient register
– Four simultaneous operations per machine cycle
– Shift right, shift left and bi-modal clip
– Log2/Alog2
– Magnitude Truncation
• Hardware acceleration units
– Soft volume controller
– Delay memory
– Dither generator
– log2/2× estimator
• 1024 + 768 dual port ports words of data (24 and 48 bits, respectively)
• 1228 words of coefficient memory (28 bits)
• 3K word of program RAM (55 bits)
• 5.88K words of 24-bits delay memory (1.22 ms)
• Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into
the same memory space for convenient addressing by the microcontroller.
• Memory interface block contains four pointers, two for data memory and two for coefficient memory.
Submit Documentation Feedback
Digital Audio Processor (DAP) Arithmetic Unit
33
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
28
28
Micro
Mem
IF
28
48
28
DATA RAM
COEF RAM
1022 × 48
1022 × 28
28
48
48
28
VOL (5 lsbs)
(EREG4)
48
DI (3 lsbs)
(EREG3)
48
48
LFS
(LFSR)
2
28
48
48
48
28 48
28
48
48
48
48
B
(BREG)
48
L
(CREG)
48
MD
(AREG)
48
48
28
MC
(RREG)
28
Barrel Shift,
NEG, ABS,
or THRU
DLYO
(EREG1)
48
76
ACC
LOG, ALOG,
NEG, ABS,
or THRU
BR
(PREG1)
Multiply
48
76
LR
(PREG2)
MR
PREG3
(PREG3)
“ZERO”
76
48
48
Operand A
76
Legend
76
Register
Operand B
28
ADD
32
76
48
CLIP
Delay RAM
5.8K × 24
DLYI
(DREG9)
76
28-bit data
32-bit data
48-bit data
76-bit data
48
Output Register File (DO1 – DO8)
(DREG1 – DREG8)
32
To Output SAP
Figure 7-1. DSP Core Block Diagram
7.1 DAP Instructions Set
Please see this information in the TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
34
Digital Audio Processor (DAP) Arithmetic Unit
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
7.2 DAP Data Word Structure
Figure 7-2 shows the data word structure of the DAP arithmetic unit. Eight bits of overhead or guard bits
are provided at the upper end of the 48-bit DAP word, and 16 bits of computational precision or noise bits
are provided at the lower end of the 48-bit word. The incoming digital audio words are all positioned with
the most significant bit abutting the 8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all
incoming audio samples are treated as signed data samples The arithmetic engine is a 48-bit (25.23
format) processor consisting of a general-purpose 76-bit arithmetic logic unit and function-specific
arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks) always involve
48-bit DAP words and 28-bit coefficients (usually I2C programmable coefficients). If a group of products is
to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a
DSP-like multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC
operation to maintain precision in the intermediate computational stages.
40 39
47
32 31
24 23 22 21 20 19
16 15
8 7
0
16-Bit Audio
18-Bit Audio
20-Bit Audio
Overhead/
Guard Bits
Precision/Noise Bits
24-Bit Audio
Figure 7-2. Arithmetic Unit Data Word Structure
To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations,
intermediate overflows are permitted, and it is assumed that subsequent terms in the computation flow
correct the overflow condition (see Figure 7-3). The DAP memory banks include a dual port data RAM for
storing intermediate results, a coefficient RAM, and a fixed program ROM. Only the coefficient RAM,
assessable via the I2C bus, is available to the user.
+
+
Rollover
+
1
0
1
1
0
1
1
1
(-73)
1
1
0
0
1
1
0
1
(-51)
1
0
0
0
0
1
0
0
(-124)
-124
1
1
0
1
0
0
1
1
(-45)
+ -45
0
1
0
1
0
1
1
1
(57)
57
0
0
1
1
1
0
1
1
(59)
1
0
0
1
0
0
1
0
(-110)
-73
+
+
-51
59
-110
Figure 7-3. DSP ALU Operation With Intermediate Overflow
Submit Documentation Feedback
Digital Audio Processor (DAP) Arithmetic Unit
35
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
D23 D22 - - - - - D1 D0
Input 24-Bit Data
8-Bit Headroom
and 16-Bit Noise
0...0
D23 D22 - - - - - D1 D0
0...0
47–40
39 - - - - - - 16
15–0
27–23
Coefficient
Representation
Scaling Headroom
Multiplier
Output
75–71
70–63
5
8
22 - - - - - - - - - - - - - - - 0
Data (24 bits)
62
–
Fractional Noise
39
12
38–31
12
30 – 0
8
31
48-Bit Clipping
POS48 –
NEG48 –
0x7F_F
0x80_0
POS40 –
NEG40 –
0xXX_
0xXX_
FFF_FFFF
000_0000
_FF
_00
32-Bit Clipping
7FFF_FFFF
8000_0000
_XX
_XX
28-Bit Clipping
POS20 –
NEG20 –
0xXXXXX_
0xXXXXX_
7FFF_FFFF
8000_0000
Figure 7-4. DAP Data-Path Data Representation
36
Digital Audio Processor (DAP) Arithmetic Unit
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
8 Electrical Specifications
8.1 Absolute Maximum Ratings (1)
over operating temperature range (unless otherwise noted)
DVDD
Digital supply voltage range
AVDD
Analog supply voltage range
VI
Input voltage range
–0.5 V to 3.8 V
–0.5 V to 3.8 V
3.3-V TTL
–0.5 V to DVDD + 0.5 V
1.8 V LVCMOS (XTLI)
–0.5 V to 2.3 V
3.3 V TTL
–0.5 V to DVDD + 0.5 V
VO
Output voltage range
IIK
Input clamp current (VI < 0 or VI > DVDD)
±20 µA
IOK
Output clamp current (VO < 0 or VO > DVDD)
±20 µA
TA
Operating free-air temperature range
Tstg
Storage temperature range
(1)
–0.5 V to 2.3 V (2)
1.8 V LVCMOS (XTLO)
0°C to 70°C
–65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Pin XTAL_OUT is the only TAS3204 output that is derived from the internal 1.8-V logic supply. The absolute maximum rating listed is for
reference; only a crystal should be connected to XTAL_OUT.
Note:
• VR_ANA is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices.
• VR_DIG is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices.
• VR_PLL is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices.
(2)
8.2 Package Dissipation Ratings
Package Description
Package Type
Pin Count
Package
Designator
TQFP
64
PAG
TA ≤ 25°C
Power Rating
(mW)
Derating Factor
Above TA = 25°C
(mW/°C)
TA = 70°C
Power Rating
(mW)
1869
23.36
818
8.3 Recommended Operating Conditions
MIN
NOM
MAX
DVDD Digital supply voltage
3
3.3
3.6
V
AVDD Analog supply voltage
3
3.3
3.6
V
3.3 V TTL
2
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating ambient air temperature
0
TJ
Operating junction temperature
0
1.8 V LVCMOS (XTL_IN)
Analog output load
Submit Documentation Feedback
V
1.2
3.3 V TTL
0.8
1.8 V LVCMOS (XTL_IN)
0.5
Analog differential input
Resistance
Capacitance
UNIT
25
70
105
V
°C
°C
2
VRMS
10
kΩ
100
pF
Electrical Specifications
37
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
8.4 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
3.3-V TTL
IOH = –4 mA
1.8-V LVCMOS
(XTL_OUT)
IOH = –0.55 mA
MIN
TYP
MAX
UNIT
2.4
VOH
High-level output voltage
V
3.3-V TTL
IOL = 4 mA
0.5
VOL
Low-level output voltage
1.8-V LVCMOS
(XTL_OUT)
IOL = 0.75 mA
0.4
IOZ
High-impedance output current
3.3-V TTL
VI = VIL
±20
3.3-V TTL
VI = VIL
±20
1.8-V LVCMOS
(XTL_IN)
VI = VIL
±20
1.44
V
µA
µA
IIL
Low-level input current
3.3-V TTL
VI = VIH
±20
IIH
High-level input current
1.8-V LVCMOS
(XTL_IN)
VI = VIH
±20
IDVDD
Digital supply current
Normal operation
MCLK_IN = 24.576 MHz,
LRCLK = 48 kHz
130
mA
IAVDD
Analog supply current
Normal operation
MCLK_IN = 24.576 MHz,
LRCLK = 48 kHz
60
mA
Normal operation
MCLK_IN = 24.576 MHz,
LRCLK = 48 kHz
627
mW
With voltage regulators on
23
mW
With voltage regulators off
825
µW
µA
Power
Dissipation
(Total)
Digital and analog supply current
VR_ANA
Internal voltage regulator – analog
1.6
1.8
1.98
V
VR_PLL
Internal voltage regulator – PLL
1.6
1.8
1.98
V
VR_DIG
Internal voltage regulator – digital
1.6
1.8
1.98
V
Standby mode
Reset mode
20
mW
8.5 Audio Specifications
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs = 48 kHz, 1-kHz sine wave full scale, over operating free-air temperature range
(unless otherwise noted)
PARAMETER
Overall performance:
input ADC – DAP –
DAC – line out
ADC section
TYP
MAX
UNIT
100
dB
THD+N
Evaluation module. –3 dB with
respect to full scale
101
dB
Dynamic range
A-weighted, –60 dB with respect to
full scale.
102
dB
THD+N
–4 dB with respect to full scale.
93
dB
Crosstalk
One channel = –3 dB;
Other channel = 0 V
84
dB
Power supply rejection ratio
1 kHz, 100 mVpp on AVDD
57
dB
20
kΩ
Input capacitance
10
pF
0.45Fs
Hz
Pass band ripple
±0.01
dB
Stop band edge
0.55Fs
Hz
100
dB
37÷Fs
Sec
Pass band edge
Stop band attenuation
Group delay
38
MIN
Dynamic range
Input resistance
ADC decimation filter
TEST CONDITIONS
Evaluation module. A-weighted,
–60 dB with respect to full scale
Electrical Specifications
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Audio Specifications (continued)
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs = 48 kHz, 1-kHz sine wave full scale, over operating free-air temperature range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Differential full scale output
voltage
TYP
MAX
2
Dynamic range
A-weighted, –60 dB with respect to
full scale
THD+N
UNIT
VRMS
105
dB
0-dBFS input, 0-dB gain
95
dB
DAC to ADC
One channel –3 dBFS;
Other channel 0 V
84
dB
ADC to DAC
One channel –3 dB;
Other channel 0 V
84
dB
DAC to DAC
One channel –3 dBFS;
Other channel 0 V
84
dB
Power supply rejection ratio
1 kHz, 100 mVpp on AVDD
56
dB
DC offset
With respect to VREF
DAC section
Crosstalk
DAC interpolation filter
MIN
mV
Pass band edge
0.45Fs
Hz
Pass band ripple
±0.06
dB
Transition band
1.45 Fs to
0.55Fs
Hz
Stop band edge
7.4Fs
Hz
-65
dB
21÷Fs
Sec
Stop band attenuation
Filter group delay
Figure 8-1. Frequency Response (ADC-DAC)
Submit Documentation Feedback
Electrical Specifications
39
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Figure 8-2. THD+N (ADC-DAC)
40
Electrical Specifications
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
8.6 Timing Characteristics
The following sections describe the timing characteristics of the TAS3204.
8.6.1
Master Clock
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
f(XTAL_IN)
Frequency, XTAL_IN (1/ tc(1))
tc(1)
Cycle time, XTAL_IN
f(MCLK_IN)
Frequency, MCLK_IN (1/ tc(2))
tw(MCLK_IN)
Pulse duration, MCLK_IN high
See
MIN
(1)
TYP
MAX
512Fs
Hz
1÷512Fs
Sec
512Fs
See
(2)
0.4 tc(2)
UNIT
0.5 tc(2)
Crystal frequency deviation
Hz
0.6 tc(2)
50
ppm
f(MCLKO)
Frequency, MCLKO (1/ tc(3))
tr(MCLKO)
Rise time, MCLKO
CL = 30 pF
15
ns
tf(MCLKO)
Fall time, MCLKO
CL = 30 pF
15
ns
tw(MCLK_IN)
Pulse duration, MCLKO high
(1)
(2)
(3)
(4)
(5)
(6)
See
(3)
XTAL_IN master clock
source
MCLKO jitter
td(MI-MO)
256Fs
ns
MCLK_IN master clock
source
Delay time, MCLK_IN rising
edge to MCLKO rising edge
Hz
HMCLKO
ns
80
ps
See
(4)
MCLKO = MCLK_IN
See
(5)
20
ns
MCLKO < MCLK_IN
See
(5) (6)
20
ns
ps
Duty cycle is 50/50.
Period of MCLK_IN = TMCLK_IN = 1/fMCLK_IN
HMCLKO = 1/(2 × MCLKO). MCLKO has the same duty cycle as MCLK_IN when MCLKO = MCLK_IN. When MCLKO = 0.5 MCLK_IN or
0.25 MCLK_IN, the duty cycle of MCLKO is typically 50%.
When MCLKO is derived from MCLK_IN, MCLKO jitter = MCLK_IN jitter
Only applies when MCLK_IN is selected as master source clock
Also applies to MCLKO falling edge when MCLKO = MCLK_IN/2 or MCLK_IN/4
XTALI
tc(1)
tw(MCLKI)
MCLKI
tc(2)
td(MI-MO)
tw(MCLKO)
tf(MCLKO)
tr(MCLKO)
MCLKO
tc(3)
T0088-01
Figure 8-3. Master Clock Signal Timing Waveforms
Submit Documentation Feedback
Electrical Specifications
41
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
8.6.2
Serial Audio Port, Slave Mode
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
fLRCLK
Frequency, LRCLK (fS)
tw(SCLKIN)
Pulse duration, SCLKIN high
fSCLKIN
Frequency, SCLKIN
tpd1
Propagation delay, SCLKIN falling edge to
SDOUT
tsu1
Setup time, LRCLK to SCLKIN rising edge
th1
Hold time, LRCLK from SCLKIN rising edge
tsu2
Setup time, SDIN to SCLKIN rising edge
th2
Hold time, SDIN from SCLKIN rising edge
tpd2
Propagation delay, SCLKIN falling edge to
SCLKOUT2 falling edge
(1)
(2)
See
(1)
See
(2)
MIN
TYP
MAX
UNIT
48
kHz
0.4 tc(SCLKIN)
0.5 tc(SCLKIN)
0.6 tc(SCLKIN)
64 FS
ns
MHz
16
ns
10
ns
5
ns
10
ns
5
ns
15
ns
Period of SCLKIN = TSCLKIN = 1/fSCLKIN
Duty cycle is 50/50.
tw(SCLKIN)
tc(SCLKIN)
SCLKIN
th1
tsu1
LRCLK
(Input)
tpd1
SDOUT1
SDOUT2
SDOUT3
SDOUT4
th2
tsu2
SDIN1
SDIN2
SDIN3
SDIN4
tpd2
SCLKOUT2
T0090-01
Figure 8-4. Serial Audio Port Slave Mode Timing Waveforms
42
Electrical Specifications
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
8.6.3
Serial Audio Port Master Mode Signals (TAS3204)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
tr(LRCLK)
Rise time, LRCLK
tf(LRCLK)
Fall time, LRCLK
f(SCLKOUT)
Frequency, SCLKOUT
CL = 30 pF
tr(SCLKOUT)
Rise time, SCLKOUT
CL = 30 pF
12
ns
tf(SCLKOUT)
Fall time, SCLKOUT
CL = 30 pF
12
ns
tpd1(SCLKOUT)
Propagation delay, SCLKOUT falling edge to LRCLK edge
5
ns
tpd2
Propagation delay, SCLKOUT falling edge to SDOUT1-2
5
ns
tsu
Setup time, SDIN to SCLKOUT rising edge
25
ns
Hold time, SDIN from SCLKOUT rising edge
30
ns
th
(1)
(1)
48
UNIT
Frequency LRCLK
(1)
CL = 30 pF
TYP
f(LRCLK)
kHz
CL = 30 pF
12
ns
Duty cycle is 50/50
12
ns
64FS
MHz
Rise time and fall time measured from 20% to 80% of maximum height of waveform.
tr(SCLKOUT)
tf(SCLKOUT)
SCLKOUT2
tr(SCLKOUT)
tf(SCLKOUT)
tsk
SCLKOUT1
tpd1(SCLKOUT2)
tpd1(SCLKOUT1)
LRCLK
(Output)
tf(LRCLK), tr(LRCLK)
tpd2
SDOUT1
SDOUT2
SDOUT3
SDOUT4
th
tsu
SDIN1
SDIN2
SDIN3
SDIN4
T0091-01
Figure 8-5. Serial Audio Port Master Mode Timing Waveforms
Submit Documentation Feedback
Electrical Specifications
43
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
8.6.4 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices
PARAMETER
TEST CONDITIONS
STANDARD MODE
MAX
MIN
MAX
0.8
–0.5
0.8
VIL
LOW-level input voltage
–0.5
VIH
HIGH-level input voltage
2
Vhys
Hysteresis of inputs
VOL1
LOW-level output voltage (open drain or
open collector)
3-mA sink current
tof
Output fall time from VIHmin to VILmax
Bus capacitance from 10 pF
to 400 pF
II
Input current, each I/O pin
–10
tSP(SCL)
SCL pulse duration of spikes that must
be suppressed by the input filter
tSP(SDA)
SDA pulse duration of spikes that must
be suppressed by the input filter
CI
Capacitance, each I/O pin
(1)
(2)
(3)
FAST MODE
MIN
N/A
N/A
UNIT
V
2
V
0.05 VDD
V
0
0.4
V
250 7 + 0.1 Cb (1)
250
ns
10
–10 (2)
10 (2)
µA
N/A
N/A
14 (3)
ns
N/A
N/A
22 (3)
ns
10
10
pF
I2C
Cb = capacitance of one bus line in pF. The output fall time is faster than the standard
specification.
The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off.
These values are valid at the 135-MHz DSP clock rate. If DSP clock is reduced by half, the tSP doubles.
all values are referred to VIHmin and VILmax (see Section 8.6.4)
PARAMETER
STANDARD MODE
MIN
MAX
MAX
400 (1)
SCL clock frequency
0
tHD-STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
4
0.6
µs
tLOW
LOW period of the SCL clock
4.7
1.3
µs
tHIGH
HIGH period of the SCL clock
4
0.6
µs
tSU-STA
Setup time for repeated START
4.7
0.6
µs
tSU-DAT
Data setup time
250
100
µs
kHz
3.45
0
0.9
µs
1000
20 + 0.1 Cb (4)
300
ns
300
20 + 0.1 Cb (4)
300
ns
tHD-DAT
Data hold time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL
tSU-STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and START condition
Cb
Capacitive load for each bus line
VnL
Noise margin at the LOW level for each connected device
(including hysteresis)
0.1VDVDD
0.1VDVDD
V
VnH
Noise margin at the HIGH level for each connected device
(including hysteresis)
0.2VDVDD
0.2VDVDD
V
(1)
(2)
(3)
(4)
44
0
0
UNIT
fSCL
(2) (3)
100
FAST MODE
MIN
4
0.6
4.7
1.3
400
µs
µs
400
pF
In master mode, the maximum speed is 375 kHz.
Note that SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges
of SCL. TI recommends that a 2-kΩ pullup resistor be used to avoid potential timing issues.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the
standard-mode I2C bus specification) before the SCL line is released.
Cb = total capacitance of one bus line in pF
Electrical Specifications
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
NOTE
SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be
valid by the rising and falling edges of SCL.
SDA
tf
tSU-DAT
tHD-STA
tLOW
tr
tSP
tr
tBUF
tf
SCL
tHD-DAT
tSU-STA
tHD-STA
tSU-STO
tHIGH
S
Sr
P
S
T0114-01
Figure 8-6. Start and Stop Conditions Timing Waveforms
8.6.5.1 Recommended I2C Pullup Resistors
It is recommended that the I2C pullup resistors RP be 4.7 kΩ (see Figure 8-7). If a series resistor is in the
circuit (see Figure 8-8), then the series resistor RS should be less than or equal to 300 Ω.
DVDD
TAS3204
External
Microcontroller
IP
RP
SDA
SCL
IP
RP
VI(SDA)
VI(SCL)
Figure 8-7. I2C Pullup Circuit (With No Series Resistor)
DVDD
TAS3204
External
Microcontroller
RP
SDA
or
SCL
VI
RS
IP
(2)
VS
RS
(2)
(1)
(1)
VS = DVDD × RS/(RS – RP). When driven low, VS << VIL requirements.
(2)
RS ≤ 300 Ω
Figure 8-8. I2C Pullup Circuit (With Series Resistor)
Submit Documentation Feedback
Electrical Specifications
45
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
8.6.6 Reset Timing
control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(RESET)
Pulse duration, RESET active
tr(DMSTATE)
Time to outputs inactive
tr(run)
Time to enable I2C
MIN
MAX
UNIT
100
µs
200
50
ns
ms
RESET
tw(RESET)
Internal Reset
Initialization Complete
tr(run)
tr(DMSTATE)
2
Time to enable I C
Figure 8-9. Reset Timing
46
Electrical Specifications
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9 I2C Register Map
I2C registers are also mapped to some of the Extended Special Function Registers (ESFR). They are
defined in the following sections.
Table 9-1. I2C Register Map
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
CONTENTS
INITIALIZATION
VALUE
0x00
Clock and SAP Control Register
4
Description shown in Section 9.1
0x00, 0x40, 0x1B, 0x22
0x01
Reserved
4
Reserved
0x00, 0x00, 0x00, 0x40
0x02
Status Register
4
Description shown in Section 9.3
0x00, 0x00, 0x03, 0xFF
0x03
Unused
0x04
I2C Memory Load Control
8
Description shown in Section 9.4
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x05
I2C Memory Load Data
8
Description shown in Section 9.4
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x06
Memory Select and Address
4
u(31:24) (1), MemSelect(23:16),
Addr(15:8), Addr(7:0)
0x00, 0x00, 0x00, 0x00
0x07
Data Register
16
D(63:56), D(55:48), D(47:40),
D(39:32), D(31:24), D(23:16),
D(15:8), D(7:0)
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x08
Device Version
4
TAS3204 version
0x00, 0x00, 0x00, 0x01
0x09
Unused
Unused
Unused
Unused
0x10
Analog Power Down Control 1
4
Analog Power Down Control 1
0x00, 0x00, 0x00, 0x1F
0x11
Analog Power Down Control 2
4
Analog Power Down Control 2
0x00, 0x00, 0x00, 0xFF
0x12
Analog Input Control
4
Analog Input Control
0x00, 0x00, 0x00, 0x01
0x13
ADC Dynamic Element Matching
4
ADC Dynamic Element Matching
0x00, 0x00, 0x00, 0x08
0x14
ADC2 Current Control 1
4
ADC1 Current Control 1
0x00, 0x00, 0x00, 0x00
0x15
ADC2 Current Control 2
4
ADC1 Current Control 2
0x00, 0x00, 0x00, 0x00
0x16
Unused
0x17
ADC1 Current Control 1
4
ADC2 Current Control 1
0x00, 0x00, 0x00, 0x00
0x18
ADC1 Current Control 2
4
ADC2 Current Control 2
0x00, 0x00, 0x00, 0x00
0x19
Unused
4
Unused
0x1A
DAC Control 1
4
DAC Control 1
0x00, 0x00, 0x00, 0x00
0x1B
DAC Control 2
4
DAC Control 2
0x00, 0x00, 0x00, 0x00
0x1C
Analog Test Modes
4
Analog Test Modes
0x00, 0x00, 0x00, 0x00
0x1D
DAC Modulator Dither
4
DAC Modulator Dither
0x00, 0x00, 0x00, 0x00
0x1E
ADC/DAC Digital Reset
4
0x1F
Analog Input Gain Select
0x20
Clock Delay Setting ADC
0x21
0x22
(1)
0x00, 0x00, 0x00, 0x00
Unused
ADC/DAC Digital Reset
0x00, 0x00, 0x00, 0x00
Analog Input Gain Select
0x00, 0x00, 0x00, 0x00
4
Clock Delay Setting ADC
0x00, 0x00, 0x00, 0x00
MCLK_OUT2 Divider
4
MCLK_OUT2 Divider
0x00, 0x00, 0x00, 0x05
MCLK_OUT3 Divider
4
MCLK_OUT3 Divider
0x00, 0x00, 0x00, 0x00
0x23
Bypass Time
4
Bypass Time
0x00, 0x00, 0x00, 0x00
0x24
Clock Delay Setting DAC
4
Clock Delay Setting DAC
0x00, 0x00, 0x00, 0x00
0x30–0x3F
Digital Cross Bar
32
Digital Cross Bar
See Section 9.15
u indicates unused bits.
In the following sections, BOLD indicates the default state of the bit fields.
Submit Documentation Feedback
I2C Register Map
47
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.1 Clock Control Register (0x00)
Register 0x00 provides the user with control over MCLK, LRCLK, SCLKOUT1, SCLKOUT2, data-word
size, and serial audio port modes. Register 0x00 default = 0x00 00 1B 22.
Table 9-2. Clock Control Register (0x00)
D31
D30
D29
D28
D27
D26
D25
D24
–
–
–
–
–
–
–
–
D23
D22
D21
D20
D19
D18
D17
D16
–
1
–
–
–
–
–
–
Master Mode (XTAL)
–
0
–
–
–
–
–
–
Slave mode (MCLK_IN)
D15
D14
D13
D12
D11
D10
D9
D8
–
–
–
–
–
–
0
0
Output SAP 32 bit word
–
–
–
–
–
–
0
1
Output SAP 16 bit word
–
–
–
–
–
–
1
0
Output SAP 20 bit word
–
–
–
–
–
–
1
1
Output SAP 24 bit word
–
–
–
0
0
–
–
–
Input SAP 32 bit word
–
–
–
0
1
–
–
–
Input SAP 16 bit word
–
–
–
1
0
–
–
–
Input SAP 20 bit word
–
–
–
1
1
–
–
–
Input SAP 24 bit word
D3
D2
D1
D0
D7
D6
D5
D4
IM3
IM2
IM1
IM0
DESCRIPTION
Firmware definable
DESCRIPTION
DESCRIPTION
DESCRIPTION
Input data format
OM3
OM2
OM1
OM0
Output data format
9.2 Microcontroller Clock Control Register
This register is reserved.
48
I2C Register Map
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.3 Status Register (0x02)
During I2C download, the write operation to indicate that a particular memory is to be written causes the
TAS3204 to set an error bit to indicate a load for that memory type. This error bit is cleared when the
operation completes successfully.
Table 9-3. Status Register (0x02)
D31
D30
D29
D28
D27
D26
D25
D24
–
–
–
–
–
–
–
–
D23
D22
D21
D20
D19
D18
D17
D16
–
–
–
–
–
–
–
–
D15
D14
D13
D12
D11
D10
D9
D8
–
–
–
–
–
–
–
–
D7
D6
D5
D4
D3
D2
D1
D0
0
0
–
–
–
–
–
1
Microprocessor program memory load error
0
0
–
–
–
–
1
–
Microprocessor external data memory load error
0
0
–
–
–
1
–
–
Audio DSP core program memory load error
0
0
–
–
1
–
–
–
Audio DSP core upper coefficient memory load error
0
0
–
1
–
–
–
–
Audio DSP core upper data memory load error
0
0
1
–
–
–
–
–
Invalid memory select
1
1
1
1
0
0
0
0
End-of-load header error
1
1
1
1
1
1
1
1
N, IC sampling clock is 33 MHz divided by 2N
0
0
0
0
0
0
0
0
No errors
Submit Documentation Feedback
DESCRIPTION
Firmware definable
DESCRIPTION
Firmware definable
DESCRIPTION
Firmware definable
DESCRIPTION
I2C Register Map
49
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.4 I2C Memory Load Control and Data Registers (0x04 and 0x05)
Registers 0x04 (Table 9-4) and 0x05 (Table 9-5) allow the user to download TAS3204 program code and
data directly from the system I2C controller. This mode is called the I2C slave mode (from the TAS3204
point of view). See the TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details.
The I2C slave memory load port permits the system controller to load the TAS3204 memories as an
alternative to having the TAS3204 load its memory from EEPROM.
• Micro program memory
• Micro extended memory
• DAP program memory
• DAP coefficient memory
• DAP data memory
The transfer is performed by writing to two I2C registers. The first register is a eight byte register that holds
the checksum, the memory to be written, the starting address, the number of data bytes to be transferred.
The second location holds 8 bytes of data. The memory load operation starts with the first register being
set. Then the data is written into the second register using the format shown. After the last data byte is
written into the second register, an additional two bytes are written which contain the two-byte checksum.
At that point, the transfer is complete and status of the operation is reported in the status register. The end
checksum is always contained in the last two bytes of the data block.
Table 9-4. TAS3204 Memory Load Control Register (0x04)
BYTE
DATA BLOCK FORMAT
1–2
SIZE
Checksum code
3-4
Memory to be loaded
NOTES
2 bytes
Checksum of bytes 2 through N + 8. If this is a termination header,
this value is 00 00.
2 bytes
0: Microprocessor program memory
1: Microprocessor external data memory
2: Audio DSP core program memory
3: Audio DSP core coefficient memory
4: Audio DSP core data memory
5: Audio DSP core upper data memory
6: Audio DSP core upper coefficient memory
7–15: Reserved for future expansion
5
Unused
1 byte
Reserved for future expansion
6–7
Starting TAS3204 memory address
2 bytes
If this is a termination header, this value is 0000.
7–8
Number of data bytes to be transferred
2 bytes
If this is a termination header, this value is 0000.
Table 9-5. TAS3204 Memory Load Data Register (0x05)
50
BYTE
8-BIT DATA
28-BIT DATA
48-BIT DATA
1
Datum 1 D7–D0
0000 D27–D24
0000 0000
0000 0000
2
Datum 2 D7–D0
D7–D0
0000 0000
00 D53–D48
3
Datum 3 D7–D0
D15–D8
D47–D40
D47–D40
4
Datum 4 D7–D0
D7–D0
D39–D32
D39–D32
5
Datum 5 D7–D0
0000 D27–D24
D31–D24
D31–D24
6
Datum 6 D7–D0
D23–D16
D23–D16
D23–D16
7
Datum 7 D7–D0
D15–D8
D15–D8
D15–D8
8
Datum 8 D7–D0
D7–D0
D7–D0
D7–D0
I2C Register Map
54-BIT DATA
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.5 Memory Access Registers (0x06 and 0x07)
Registers 0x06 (Table 9-6) and 0x07 (Table 9-7) allow the user to access the internal resources of the
TAS3204. See TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details.
Table 9-6. Memory Select and Address Register (0x06)
D31
D30
D29
D28
D27
D26
D25
D24
–
–
–
–
–
–
–
–
DESCRIPTION
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
1
Audio DSP core coefficient memory select
0
0
0
0
0
0
1
0
Audio DSP core data memory select
0
0
0
0
0
0
1
1
Reserved
0
0
0
0
0
1
0
0
Microprocessor internal data memory select
0
0
0
0
0
1
0
1
Microprocessor external data memory select
0
0
0
0
0
1
1
0
SFR select
0
0
0
0
0
1
1
1
Microprocessor program RAM select
0
0
0
0
1
0
0
0
Audio DSP core program RAM select
0
0
0
0
1
0
0
1
Audio DSP core upper memory select
0
0
0
0
1
0
1
0
Audio DSP core program RAM select
D15
D14
D13
D12
D11
D10
D9
D8
A0
A1
A2
A3
A4
A5
A6
A7
D7
D6
D5
D4
D3
D2
D1
D0
A8
A9
A10
A11
A12
A13
A14
A15
Unused
DESCRIPTION
DESCRIPTION
Memory address
DESCRIPTION
Memory address
Table 9-7. Data Register (Peek and Poke) (0x07)
D63
D62
D61
D60
D59
D58
D57
D56
D63
D62
D61
D60
D59
D58
D57
D56
D55
D54
D53
D52
D51
D50
D49
D48
D55
D54
D53
D52
D51
D50
D49
D48
D47
D46
D45
D44
D43
D42
D41
D40
D47
D46
D45
D44
D43
D42
D41
D40
D39
D38
D37
D36
D35
D34
D33
D32
D39
D38
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D31
D30
D29
D28
D27
D25
D26
D25
D23
D22
D21
D20
D19
D18
D17
D16
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Submit Documentation Feedback
DESCRIPTION
Data to be written or read
DESCRIPTION
Data to be written or read
DESCRIPTION
Data to be written or read
DESCRIPTION
Data to be written or read
DESCRIPTION
Data to be written or read
DESCRIPTION
Data to be written or read
DESCRIPTION
Data to be written or read
DESCRIPTION
Data to be written or read
I2C Register Map
51
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.6 Device Version (0x08)
Table 9-8. Device Version
D31
D30
D29
D28
D27
D26
D25
D24
–
–
–
–
–
–
–
–
D23
D22
D21
D20
D19
D18
D17
D16
–
–
–
–
–
–
–
–
D15
D14
D13
D12
D11
D10
D9
D8
–
–
–
–
–
–
–
–
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
DESCRIPTION
Firmware definable
DESCRIPTION
Firmware definable
DESCRIPTION
Firmware definable
DESCRIPTION
TAS3204 device version
9.7 Analog Power Down Control (0x10 and 0x11), ESFR (0xE1 and 0xE2)
ESFR 0xE1, 0xE2 have the same bit mapping and functions as IC registers 0x10, 0x11, respectively.
Table 9-9. Analog Power Down Control 1 (0x10/0xE1)
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
–
1
Central reference enable
DESCRIPTION
–
–
–
–
–
–
–
0
Power down central reference
–
–
–
–
–
–
1
–
ADC1 enable
–
–
–
–
–
–
0
–
ADC1 power down
–
–
–
–
–
1
–
–
ADC2 enable
–
–
–
–
–
0
–
–
ADC2 power down
–
–
–
–
1
–
–
–
ADC reference enable
–
–
–
–
0
–
–
–
ADC reference power down
–
–
–
1
–
–
–
–
DAC reference enable
–
–
–
0
–
–
–
–
DAC reference power down
Table 9-10. Analog Power Down Control 2 (0x11/0xE2)
52
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
–
1
DAC1 left enable
–
–
–
–
–
–
–
0
DAC1 left power down
–
–
–
–
–
–
1
–
DAC1 right enable
–
–
–
–
–
–
0
–
DAC1 right power down
–
–
–
–
–
1
–
–
DAC2 left enable
–
–
–
–
–
0
–
–
DAC2 left power down
–
–
–
–
1
–
–
–
DAC2 right enable
–
–
–
–
0
–
–
–
DAC2 right power down
–
–
–
1
–
–
–
–
Line out 1 left enable
–
–
–
0
–
–
–
–
Line out 1 left power down
–
–
1
–
–
–
–
–
Line out 1 right enable
–
–
0
–
–
–
–
–
Line out 1 right power down
–
1
–
–
–
–
–
–
Line out 2 left enable
–
0
–
–
–
–
–
–
Line out 2 left power down
1
–
–
–
–
–
–
–
Line out 2 right enable
0
–
–
–
–
–
–
–
Line out 2 right power down
I2C Register Map
DESCRIPTION
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.8 Analog Input Control (0x12), ESFR (0xE3)
ESFR 0xE3 has the same bit mapping and functions as IC register 0x12.
Table 9-11. Analog Input Control
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
–
0
–
DESCRIPTION
–
–
–
–
–
–
–
1
Select input 1 to ADC 1
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
1
–
Select input 1 to ADC 2
–
–
–
–
–
0
–
–
–
–
–
–
–
–
1
–
–
Select input 2 to ADC 2
–
–
–
–
0
–
–
–
–
–
–
–
–
1
–
–
–
Select input 2 to ADC 2
–
–
–
0
–
–
–
–
–
–
–
–
1
–
–
–
–
Select input 3 to ADC 2
–
–
0
–
–
–
–
–
–
–
–
1
–
–
–
–
–
Select input 3 to ADC 2
–
0
–
–
–
–
–
–
ADC 1 differential input
–
1
–
–
–
–
–
–
ADC 1 single ended input
0
–
–
–
–
–
–
–
ADC 2 differential input
1
–
–
–
–
–
–
–
ADC 2 single ended input
9.9 Dynamic Element Matching (0x13), ESFR (0XE4)
ESFR 0xE4 has the same bit mapping and functions as IC register 0x13.
Table 9-12. Dynamic Element Matching
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
–
–
–
–
–
–
0
ADC dynamic element matching algorithm enabled (recommended
setting)
–
–
–
–
–
–
–
1
ADC dynamic element matching algorithm disabled
–
–
–
–
–
–
0
–
Dynamic weighted averaging enabled (recommended setting)
–
–
–
–
–
–
1
–
Dynamic weighted averaging disabled
–
–
–
–
–
0
–
–
Unused
–
–
–
–
–
1
–
–
Unused
–
–
–
–
0
–
–
–
Fast charge of cap on VREF (filtering disabled – recommended setting
at startup)
–
–
–
–
1
–
–
–
Slow charge of cap on VREF (filtering enabled – recommended setting
during normal operation)
–
–
–
0
–
–
–
–
Unused
–
–
–
1
–
–
–
–
Unused
–
–
0
–
–
–
–
–
Unused
–
–
1
–
–
–
–
–
Unused
–
0
–
–
–
–
–
–
Unused
–
1
–
–
–
–
–
–
Unused
0
–
–
–
–
–
–
–
Unused
1
–
–
–
–
–
–
–
Unused
Submit Documentation Feedback
I2C Register Map
53
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.10 Current Control Select (0x14, 0x15, 0x17, 0x18), ESFR (0xE5, 0xE6, 0xE7, 0xE9)
ESFR 0xE5, 0xE6, 0xE7, 0xE9 have the same bit mapping and functions as IC register 0x14, 0x15, 0x17,
and 0x18, respectively.
Table 9-13. Current Control Select (0x14/0xE5)
D7
54
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
–
–
–
–
–
0
0
ADC2 summer current setting (left and right) = 130% of nominal current
(recommended setting)
–
–
–
–
–
–
0
1
ADC2 summer current setting (left and right) = 100% of nominal current
–
–
–
–
–
–
1
0
ADC2 summer current setting (left and right) = 100% of nominal current
–
–
–
–
–
–
1
1
ADC2 summer current setting (left and right) = 70% of nominal current
–
–
–
–
0
0
–
–
ADC2 quantizer current setting (left and right) = 137.5% of nominal
current (recommended setting)
–
–
–
–
0
1
–
–
ADC2 quantizer current setting (left and right) = 100% of nominal current
–
–
–
–
1
0
–
–
ADC2 quantizer current setting (left and right) = 100% of nominal current
–
–
–
–
1
1
–
–
ADC2 quantizer current setting (left and right) = 62.5% of nominal
current
–
–
0
0
–
–
–
–
ADC2 third integrator current setting (left and right) = 130% of nominal
current (recommended setting)
–
–
0
1
–
–
–
–
ADC2 third integrator current setting (left and right) = 100% of nominal
current
–
–
1
0
–
–
–
–
ADC2 third integrator current setting (left and right) = 100% of nominal
current
–
–
1
1
–
–
–
–
ADC2 third integrator current setting (left and right) = 70% of nominal
current
0
0
–
–
–
–
–
–
ADC2 reference buffer current setting (left and right) = 130% of nominal
current (recommended setting)
0
1
–
–
–
–
–
–
ADC2 reference buffer current setting (left and right) = 100% of nominal
current
1
0
–
–
–
–
–
–
ADC2 reference buffer current setting (left and right) = 100% of nominal
current
1
1
–
–
–
–
–
–
ADC2 reference buffer current setting (left and right) = 70% of nominal
current
I2C Register Map
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-14. Current Control Select (0x15/0xE6)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
–
–
–
–
–
0
0
ADC2 second integrator current setting (left and right) = 130% of
nominal current
(recommended setting)
–
–
–
–
–
–
0
1
ADC2 second integrator current setting (left and right) = 100% of
nominal current
–
–
–
–
–
–
1
0
ADC2 second integrator current setting (left and right) = 100% of
nominal current
–
–
–
–
–
–
1
1
ADC2 second integrator current setting (left and right) = 70% of
nominal current
–
–
–
–
0
0
–
–
ADC2 second integrator current setting (left and right) = 130% of
nominal current
(recommended setting)
–
–
–
–
0
1
–
–
ADC2 first integrator current setting (left and right) = 100% of nominal
current
–
–
–
–
1
0
–
–
ADC2 first integrator current setting (left and right) = 100% of nominal
current
–
–
–
–
1
1
–
–
ADC2 first integrator current setting (left and right) = 70% of nominal
current
–
–
–
0
–
–
–
–
ADC2 current for common mode buffer to integrator 1 = 3.5 µA
–
–
–
1
–
–
–
–
ADC2 current for common mode buffer to integrator 1 = 2.0 µA
–
–
0
–
–
–
–
–
ADC2 current for common mode buffer to integrator 2 and 3 = 3.5 µA
–
–
1
–
–
–
–
–
ADC2 current for common mode buffer to integrator 2 and 3 = 2.0 µA
–
0
–
–
–
–
–
–
ADC2 current for the buffer to the ADC sampling switches = 3.5 µA
–
1
–
–
–
–
–
–
ADC2 current for the buffer to the ADC sampling switches = 2.0 µA
0
–
–
–
–
–
–
–
ADC2 current for the reference buffer to the ADC DAC = 3.5 µA
1
–
–
–
–
–
–
–
ADC2 Current for the Reference Buffer to The ADC DAC = 2.0 µA
Submit Documentation Feedback
I2C Register Map
55
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-15. Current Control Select (0x17/0xE7)
D7
56
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
–
–
–
–
–
0
0
ADC1 summer current setting (left and right) = 130% of nominal
current
(Recommended Setting)
–
–
–
–
–
–
0
1
ADC1 summer current setting (left and right) = 100% of nominal
current
–
–
–
–
–
–
1
0
ADC1 summer current setting (left and right) = 100% of nominal
current
–
–
–
–
–
–
1
1
ADC1 summer current setting (left and right) = 70% of nominal
current
–
–
–
–
0
0
–
–
ADC1 quantizer current setting (left and right) = 137.5% of nominal
current
(recommended setting)
–
–
–
–
0
1
–
–
ADC1 quantizer current setting (left and right) = 100% of nominal
current
–
–
–
–
1
0
–
–
ADC1 quantizer current setting (left and right) = 100% of nominal
current
–
–
–
–
1
1
–
–
ADC1 quantizer current setting (left and right) = 62.5% of nominal
current
–
–
0
0
–
–
–
–
ADC1 third integrator current setting (left and right) = 130% of
nominal current
(Recommended Setting)
–
–
0
1
–
–
–
–
ADC1 third integrator current setting (left and right) = 100% of
nominal current
–
–
1
0
–
–
–
–
ADC1 third integrator current setting (left and right) = 100% of
nominal current
–
–
1
1
–
–
–
–
ADC1 third integrator current setting (left and right) = 70% of nominal
current
0
0
–
–
–
–
–
–
ADC1 reference buffer current setting (left and right) = 130% of
nominal current
(Recommended Setting)
0
1
–
–
–
–
–
–
ADC1 reference buffer current setting (left and right) = 100% of
nominal current
1
0
–
–
–
–
–
–
ADC1 reference buffer current setting (left and right) = 100% of
nominal current
1
1
–
–
–
–
–
–
ADC1 reference buffer current setting (left and right) = 70% of
nominal current
I2C Register Map
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-16. Current Control Select (0x18/0xE9)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
–
–
–
–
–
0
0
ADC1 second integrator current setting (left and right) = 130% of
nominal current
(recommended setting)
–
–
–
–
–
–
0
1
ADC1 second integrator current setting (left and right) = 100% of
nominal current
–
–
–
–
–
–
1
0
ADC1 second integrator current setting (left and right) = 100% of
nominal current
–
–
–
–
–
–
1
1
ADC1 second integrator current setting (left and right) = 70% of
nominal current
–
–
–
–
0
0
–
–
ADC1 second integrator current setting (left and right) = 130% of
nominal current
(recommended setting)
–
–
–
–
0
1
–
–
ADC1 first integrator current setting (left and right) = 100% of nominal
current
–
–
–
–
1
0
–
–
ADC1 first integrator current setting (left and right) = 100% of nominal
current
–
–
–
–
1
1
–
–
ADC1 first integrator current setting (left and right) = 70% of nominal
current
–
–
0
0
–
–
–
–
ADC1 current for common mode buffer to integrator 1 = 3.5 µA
–
–
0
1
–
–
–
–
ADC1 current for common mode buffer to integrator 1 = 2.0 µA
–
–
1
0
–
–
–
–
ADC1 current for common mode buffer to integrator 2 and 3 = 3.5 µA
–
–
1
1
–
–
–
–
ADC1 current for common mode buffer to integrator 2 and 3 = 2.0 µA
0
0
–
–
–
–
–
–
ADC1 current for the buffer to the ADC sampling switches = 3.5 µA
0
1
–
–
–
–
–
–
ADC1 current for the buffer to the ADC sampling switches = 2.0 µA
1
0
–
–
–
–
–
–
ADC1 current for the reference buffer to the ADC DAC = 3.5 µA
1
1
–
–
–
–
–
–
ADC1 current for the reference buffer to the ADC DAC = 2.0 µA
Submit Documentation Feedback
I2C Register Map
57
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.11 DAC Control (0x1A, 0x1B, 0x1D), ESFR (0xEB, 0xEC, 0xEE)
ESFR 0xEB, 0xEC, and 0xED have the same bit mapping and functions as IC register 0x1A, 0x1B, and
0x1D, respectively.
Table 9-17. DAC Control (0x1A/0xEB)
D7
58
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
–
–
–
–
–
0
0
DAC1 current control for DAC local reference block and lineout amps
= default
(recommended setting)
–
–
–
–
–
–
0
1
DAC1 current control for DAC local reference block and lineout amps
= 125% bias current
–
–
–
–
–
–
1
0
DAC1 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
–
–
1
1
DAC1 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
0
0
–
–
DAC2 current control for DAC local reference block and lineout amps
= default
(recommended setting)
–
–
–
–
0
1
–
–
DAC2 current control for DAC local reference block and lineout amps
= 125% bias current
–
–
–
–
1
0
–
–
DAC2 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
1
1
–
–
DAC2 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I2C Register Map
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-18. DAC Control (0x1B/0xEC)
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
–
0
DAC1 chopper stabilization disable
DESCRIPTION
–
–
–
–
–
–
–
1
DAC1 chopper stabilization enable
–
–
–
–
–
–
0
–
DAC2 chopper stabilization disable
–
–
–
–
–
–
1
–
DAC2 chopper stabilization enable
–
–
–
–
–
0
–
–
DC offset subtraction in DACs 1 and 2 disable
–
–
–
–
–
1
–
–
DC offset subtraction in DACs 1 and 2 enable
–
–
–
–
0
–
–
–
Connected to microprocessor SDA2
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Table 9-19. DAC Control (0x1D/0xEE)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
–
–
–
–
–
0
0
DAC1 current control for DAC local reference block and lineout amps
= default
(recommended setting)
–
–
–
–
–
–
0
1
DAC1 current control for DAC local reference block and lineout amps
= 125% bias current
–
–
–
–
–
–
1
0
DAC1 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
–
–
1
1
DAC1 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
0
0
–
–
DAC2 current control for DAC local reference block and lineout amps
= default
(recommended setting)
–
–
–
–
0
1
–
–
DAC2 current control for DAC local reference block and lineout amps
= 125% bias current
–
–
–
–
1
0
–
–
DAC2 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
1
1
–
–
DAC2 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Submit Documentation Feedback
I2C Register Map
59
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.12 ADC and DAC Reset (0x1E), ESFR (0xFB)
ESFR 0xFB has the same bit mapping and functions as IC register 0x1E.
Table 9-20. ADC and DAC Reset (0x1E/0xFB)
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
–
0
–
DESCRIPTION
–
–
–
–
–
–
–
1
ADC reset channel 1
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
1
–
ADC reset channel 2
–
–
–
–
–
0
–
–
–
–
–
–
–
–
1
–
–
ADC reset channel 3
–
–
–
–
0
–
–
–
–
–
–
–
–
1
–
–
–
ADC reset channel 4
–
–
–
0
–
–
–
–
–
–
–
–
1
–
–
–
–
DAC reset channel 1
–
–
0
–
–
–
–
–
–
–
–
1
–
–
–
–
–
DAC reset channel 2
–
0
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
DAC reset channel 3
0
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
DAc reset channel 4
9.13 ADC Input Gain Control (0x1F), ESFR (0xFA)
Table 9-21. ADC Input Gain Control (0x1F/0xFA)
60
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
0
0
Channel 1Sinc input gain control = 0 dB
–
–
–
–
–
–
0
1
Channel 1Sinc input gain control = +30 dB
–
–
–
–
–
–
1
0
Channel 1Sinc input gain control = +600 dB
–
–
–
–
–
–
1
1
Channel 1Sinc input gain control = 0 dB
–
–
–
–
0
0
–
–
Channel 2Sinc input gain control = 0 dB
–
–
–
–
0
1
–
–
Channel 2Sinc input gain control = +30 dB
–
–
–
–
1
0
–
–
Channel 2Sinc input gain control = +60 dB
–
–
–
–
1
1
–
–
Channel 2Sinc input gain control = 0 dB
–
–
0
0
–
–
–
–
Channel 3Sinc input gain control = 0 dB
–
–
0
1
–
–
–
–
Channel 3Sinc input gain control = +30 dB
–
–
1
0
–
–
–
–
Channel 3Sinc input gain control =+60 dB
–
–
1
1
–
–
–
–
Channel 3Sinc input gain control = 0 dB
0
0
–
–
–
–
–
–
Channel 4Sinc input gain control = 0 dB
0
1
–
–
–
–
–
–
Channel 4Sinc input gain control = +30 dB
1
0
–
–
–
–
–
–
Channel 4Sinc input gain control = +60 dB
1
1
–
–
–
–
–
–
Channel 4Sinc input gain control = 0 dB
I2C Register Map
DESCRIPTION
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
9.14 MCLK_OUT Divider (0x21 and 0x22)
Table 9-22. MCLK_OUT 2 (0x21)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
1
DESCRIPTION
MCLK_OUT2 frequency is 6.144 MHz/(divider+1)
Table 9-23. MCLK_OUT 3 (0x22)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
DESCRIPTION
MCLK_OUT3 frequency is 512 kHz/(divider+1)
9.15 Digital Cross Bar (0x30 to 0x3F)
Table 9-24. Digital Cross Bar (0x30 to 0x3F)
SUBADDRESS
0x30
0x31
0x32
0x33
0x34
REGISTER
NAME
CH1 Input Mixer
CH2 Input Mixer
CH3 Input Mixer
CH4 Input Mixer
CH5 Input Mixer
Submit Documentation Feedback
NO. OF BYTES
32
32
32
32
32
CONTENTS
INITIALIZATION VALUE
Input cross bar mux
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
I2C Register Map
61
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-24. Digital Cross Bar (0x30 to 0x3F) (continued)
SUBADDRESS
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
62
REGISTER
NAME
CH6 Input Mixer
CH7 Input Mixer
CH8 Input Mixer
CH1 Output Mixer
CH2 Output Mixer
CH3 Output Mixer
CH4 Output Mixer
CH5 Output Mixer
I2C Register Map
NO. OF BYTES
32
32
32
32
32
32
32
32
CONTENTS
INITIALIZATION VALUE
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
Input cross bar mux
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-24. Digital Cross Bar (0x30 to 0x3F) (continued)
REGISTER
NAME
SUBADDRESS
0x3D
0x3E
0x3F
NO. OF BYTES
CH6 Output Mixer
CH7 Output Mixer
CH8 Output Mixer
CONTENTS
32
32
32
INITIALIZATION VALUE
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
9.16 Extended Special Function Registers (ESFR) Map
See TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details on ESFR.
Table 9-25. Extended Special Fucntion Registers (ESFR)
ESFR
MAPPED_TO
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
REGISTER TYPE
DESCRIPTION
84
di_o
8
OUT
I2C
8-bit asynchronous rstz
positive edge triggered
Reset low
Data to be transferred from microprocessor
to I2C
85
da_i
8
IN
I2C
NO REG - direct input
Data to be transferred from I2C to
microprocessor during slave write in I2C
slave-write mode if the MCU controls I2C
interface
86
sub_addr_i
8
IN
I2C
NO REG – direct input
Indicates the type of information being
relayed to the microprocessor. This affects
how the microprocessor changes the data
that follows the subaddress.
91
data_out1_i
8
IN
I2C
NO REG – direct input
92
data_out2_i
8
IN
I2C
NO REG – direct input
NO REG – direct input
These registers are used to deliver data
from the I 2C block to the microprocessor.
93
data_out3_i
8
IN
I2C
94
data_out4_i
8
IN
I2C
NO REG – direct input
Address of I2C internal registers. See Mentor
I2C product specification.
95
A_o
3
OUT
I2C
8-bit asynchronous rstz
positive edge triggered
Reset Low
96
i2s_word_byte_t
8
OUT
SAP
8-bit asynchronous rstz
positive edge triggered
Reset Low
Bit definition follows functional spec
definition for specification SAP WORD byte
97
i2s_mode_byte_t
8
OUT
SAP
8-bit asynchronous rstz
positive edge triggered
Reset Low
Bit definition follows functional spec
definition for specification SAP mode byte
A1
MLRCLK_t
5
OUT
CLOCK
5-bit asynchronous rstz
positive edge triggered
Reset Low
Bit definition follows functional spec
definition for specification MLRCLK field
Submit Documentation Feedback
I2C Register Map
63
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
MAPPED_TO
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
A2
SCLK_t
8
OUT
CLOCK
8-bit asynchronous rstz
positive edge triggered
Reset Low
Bit definition follows functional spec
definition for specification SCLK field
A3
addr_sel_t
4
OUT
DELAY_MEM
4-bit asynchronous rstz
positive edge triggered
Reset Low
Delay memory select lines
A4
addr_t
8
OUT
DELAY_MEM
8-bit asynchronous rstz
positive edge triggered
Reset Low
Delay memory address bus
A5
addr_t
5
OUT
DELAY_MEM
5-bit asynchronous rstz
positive edge triggered
Reset Low
Delay memory address bus high bits
A6
vol_mode_i_t
2
OUT
VOLUME
2-bit asynchronous rstz
positive edge triggered
Reset Low
Specify slew rate 0, 1, 2 (2048, 4096, 8192)
A7
volume_index_i_t
3
OUT
VOLUME
3-bit asynchronous rstz
positive edge triggered
Reset Low
Host control channel specification
8
OUT
VOLUME
8-bit asynchronous rstz
positive edge triggered
Reset Low
8
OUT
VOLUME
8-bit asynchronous rstz
positive edge triggered
Reset Low
A9
AA
64
vol_data_i_t
REGISTER TYPE
AB
vol_data_i_t
8
OUT
VOLUME
8-bit asynchronous rstz
positive edge triggered
Reset Low
AC
vol_data_i_t
4
OUT
VOLUME
4-bit asynchronous rstz
positive edge triggered
Reset Low
AD
To_micro_i[7:0]
8
IN
DSP
NO REG – direct input
AE
To_micro_i[15:8]
8
IN
DSP
NO REG – direct input
AF
To_micro_i[23:16]
8
IN
DSP
NO REG – direct input
B1
To_micro_i[31:24]
8
IN
DSP
NO REG – direct input
B2
To_micro_i[39:32]
8
IN
DSP
NO REG – direct input
D6
To_micro_i[47:40]
8
IN
DSP
NO REG – direct input
D7
To_micro_i[53:48]
8
IN
DSP
NO REG – direct input
B3
Data_to_DSP_o[7:0]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
Reset Low
B4
Data_to_DSP_o[15:0]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
B5
Data_to_DSP_o[23:16]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
B6
Data_to_DSP_o[31:24]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
Reset Low
B7
Data_to_DSP_o[39:32
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
Reset Low
B9
Data_to_DSP_o[47:40]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
Reset Low
BA
Data_to_DSP_o[53:48]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
Reset Low
BB
micro_addr_o[7:0]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
Reset Low
I2C Register Map
DESCRIPTION
Volume coefficient
Data bus from DSP to the microprocessor
Data bus from microprocessor to the DSP
Microprocessor uses these 16 bits to set
DSP RAM and Micro I addresses
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
MAPPED_TO
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
REGISTER TYPE
DESCRIPTION
Microprocessor uses these 16 bits to set
DSP RAM and Micro I addresses
Bit 10 of the address selects between audio
DSP coefficient and audio DSP data
memory
BC
micro_addr_o[13:8]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
Reset Low
BD
Mode0_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
Miscellaneous signal for
microprocessor-DSP communication.
This is not a bit-addressable register, but
contains bit data. The firmware must read in
the data, mask the change, and write it back
out.
BE
Mode3_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered,
Reset low
BF
Mode4_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
C1
C1 Mode5_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
C2
Mode6_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
C3
Mode7_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
C4
Mode8_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
C5
GPIO_IN_t
1
IN
DSP
1-bit asynchronous rstz
positive edge triggered
Reset Low
Registered input GPIO sense line
C6
gpio_enz_t
1
OUT
GPIO
4-bit asynchronous rstz
positive edge triggered
Reset Low
GPIO bidirect configuration—low → output,
high → input
C7
gpio_out_t
1
OUT
GPIO
1-bit asynchronous rstz
positive edge triggered
Reset Low
Drive value on GPIO line when configured
as output
C9
cs1
1
IN
CHIP_SEL
1-bit asynchronous rstz
positive edge triggered
Reset Low
Reset-low sense lines for chip-select
input/output
CA
tb_loop_count_t
8
OUT
TONE
8-bit asynchronous rstz
positive edge triggered
Reset Low
Tone slew rate counter configuration
Miscellaneous signal for
microprocessor-DSP communication.
This is not a bit-addressable register, but
contains bit data. The firmware must read in
the data, mask the change, and write it back
out.
CB
dlymemif_out
8
IN
DLY_MEM
NO REG – direct input
Low-byte delay interface date port
CC
dlymemif_out
8
IN
DLY_MEM
NO REG – direct input
High-byte delay interface date port
CD
dlymemif_out
8
IN
DLY_MEM
NO REG – direct input
High-byte delay interface date port
CE
cntrl1_treb_active_t
1
OUT
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
CF
cntrl2_treb_active_t
1
OUT
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
D0
cntrl3_treb_active_t
1
OUT
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
D1
cntrl4_treb_active_t
1
OUT
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
D2
cntrl1_bass_active_t
1
OUT
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
D3
cntrl2_bass_active_t
1
OUT
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
D4
cntrl3_bass_active_t
1
OUT
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
Submit Documentation Feedback
Schedule tone coefficient calculations in the
audio DSP
Schedule tone coefficient calculations in the
audio DSP
I2C Register Map
65
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
MAPPED_TO
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
D5
cnrtrl4_bass_active_t
1
OUT
C0(0)
I2c_irg_o
1
OUT
REGISTER TYPE
DESCRIPTION
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
Schedule tone coefficient calculations in the
audio DSP
I2C
1-bit asynchronous rstz
positive edge triggered
ONE SHOT (PULSE)
Reset low
PULSE REGISTER
Slave read: set high when MCU recognizes
that the SLAVE_READ bit on the I2C has
been set high.
Slave write: if the RCVD_DATA_STAT bit is
set high by the I2C, microprocessor sets IRG
high in response.
PULSE REGISTER
I2C_MCU is set to 1 MCU assumes control
over the I2C interface. If it is set to 0, the I2C
block has control. If the microprocessor
reads a 1 on slave_read, it sends an ACK to
the I2C and sets I2C_MCU high.
C0(1)
I2c_mcu_o
1
OUT
I2C
1-bit asynchronous rstz
positive edge triggered
RESET HI
C0(2)
update_volume_t
1
OUT
VOLUME
1-bit asynchronous rstz
positive edge triggered
Reset low
Signoff assertion that volume coefficients to
volume block are updated and execution is
commanded
C0(3)
clr_dly_RAM_t
1
OUT
DLY_MEM
1-bit asynchronous rstz
positive edge triggered
Reset low
Used during initialization to inspire
self-clearing logic activation to the delay
RAM
C0(4)
wr_t
1
OUT
I2C
1-bit asynchronous rstz
positive edge triggered
ONE SHOT (PULSE)
PULSE REGISTER
I2C write pulse for slave transmit and master
transmit
C0(5)
I2c_sel_o
1
OUT
I2C
1-bit asynchronous rstz
positive edge triggered
The I2C has two registers to which the
microprocessor can write. This signal selects
one of them.
C0(6)
micro_RAM_we_req_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
ONE SHOT (PULSE)
PULSE REGISTER
When DSP_HOST = 1, the microprocessor
has direct control of the RAMs and pulses
this signal to write to them.
1-bit asynchronous rstz
positive edge triggered
ONE SHOT (PULSE)
When DSP_HOST is high and the
microprocessor has complete control of the
DSP RAMS, this bit is N/A. When
DSP_HOST is low, the microprocessor uses
this bit to submit a read request to the DSP.
C0(7)
micro_rd_req_o
1
OUT
DSP
C8(0)
power_down_in
1
IN
CNTL
NO REG – direct input
Power-down pin sense
Volume busy flag
C8(2)
vol_busy_o
1
IN
VOL
1-bit asynchronous rstz
positive edge triggered
Reset High
C8(3)
mem_bist_i
1
IN
membist
Direct input
Indicates chip is in firmware BIST mode
C8(4)
intr
1
IN
CNTL
Direct input
Indicates status warp IFLAG
DSP sets this bit to notify microprocessor it
has captured data
C8(5)
micro_ack_I
1
IN
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
C8(6)
clearing_dly_RAM_t
1
IN
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
Busy flag from Delay RAM Init clear process
C8(7)
dsp_rom_bist_I
1
IN
DSP
NO REG – direct input
Set HIGH to signal that DSP ROM BIST
completed successfully
D8(0)
power_down_o
1
OUT
Multiple blks
1-bit asynchronous rstz
positive edge triggered
Reset low
Set HIGH by the microprocessor. (Need
more info)
D8(1)
watchdog_clr_t
1
OUT
CNTL
1-bit asynchronous rstz
positive edge triggered
Reset low
Strobe to the watchdog timer logic
D8(2)
slave_mode_t
1
OUT
DLY_MEM
1-bit asynchronous rstz
positive edge triggered
Reset low
Asserted to provide direct delay memory
access to the host (microprocessor)
D8(3)
addr_wr_t
1
OUT
DLY_MEM
1-bit asynchronous rstz
positive edge triggered
Reset low
Write assertion to delay memory during host
control configuration
66
I2C Register Map
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
MAPPED_TO
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
D8(4)
micro_wr_en_i_t
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
Write enable signal to the audio DSP
coefficients and DATA RAMs
D8(5)
host_DSP_o
1
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset high
Sets the DSP in host mode. Microprocessor
is in control
D8(6)
bass_data_ready_o
1
OUT
T/B
1-bit asynchronous rstz
positive edge triggered
Reset low
Microprocessor notifies T/B block that bass
data has been processed and is ready.
D8(7)
treble_data_ready_o
1
OUT
T/B
1-bit asynchronous rstz
positive edge triggered
Reset low
Microprocessor notifies T/B block that treble
data has been processed and is ready.
MICRO DAP
2-bit asynchronous rstz
positive edge triggered
Reset low
D9
MEM_SEL
2
OUT
FC
i2c_ms_ctl
1
OUT
FD
pc_source
1
OUT
FE
sap_en_t
1
OUT
Submit Documentation Feedback
I2C
SAP
REGISTER TYPE
DESCRIPTION
00
Audio DSP coefficient/data
(Depending on address bit 10)
01
Audio DSP instruction
10
Microprocessor instruction
11
Reserved
1-bit asynchronous rstz
positive edge triggered
Reset low
Select Master or Slave mode by switching
mux
1-bit asynchronous rstz
positive edge triggered
Reset low
Changes source from microprocessor
program ROM to microprocessor program
RAM
1-bit asynchronous rstz
positive edge triggered
Reset Low
Expected to toggle high, then low, to inspire
a recent SAP change to activate.
I2C Register Map
67
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
10 Application Information
10.1 Schematics
Figure 10-1 shows a typical TAS3204 application. In this application the following conditions apply:
•
•
•
•
•
TAS3204 is in clock-master mode. The TAS3204 generates MCLK_OUT1, SCLK_OUT, and
LRCLOK_OUT.
XTAL_IN = 24.576 MHz
I2C register 0x00 contains the default settings, which means:
– Audio data word size is 24-bit input and 24-bit output.
– Serial data format is 2-channel, I2S for input and output.
– I2C data transfer is approximately 400 kbps for both master and slave I2C interfaces.
– Sample frequency (fS) is 48 kHz, which means that fLRCLK = 48 kHz and fSCLKIN = 3.072 MHz.
Application code and data are loaded from an external EEPROM using the master I2C interface.
Application commands come from the system microprocessor to the TAS3204 using the slave I2C
interface.
Good design practice requires isolation between the digital and analog power as shown. Power supply
capacitors of 10 µF and 0.1 µF should be placed near the power supply pins AVDD (AVSS) and DVDD
(DVSS).
The TAS3204 reset needs external glitch protection. Also, reset going HIGH should be delayed until
TAS3204 internal power is good (~200 µs after power up). This is provided by the 1-kΩ resistor, 1-µF
capacitor, and diode placed near the RESET pin.
It is recommended that a 4.7-µF capacitor (fast ceramic type) be placed near pin 28 (VR_DIG). This pin
must not be used to source external components.
68
Application Information
Submit Documentation Feedback
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197 – APRIL 2007
I2S Master Mode Application
3.3 W
3.3 V
2
4.7 µF
I S Input
0.1 µF
40
39
38
37
AVSS2
13
14
36
35
AOUT1RM
1 MW
33 pF
33 pF
AVSS3
AOUT1RP
AOUT1LP
3.3 V
3.3 W
AOUT2LM
32
29
30
31
26
27
28
25
33
24
34
16
23
15
17
18
AIN2LP
9
22
AIN1RM
AVDD3
VR_ANA
11
12
21
AIN1LM
MCLK_IN
XTAL_OUT
XTAL_IN
10
19
20
AIN1LP
AIN1RP
24.576 MHz
0.1 µF
41
3.3 W
DVSS2
4.7 µF
42
8
3.3 V
DVDD2
0.1 µF
43
7
MCLK_OUT1
MCLK_OUT2
MCLK_OUT3
0.1 µF
RESERVED
VREG_EN
49
SDOUT2
SCLK_OUT
LRCLK_OUT
52
51
50
DVSS3
VR_DIG
SDOUT1
55
54
53
57
56
SCLK_IN
LRCLK_IN
DVDD3
58
6
PDN
AVSS1
0.1 µF
59
44
VR_PLL
4.7 µF
SDIN1/GPIO3
5
DVDD1
0.1uF
SDIN2/GPIO4
MUTE
DVSS1
3.3 V
60
GPIO1
46
45
CS0
3.3 W
62
61
I2C2_SCL
48
47
3
4
GPIO2
10 kW
2
I S Output
1
2
I2C1_SDA
Controller
64
63
I2C1_SCL
External
I2C2_SDA
RESET
0.1 µF
0W
0W
EEPROM
AOUT2RP
AOUT2RM
AOUT2LM
AVDD2
AOUT2LP
REXT
VREF
VMID
AVDD1
AIN3RM
AIN3RP
AIN3LM
AIN3LP
Input
AIN2RM
AIN2LM
Stereo Analog
AIN2RP
Three Differential
Two Differential
Stereo Analog
A.
22 kW
4.7 µF
0.1 µF
0.1 µF
0.1 µF
Output
0.1 µF
3.3 W
4.7 µF
3.3 V
Capacitors should be placed as close as possible to the power supply pins.
Figure 10-1. Typical Application Diagram
10.2 Recommended Oscillator Circuit
TAS3204
Oscillator
Circuit
C1
rd
XO
C2
XI
AVSS
•
•
•
•
Crystal type = parallel-mode, fundamental-mode crystal
rd = drive-level control resistor – vendor specified
CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)
CL = (C1× C2)/(C1 + C2) + CS (where CS = board stray capacitance, ~2 pF)
Submit Documentation Feedback
Application Information
69
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TAS3204PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS3204PAGR
ACTIVE
TQFP
PAG
64
1500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated