DS100BR410
Low Power Quad Channel Repeater with 10.3125 Gbps
Equalizer and De-Emphasis Driver
General Description
Features
The DS100BR410 is an extremely low power, high performance quad-channel repeater for high-speed serial links with
data rates up to 10.3125 Gbps. The device performs both receive equalization and transmit de-emphasis on each of its 4
channels to compensate for channel loss, allowing maximum
flexibility of physical placement within a system.
The receiver's continuous time linear equalizer (CTLE) is capable of opening an input eye that is completely closed due
to inter-symbol interference (ISI) induced by the interconnect
medium such as backplane trace or cable. The transmitter
features adjustable VOD (output amplitude voltage level) and
de-emphasis driver to compensate for PCB trace lost.
With a low power consumption and control to turn-off unused
channels, the DS100BR410 is part of National's PowerWise
family of energy efficient devices.
The programmable settings can be applied via pin mode or
SMBus mode interface.
■ Quad channel repeater for up to 10.3125 Gbps
■ Low power consumption, with option to power down
■
■
■
■
■
■
■
■
■
■
unused channels
Adjustable receive equalization
Adjustable transmit de-emphasis
Adjustable transmit VOD (up to 1200 mVp-p)
IDLE detection — squelch function auto mutes the output
for SATA/SAS OOB signal
<0.22 UI of residual DJ at 10.3125 Gbps with 12 meters
cable
Programmable via pin selection or SMBus interface
Single supply operation at 2.5 V ±5%
-40°C to +85°C Operation
≥7 kV HBM ESD Rating
High speed signal flow–thru pinout package: 48-pin LLP
(7 mm x 7 mm, 0.5 mm pitch)
Applications
■ High-speed active copper cable modules
■ FR-4 Backplanes
■ 10GE, 8GFC, 10GFC, 10G SONET, SAS, SATA, and
InfiniBand
Typical Application Diagram
30122480
© 2012 Texas Instruments Incorporated
301224 SNLS326A
www.ti.com
DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis
Driver
March 22, 2012
DS100BR410
Connection Diagram
30122426
Ordering Information
NSID
Quantity
Package
Spec
DS100BR410SQE 48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch)
250 in Tape & Reel
SQA48A
NOPB
DS100BR410SQ
48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch)
1000 in Tape & Reel
SQA48A
NOPB
DS100BR410SQX 48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch)
2500 in Tape & Reel
SQA48A
NOPB
www.ti.com
Package Description
2
Pin Name
Pin #
I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0–
1
2
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor connects IN_0+ to IN_0-.
IN_1+
IN_1–
4
5
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor connects IN_1+ to IN_1-.
IN_2+
IN_2–
8
9
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor connects IN_2+ to IN_2-.
IN_3+
IN_3–
11
12
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor connects IN_3+ to IN_3-.
OUT_0+
OUT_0–
36
35
O, CML
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω
terminating resistor connects OUT_0+ to OUT_0-.
OUT_1+
OUT_1–
33
32
O, CML
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω
terminating resistor connects OUT_1+ to OUT_1-.
OUT_2+
OUT_2–
29
28
O, CML
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω
terminating resistor connects OUT_2+ to OUT_2-.
OUT_3+
OUT_3–
26
25
O, CML
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω
terminating resistor connects OUT_3+ to OUT_3-.
2.5V LVCMOS CONTROL PINS
BST_2
BST_1
BST_0
37
14
23
I, LVCMOS
BST_2, BST_1, and BST_0 select the equalizer boost level for all channels.
BST_2 and BST_1 are internally pulled high.
BST_0 is internally pulled low. See Table 1
EN0
EN1
EN2
EN3
44
42
40
38
I, LVCMOS
Enable channel n input.
When held High, normal operation is selected.
When held Low, standby mode is selected.
EN is internally pulled High.
PIN_MODE
21
I, LVCMOS
Pin mode control input.
When held High, device is in Pin control mode.
When held Low, device is in SMBus Control Mode
PIN_MODE is internally pulled High.
SD0
SD1
SD2
SD3
45
43
41
39
O, LVCMOS
Signal detect n output.
Output is High when signal is detected.
Output is Low when signal is NOT detected.
OOB_DIS
47
I, LVCMOS
OOB disable control input.
When held High, OOB is disabled.
When held Low, OOB is enabled.
Out Of Band (OOB) for SATA/SAS applications is active.
OOB_DIS is internally pulled Low.
Analog Input Pins (4–level Inputs)
VOD_SEL
19
I, analog
Differential Output Voltage Select Input
Tie to VDD, VOD = 1.2 Vp-p
Leave Open, VOD = 1.0 Vp-p
Resistor (20 kΩ) to GND, VOD = 800 mVp-p
Tie to GND, VOD = 600 mVp-p
DE_SEL
20
I, analog
De-Emphasis Select Input
Tie to VDD = -9 dB
Leave Open = -6 dB
Resistor (20 kΩ) to GND = -3 dB
Tie to GND = 0 dB
3
www.ti.com
DS100BR410
Pin Descriptions
DS100BR410
Pin Name
Pin #
I/O, Type
Description
SERIAL MANAGEMENT BUS (SMBus) INTERFACE
SDA
18
I/O, LVCMOS Data Input / Open Drain Output
External pull-up resistor is required.
Pin is 3.3 V LVCMOS tolerant.
SDC
17
I, LVCMOS
Clock Input
Pin is 3.3 V LVCMOS tolerant.
CS
16
I, LVCMOS
Chip Select
When high, access to the SMBus registers are enabled. When low, access to the SMBus
registers are disabled. Please refer to “SMBus configuration Registers” section for detail
information.
Pin is 3.3 V LVCMOS tolerant.
VDD
3, 6, 7,
10, 13,
15, 46
Power
VDD = 2.5 V ± 5%
GND
22, 24,
27, 30,
31, 34
Power
Ground reference.
DAP
PAD
Power
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board with at least 4 via to lower the ground impedance and improve
the thermal performance of the package.
RES
48
NC
POWER
Reserved – Do not connect
Note: I = Input O = Output, LVCMOS pins are 2.5 V levels only, only SMBus pins SDA, SDC and CS are 3.3V tolerant.
www.ti.com
4
Thermal Resistance
θJA, No Airflow,
4 layer JEDEC, 9 thermal vias
27.6 °C/W
For soldering specifications: see product folder at
www.national.com
www.national.com/ms/MS/MS-SOLDERING.pdf
-0.5V to +2.75V
-0.5V to +2.75V
-0.5V to +4.0V
Recommended Operating
Conditions
-0.5V to +2.75V
-0.5V to +2.75V
+150°C
-65°C to +150°C
Supply Voltage
VDD to GND
Ambient Temperature
≥7 kV
Min
Typ
Max Units
2.375
-40
2.5
25
2.625
+85
V
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified. (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Device Output Enabled
(EN[3:0] = High),
VOD_SEL = open (1.0 Vp-p)
220
275
mW
Device Output Disable
(EN[3:0] = Low)
25
40
mW
50 Hz to 100 Hz
100
mVP-P
100 Hz to 10 MHz
40
mVP-P
10 MHz to 5.0 GHz
10
mVP-P
POWER
PD
PSNT
Power Supply Consumption
Supply Noise Tolerance (Note 4)
2.5 LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
1.75
VDD
V
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
IOH = -3mA
-0.3
0.7
V
VOL
Low Level Output Voltage
IOL = 3mA
0.4
V
IIN
Input Leakage Current
VIN = VDD
+10
μA
IIN-P
Input Leakage Current with
Internal Pull-Down/Up Resistors
2.0
VIN = GND
V
μA
-10
VIN = VDD, with internal pull-down
resistors
VIN = GND, with internal pull-up
resistors
+65
μA
μA
-50
SIGNAL DETECT
SDH
Signal Detect ON Threshold Level Default input signal level to assert
SD pin, 10.3125 Gbps
130
mVp-p
SDL
Signal Detect OFF Threshold
Level
60
mVp-p
Default input signal level to deassert SD, 10.3125 Gbps
5
www.ti.com
DS100BR410
CDM, STD - JESD22-C101-D
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
2.5 I/O Voltage
(LVCMOS and Analog Input)
3.3 LVCMOS I/O Voltage
(SDA, SDC, CS)
CML Input Voltage (IN_n+/-)
CML Output Voltage (OUT_n+/-)
Junction Temperature
Storage Temperature
ESD Rating
HBM, STD - JESD22-A114F
≥200 V
≥1250 V
MM, STD - JESD22-A115-A
Absolute Maximum Ratings (Note 1)
DS100BR410
Symbol
Parameter
Conditions
Min
Source Transmit Launch Signal
Level (IN diff)
AC-Coupled Requirement,
Differential measurement at point
A. Figure 1
600
Differential Input Return Loss SDD11
100 MHz – 6 GHz, with fixture’s
effect de-embedded
Typ
Max
Units
1600
mVP-P
CML RECEIVER INPUTS (IN_n+, IN_n-)
VTX
RLI
-15
dB
CML DRIVER OUTPUTS (OUT_n+, OUT_n-)
VOD
Output Differential Voltage Level
(Note 6), Figure 2
Differential measurement with
OUT+ and OUT- terminated by
50Ω to GND, AC-Coupled,
VOD_SEL = open (1.0 Vp-p),
DE_SEL = GND
750
Differential measurement with
OUT+ and OUT- terminated by
50Ω to GND, AC-Coupled,
VOD_SEL = VDD (1.2 Vp-p),
DE_SEL = GND
VOD_DE
tR, tF
RLO
De-Emphasis Levels
(Note 6, Note 7)
Transition Time
1150
mVP-P
1140
mVP-P
DE_SEL = 20kΩ to GND,
VOD_SEL = VDD (1.2 Vp-p)
-3
dB
DE_SEL = open,
VOD_SEL = VDD (1.2 Vp-p)
-6
dB
DE_SEL = VDD,
VOD_SEL = VDD (1.2 Vp-p)
-9
dB
20% to 80% of differential output
voltage, measured within 1” from
output pins. Figure 2
Differential Output Return Loss SDD22
100 MHz – 6 GHz, with fixture’s
effect de-embedded. IN+ = static
high.
tPLHD
Differential Low to High
Propagation Delay
tPHLD
Differential High to Low
Propagation Delay
Propagation delay measurement
at 50% crossing between input to
output, 100 Mbps. Figure 3
tCCSK
Inter Pair Channel to Channel
Skew
tPPSK
RJ
www.ti.com
970
30
38
45
ps
-15
dB
240
ps
240
ps
Difference in 50% crossing
between channels
7
ps
Part to Part Output Skew
Difference in 50% crossing
between outputs
20
ps
Random Jitter
VTX = 1.0 Vp-p, BST_[2:0] = 000,
(Note 6, Note 8)
0.3
psrms
6
Parameter
Conditions
Min
Typ
Max
Units
EQUALIZATION
DJ1
DJ2
Residual Deterministic Jitter
at 10.3125 Gbps
VTX = 1.0 VP-P,
12 meter 30 AWG cable,
EQ = 03F'h (BST[2:0] = 111),
PRBS-7 (27-1) pattern. (Note 5)
0.10
0.22
UIP-P
Residual Deterministic Jitter
at 6.0 Gbps
VTX = 1.0 VP-P,
12 meter 30 AWG cable,
EQ = 07F'h, PRBS-7 (27-1)
pattern. (Note 5)
0.07
0.12
UIP-P
SIGNAL DETECT and ENABLE TIMING
tZISD
Input OFF to ON detect — SD
Output High Response Time
tIZSD
Input ON to OFF detect — SD
Output Low Response Time
tOZOED
EN High to Output ON Response
Time
tZOED
Response time measurement at
VIN to SD output, VIN = 800 mVP-P,
100 Mbps, 40” of 6 mil microstrip
FR4. Figure 4
Response time measurement at
EN input to VO, VIN = 800 mVP-P,
EN Low to Output OFF Response 100 Mbps, 40” of 6 mil microstrip
FR4. Figure 5
Time
35
ns
400
ns
150
ns
5
ns
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 4: Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
Note 5: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 6: Measured with clock-like {11111 00000} pattern.
Note 7: The de-emphasis level of −3 dB, −6 dB, −9 dB are for VOD = 1.2 Vp-p. At lower VOD level, the de-emphasis levels are reduced.
Note 8: Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see point C of Figure
1; JIN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
7
www.ti.com
DS100BR410
Symbol
DS100BR410
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified. (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
VDD
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SDC
RTERM
External Termination Resistance VDD3.3,
pull to VDD = 2.5V ± 5% OR 3.3V ± (Note 11, Note 12)
10%
VDD2.5,
(Note 11, Note 12)
2.1
(Note 11)
4
mA
2.375
3.6
V
-200
+200
µA
-15
(Note 11, Note 12)
µA
10
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS – (See Figure 6)
FSMB
Bus Operating Frequency
10
TBUF
Bus Free Time Between Stop and
Start Condition
4.7
µs
THD:STA
Hold time after (Repeated) Start
At IPULLUP, Max
Condition. After this period, the first
clock is generated.
4.0
µs
TSU:STA
Repeated Start Condition Setup
Time
4.7
µs
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
250
ns
TLOW
Clock Low Period
4.7
µs
THIGH
Clock High Period
4.0
50
µs
tF
Clock/Data Fall Time
300
ns
tR
Clock/Data Rise Time
1000
ns
tPOR
Time in which a device must be
operational after power-on reset
500
ms
100
kHz
Note 9: Recommended value. Parameter not tested in production.
Note 10: Recommended maximum capacitance load per bus segment is 400pF.
Note 11: Maximum termination voltage should be identical to the device supply voltage.
Note 12: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
www.ti.com
8
DS100BR410
AC Waveforms and Test Circuits
30122427
FIGURE 1. Test Setup Diagram
30122402
FIGURE 2. Output Transition Times
30122403
FIGURE 3. Propagation Delay Timing Diagram
30122404
FIGURE 4. Signal Detect (SD) Delay Timing Diagram
9
www.ti.com
DS100BR410
30122405
FIGURE 5. Enable (EN) Delay Timing Diagram
30122418
FIGURE 6. SMBus Timing Parameters
www.ti.com
10
DS100BR410 Functional Descriptions
The DS100BR410 is a Low Power Quad Channel Repeater
with Equalizer and De-Emphasis Driver optimized for operation up to 10.3125 Gbps for backplane and cable applications.
30122406
FIGURE 7. Simplified Block Diagram
EQUALIZER BOOST CONTROL
Each data channel support eight programmable levels of
equalization boost. The state of the PIN_MODE control input
determines how the boost settings are controlled. If
PIN_MODE is held High, then the equalizer boost setting is
controlled by the Boost Set pins (BST_[2:0]) in accordance
with Table 1. If this programming method is chosen, then the
boost setting selected on the Boost Set pins is applied to all
channels. When PIN_MODE is held Low, the equalizer boost
level is controlled through the SMBus. This programming
method is accessed via the appropriate SMBus registers (see
Table 4). Using this approach, equalizer boost settings can
be programmed for each channel individually. PIN_MODE is
internally pulled High, therefore if left open, the boost settings
are controlled by the Boost Set pins (BST_[2:0]). The eight
levels of boost settings enables the DS100BR410 to address
a wide range of media loss and data rates.
Inputs
SMBus
Register Bits
Result @ 5 GHz
0
0
000000000
2.7 dB
0
0
1
000000001
7.3 dB
0
1
0
000000011
12.2 dB
0
1
1
000000111
16.6 dB
1
0
0
000001111
20.6 dB
1
0
1
000011111
24.8 dB
1
1
0
000101111
27.6 dB (default)
1
1
1
000111111
28.9 dB
SIGNAL DETECT
The DS100BR410 features a signal detect circuit on each
data channel. The status of the signal of each channel can be
determined by either reading the Signal Detect bit (SDn) in
the SMBus registers (see Table 4) or by the state of each SDn
pin. An output logic high indicates the presence of a signal
that has exceeded the ON threshold value (called SDH). An
output logic Low means that the input signal has fallen below
the OFF threshold value (called SDL). These values are programmed via the SMBus. If not programmed via the SMBus,
the thresholds take on the default values. The Signal Detect
threshold values can be changed through the SMBus. All
threshold values specified are DC peak-to-peak differential
signals (positive signal minus negative signal) at the input of
the device.
BST_2 BST_1 BST_0 [8:0]
0
Result @ 5 GHz
BST_2 BST_1 BST_0 [8:0]
TABLE 1. Boost / EQ Pin Mode Configuration
Inputs
SMBus
Register Bits
OUTPUT LEVEL CONTROL
The output amplitude of the CML drivers can be controlled via
the 4–level analog input VOD_SEL pin or via SMBus (see
Table 4). The default VOD level is 1.0 Vp-p.
TABLE 2. VOD_SEL Pin Configuration
11
VOD_SEL Pin
Result
Tie High - VDD
1.2 Vp-p
Open* (default)
1.0 Vp-p
20 kΩ resistor to GND
800 mVp-p
Tie to GND
600 mVp-p
www.ti.com
DS100BR410
DATA CHANNELS
The DS100BR410 provides four data channels. Each data
channel consists of an equalizer stage, a limiting amplifier, a
DC offset correction block, and a CML driver as shown in
Figure 7.
Functional Description
DS100BR410
OUTPUT DE-EMPHASIS CONTROL
The output De-Emphasis may be controled via the 4–level
analog input DE_SEL pin or via SMBus (see Table 4).
SMBus Transactions
The device supports WRITE, Burst WRITE, READ. and Burst
READ transactions. See Register Description table for register address, type (Read/Write, Read Only), default value and
function information.
Writing a Register
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drive the 8-bit data byte.
7. The Device drives an ACK bit (“0”).
8. The Host drives a STOP condition.
9. The Host de-selects the device by driving its SMBus CS
signal Low.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drives a START condition.
7. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
8. The Device drives an ACK bit “0”.
9. The Device drives the 8-bit data value (register contents).
10. The Host drives a NACK bit “1”indicating end of the
READ transfer.
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS
signal Low.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Information on the Registers
The status registers 01'h to 03'h provide information of the
channel that is selected. The information provided are the
OOB_DIS, EN, EQ Boost, VOD and DEM bits of the selected
channel. By default, channel 0 is selected. In order to change
the selected channel, write to reg_07 bit[5:4]. Write a 1 to
reg_07 bit[0] is also needed to allow the registers 13'h to 1A'h
to control the channel EN and EQ boost bits of each of the
channels. Each channel can be individually enabled (EN) and
set to a desired boost level with these registers. Please refer
to Table 4 for additional information.
TABLE 3. DE_SEL Pin Configuration
DE_SEL Pin
Result
Tie High - VDD
-9 dB
Open* (default)
-6 dB
20 kΩ resistor to GND
-3 dB
Tie to GND
0 dB
AUTOMATIC ENABLE FEATURE
It may be desirable to place unused channels in power-saving
Standby mode. This can be accomplished by connecting the
Signal detect (SDn) pin to the Enable (ENn) pin for each
channel (See Figure 7).
System Management Bus (SMBus)
and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the Chip
Select signal is required. Holding the CS pin High enables
the SMBus port allowing access to the configuration registers.
Holding the CS pin Low disables the device's SMBus allowing
communication from the host to other slave devices on the
bus. In the STANDBY state, the System Management Bus
remains active. When communication to other devices on the
SMBus is active, the CS signal for the DS100BR410s must
be driven Low.
The address byte for all DS100BR410s is AC'h. Based on the
SMBus 2.0 specification, the DS100BR410 has a 7-bit slave
address of 1010110'b. The LSB is set to 0'b (for a WRITE),
thus the 8-bit value is 1010 1100'b or AC'h.
The SDA, SDC and CS pins are 3.3V tolerant, but are not 5V
tolerant. External pull-up resistor is required on the SDA. The
resistor value can be from 1 kΩ to 5 kΩ depending on the
voltage, loading and speed. The SDC and CS may also require an external pull-up resistor and it depends on the Host
that drives the bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SDC is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SDC is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High
indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
www.ti.com
12
DS100BR410
TABLE 4. DS100BR410 Register Map
ADD
(hex)
REG Name
Bit(s)
Field
Type
Default
(binary)
Description
00
Device ID
7:4
Device ID
R
0010
Device ID Value
3
SD_CH3
R
1: Signal detected on CH3
0: No signal
2
SD_CH2
R
1: Signal detected on CH2
0: No signal
1
SD_CH1
R
1: Signal detected on CH1
0: No signal
0
SD_CH0
R
1: Signal detected on CH0
0: No signal
7
Reserved
R
6
OOB_DIS
R
5
Reserved
R
4
EN
R
3:1
Reserved
R
0
Boost_bit[8]
R
Boost_bit[8]
7:0
Boost_bit[7:0]
R
Boost_bit[7:0]
01
Status Register
for OOB_DIS,
EN and
Boost_bit[8]
02
Status Register
for Boost_bit
[7:0]
03
Status Register 7:6
for VOD[5:4] and 5:4
DEM[1:0]
Reserved
R
VOD[5:4]
R
3:2
Reserved
R
1:0
DEM[1:0]
R
OOB_DIS
1: OOB Disabled
0: OOB Enabled
EN
1: Channel Enabled
0: Channel Disabled
VOD[5:4]
00 = 0.6 Vp-p
01 = 0.8 Vp-p
10 = 1.0 Vp-p
11 = 1.2 Vp-p
DEM[1:0]
00 = 0 dB
01 = -3 dB
10 = -6 dB
11 = -9 dB
04
Reserved
7:0
Reserved
R
00
05
Signal Detect
Assert
Threshold
7:6
SD_ON_CH3
R/W
00
5:4
SD_ON_CH2
R/W
00
3:2
SD_ON_CH1
R/W
00
1:0
SD_ON_CH0
R/W
00
7:6
SD_OFF_CH3
R/W
00
5:4
SD_OFF_CH2
R/W
00
3:2
SD_OFF_CH1
R/W
00
1:0
SD_FF_CH0
R/W
00
06
Signal Detect
De-assert
Threshold
13
Signal Detect ON Threshold
00 = 130 mV
01 = 125 mV
10 = 150 mV
11 = 140 mV
Signal Detect OFF Threshold
00 = 60 mV
01 = 40 mV
10 = 105 mV
11 = 90 mV
www.ti.com
DS100BR410
ADD
(hex)
07
08
REG Name
Bit(s)
Field
Type
Default
(binary)
Port/Channel
Select and
Enable SMBus
Registers
7:6
Reserved
R/W
00
5:4
Port/Channel Select for
Status
R/W
00
3:1
Reserved
R/W
000
0
SMBUS Channel EN and
EQ boost
R/W
0
7
Reserved
R/W
0
6:4
Reserved
R/W
111
3:2
VOD Control
R/W
10
Driver VOD
Control
1:0
Reserved
R/W
00
09 – 10 Reserved
7:0
Reserved
R/W
00000000
11
7:6
DEM_CH3
R/W
00
5:4
DEM_CH2
R/W
00
3:2
DEM_CH1
R/W
00
1:0
DEM_CH0
R/W
00
7:3
Reserved
R/W
00000
2:1
Reserved
R/W
11
0
OOB Signal Detect Control R/W
7:5
Reserved
R/W
000
4
Channel Enable
R/W
1
3:1
Reserved
R/W
000
0
Boost[8]
R/W
0
12
13
De-Emphasis
Control
OOB Signal
Detect Control
Channel 3
EN and EQ
Control
0
Description
Select port/channel [1:0] to report status
in REG_01 to REG_03
00 = port0 (CH0)
01 = port1 (CH1)
10 = port2 (CH2)
11 = port3 (CH3)
Channel EN and EQ Boost through pins
or smbus REG_13 to REG_1A
0 = Channel EN[3:0] and EQ BST[2:0]
boost set by external pins
1 = Allow channel EN and EQ boost to be
set by SMBus Register bits: REG_13 to
REG_1A
00 = 0.6 Vp-p
01 = 0.8 Vp-p
10 = 1.0 Vp-p
11 = 1.2 Vp-p
00 = 0 dB
01 = -3 dB
10 = -6 dB
11 = -9 dB
0 = OOB signal detect enabled
1 = OOB signal detect disabled
0 = Disabled
1 = Enabled
See Table 5
14
EQ Control
Channel 3
7:0
Boost[7:0]
R/W
00000000 See Table 5
15
Channel 2
EN and EQ
Control
7:5
Reserved
R/W
000
4
Channel Enable
R/W
1
3:1
Reserved
R/W
000
0 = Disabled
1 = Enabled
0
Boost[8]
R/W
0
16
EQ Control
Channel 2
7:0
Boost[7:0]
R/W
00000000 See Table 5
17
Channel 1
EN and EQ
Control
7:5
Reserved
R/W
000
4
Channel Enable
R/W
1
3:1
Reserved
R/W
000
0
Boost[8]
R/W
0
7:0
Boost[7:0]
R/W
00000000 See Table 5
18
www.ti.com
EQ Control
Channel 1
14
See Table 5
0 = Disabled
1 = Enabled
See Table 5
19
1A
REG Name
Bit(s)
Field
Type
Default
(binary)
Channel 0
EN and EQ
Control
7:5
Reserved
R/W
000
4
Channel Enable
R/W
1
3:1
Reserved
R/W
000
0
Boost[8]
R/W
0
7:0
Boost[7:0]
R/W
00000000 See Table 5
EQ Control
Channel 0
DS100BR410
ADD
(hex)
Description
0 = Disabled
1 = Enabled
See Table 5
TABLE 5. Boost / EQ SMBus Register: 16 levels - recommended settings
Boost Register Bits
Result
bit[8]
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
0
0
0
0
0
0
0
0
0
000'h - 2.7 dB (BST_[2:0]=000)
0
0
0
0
0
0
0
0
1
001'h - 7.3 dB (BST_[2:0]=001)
0
0
0
0
0
0
0
1
0
002'h - 10.3 dB
0
0
0
0
0
0
0
1
1
003'h - 12.2 dB (BST_[2:0]=010)
0
0
0
0
0
0
1
1
1
007'h - 16.6 dB (BST_[2:0]=011)
0
0
0
0
1
0
1
0
1
015'h - 17 dB
0
0
0
0
0
1
0
1
1
00B'h - 19.2 dB
0
0
0
0
0
1
1
1
1
00F'h - 20.6 dB (BST_[2:0]=100)
0
0
1
0
1
0
1
0
1
055'h - 21.9 dB
0
0
0
0
1
1
1
1
1
01F'h - 24.8 dB (BST_[2:0]=101)
0
0
0
1
0
1
1
1
1
02F'h - 27.6 dB (BST_[2:0]=110)
0
0
0
1
1
1
1
1
1
03F'h - 28.9 dB (BST_[2:0]=111)
0
1
0
1
0
1
0
1
0
0AA'h - 31.3 dB
0
0
1
1
1
1
1
1
1
07F'h - 33.3 dB
0
1
0
1
1
1
1
1
1
0BF'h - 35.7 dB
0
1
1
1
1
1
1
1
1
0FF'h - 37 dB
15
bit[0] @ 5.5 GHz
www.ti.com
DS100BR410
close to the signal via for a low inductance return current path
is recommended. When the via structure is associated with
stripline trace and a thick board, further optimization such as
back drilling is often used to reduce the high frequency effects
of via stubs on the signal path. To minimize cross-talk coupling, it is recommended to have >3X gap spacing between
the differential pairs. For example, if the trace width is 5 mils
with 5 mils spacing – 100Ω differential impedance (closely
coupled). The gap spacing between the differential pairs
should be >15 mils.
Applications Information
GENERAL RECOMMENDATIONS
The DS100BR410 is a high performance circuit capable of
delivering excellent performance up to 10.3125 Gbps. Careful
attention must be paid to the details associated with highspeed design as well as providing a clean power supply. Refer
to the LVDS Owner's Manual for more detailed information on
high speed design tips to address signal integrity design issues.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS100BR410 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1uF or 0.01 μF bypass capacitor should be connected to each VDD pin such that
the capacitor is placed as close as possible to the
DS100BR410. Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with capacitance in the range of 2.2 μF to 10 μF should
be incorporated in the power supply bypassing design as well.
These capacitors can be either tantalum or an ultra-low ESR
ceramic.
UNUSED CHANNEL
It is recommended to disable the unused channel (EN[3:0] =
LOW). The power consumption of the device is reduced when
the channel is disabled.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The high speed CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route
differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided
if possible. If vias must be used, they should be used sparingly
and must be placed symmetrically for each side of a given
differential pair. Route the differential signals away from other
signals and noise sources on the printed circuit board. See
AN-1187 for additional information on LLP packages.
Impedance discontinuities at the differential via can be minimized or eliminated by increasing the swell around each via
hole. To further improve the signal quality, a ground via placed
www.ti.com
16
DS100BR410
Typical Performance Curves Characteristics
30122428
FIGURE 8. Power Dissipation (PD) vs. Output Differential Voltage (VOD)
30122429
FIGURE 9. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Supply Voltage (VDD)
30122430
FIGURE 10. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Temperature
17
www.ti.com
DS100BR410
Typical Performance Eye Diagrams Characteristics
30122431
FIGURE 11. Test Setup Connections Diagram
30122432
FIGURE 12. 12 meters, 30–AWG Cable at 10.3125 Gbps,
BST[2:0] = 111, DE_SEL = 0 dB
30122433
FIGURE 13. 40 inches, 6–mil FR4 Trace at 10.3125 Gbps,
BST[2:0] = 101, DE_SEL = 0 dB
www.ti.com
18
DS100BR410
Physical Dimensions inches (millimeters) unless otherwise noted
48-pin LLP Package (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch)
Package Number SQA48A
19
www.ti.com
DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis
Driver
Notes
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated