DS64EV400
Programmable Quad Equalizer
General Description
Features
The DS64EV400 programmable quad equalizer provides
compensation for transmission medium losses and reduces
the medium-induced deterministic jitter for four NRZ data
channels. The DS64EV400 is optimized for operation up to
10 Gbps for both cables and FR4 traces. Each equalizer
channel has eight levels of input equalization that can be programmed by three control pins, or individually through a Serial
Management Bus (SMBus) interface.
The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and balanced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs. The
DS64EV400 is available in a 7 mm x 7 mm 48-pin leadless
LLP package. Power is supplied from either a 2.5V or 3.3V
supply.
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Equalizes up to 24 dB loss at 10 Gbps
Equalizes up to 22 dB loss at 6.4 Gbps
8 levels of programmable equalization
Settable through control pins or SMBus interface
Operates up to 10 Gbps with 30” FR4 traces
Operates up to 6.4 Gbps with 40” FR4 traces
0.175 UI residual deterministic jitter at 6.4 Gbps with 40”
FR4 traces
Single 2.5V or 3.3V power supply
Signal Detect for individual channels
Standby mode for individual channels
Supports AC or DC-Coupling with wide input commonmode
Low power consumption: 375 mW Typ at 2.5V
Small 7 mm x 7 mm 48-pin LLP package
9 kV HBM ESD Rating
-40 to 85°C operating temperature range
Simplified Application Diagram
30032024
© 2008 National Semiconductor Corporation
300320
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DS64EV400 Programmable Quad Equalizer
April 18, 2008
DS64EV400
Pin Descriptions
Pin Name
Pin #
I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0–
1
2
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 6.
IN_1+
IN_1–
4
5
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 6.
IN_2+
IN_2–
8
9
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 6.
IN_3+
IN_3–
11
12
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 6.
OUT_0+
OUT_0–
36
35
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to VDD and OUT_0- to VDD.
OUT_1+
OUT_1–
33
32
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to VDD and OUT_1- to VDD.
OUT_2+
OUT_2–
29
28
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to VDD and OUT_2- to VDD.
OUT_3+
OUT_3–
26
25
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to VDD and OUT_3- to VDD.
I, LVCMOS
BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is
internally pulled high. BST_1 and BST_0 are internally pulled low.
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
37
14
23
DEVICE CONTROL
EN0
44
I, LVCMOS
Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN1
42
I, LVCMOS
Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN2
40
I, LVCMOS
Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN3
38
I, LVCMOS
Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
FEB
21
I, LVCMOS
Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]
pins. When held low, the equalizer boost setting is controlled by SMBus (see Table 1) register
bits. FEB is internally pulled High.
SD0
45
O, LVCMOS
Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.
SD1
43
O, LVCMOS
Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.
SD2
41
O, LVCMOS
Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.
SD3
39
O, LVCMOS
Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.
3, 6, 7,
10, 13,
15, 46
Power
GND
22, 24,
27, 30,
31, 34
Power
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
DAP
PAD
Power
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
POWER
VDD
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VDD = 2.5V ± 5% or 3.3V ± 10%. VDD pins should be tied to VDD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes.
2
Pin #
I/O, Type
Description
SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS
SDA
SDC
CS
18
17
16
I/O, LVCMOS Data input/output (bi-directional). Internally pulled high.
I, LVCMOS Clock input. Internally pulled high.
I, LVCMOS Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When
pulled low, access to the equalizer SMBus registers are disabled. Please refer to “SMBus
configuration Registers” section for detail information.
Other
Reserv
19, 20
47,48
Reserved. Do not connect.
Note: I = Input O = Output
Connection Diagram
30032026
Ordering Information
NSID
Package Type, Qty Size
Package ID
DS64EV400SQ
48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 250
SQA48D
DS64EV400SQX
48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 2500
SQA48D
3
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DS64EV400
Pin Name
DS64EV400
Absolute Maximum Ratings (Note 1)
ESD Rating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
HBM, 1.5 kΩ, 100 pF
CML Inputs
Thermal Resistance
θJA, No Airflow
Supply Voltage (VDD)
CMOS Input Voltage
CMOS Output Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4
Seconds)
−0.5V to +4.0V
−0.5V + 4.0V
−0.5V to 4.0V
−0.5V to 4.0V
> 9 kV
> 250V
30°C/W
Recommended Operating
Conditions
+150°C
−65°C to +150°C
+260°C
Supply Voltage (note 9)
VDD2.5 to GND
VDD3.3 to GND
Ambient Temperature
Min
Typ
Max Units
2.375
3.0
−40
2.5
3.3
25
2.625
3.6
+85
V
V
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(note 2)
Max
Units
490
700
mW
100
mW
490
mW
POWER
P
Power Supply Consumption
Device Output Enabled
(EN [0–3] = High), VDD3.3
Device Output Disable
(EN [0–3] = Low), VDD3.3
P
N
Power Supply Consumption
Supply Noise Tolerance (Note 4)
Device Output Enabled
(EN [0–3] = High), VDD2.5
360
Device Output Disable
(EN [0–3] = Low), VDD2.5
30
50 Hz — 100 Hz
100 Hz — 10 MHz
10 MHz — 1.6 GHz
100
40
10
mVP-P
mVP-P
mVP-P
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
VDD3.3
2.0
VDD3.3
V
VDD2.5
1.6
VDD2.5
V
-0.3
0.8
V
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOL = 3mA
IIN
Input Leakage Current
VIN = VDD
IOH = -3mA, VDD3.3
2.4
IOH = -3mA, VDD2.5
2.0
VIN = GND
IIN-P
Input Leakage Current with
Internal Pull-Down/Up Resistors
V
0.4
V
+15
μA
μA
-15
VIN = VDD, with internal pull-down
resistors
VIN = GND, with internal pull-up
resistors
+120
μA
μA
-20
SIGNAL DETECT
SDH
Signal Detect ON Threshold Level Default input signal level to assert
SD pin, 6.4 Gbps
70
mVp-p
SDI
Signal Detect OFF Threshold
Level
40
mVp-p
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Default input signal level to deassert SD, 6.4 Gbps
4
Parameter
Conditions
Min
Typ
(note 2)
Max
Units
1600
mVP-P
CML RECEIVER INPUTS (IN_n+, IN_n-)
VTX
Source Transmit Launch Signal
Level (IN diff)
AC-Coupled or DC-Coupled
Requirement, Differential
measurement at point A.
Figure 1
VINTRE
Input Threshold Voltage
Differential measurement at
point B. Figure 1
VDDTX
Supply Voltage of Transmitter to
EQ
DC-Coupled Requirement
(Note 10)
VICMDC
Input Common Mode Voltage
DC-Coupled Requirement,
Differential measurement at point
A. Figure 1, (Note 7)
400
mVP-P
120
1.6
VDD
V
VDDTX –
0.8
VDDTX –
0.2
V
RLI
Differential Input Return Loss
100 MHz – 3.2 GHz, with fixture’s
effect de-embedded
RIN
Input Resistance
Differential across IN+ and IN-,
Figure 6.
85
100
115
Ω
Output Differential Voltage Level
(OUT diff)
Differential measurement with
OUT+ and OUT- terminated by
50Ω to GND, AC-Coupled
Figure 2
500
620
725
mVP-P
Output Common Mode Voltage
Single-ended measurement DCCoupled with 50Ω terminations
(Note 7)
10
dB
CML OUTPUTS (OUT_n+, OUT_n-)
VOD
VOCM
tR, tF
Transition Time
VDD– 0.2
V
20% to 80% of differential output
voltage, measured within 1” from
output pins. Figure 2, (Note 7)
20
42
RO
Output Resistance
Single ended to VDD
RLO
Differential Output Return Loss
100 MHz – 1.6 GHz, with fixture’s
effect de-embedded. IN+ = static
high.
VDD– 0.1
50
60
ps
58
Ω
10
dB
240
ps
240
ps
tPLHD
Differential Low to High
Propagation Delay
tPHLD
Differential High to Low
Propagation Delay
Propagation delay measurement
at 50% VO between input to
output, 100 Mbps. Figure 3,
(Note 7)
tCCSK
Inter Pair Channel to Channel
Skew
Difference in 50% crossing
between channels
7
ps
tPPSK
Part to Part Output Skew
Difference in 50% crossing
between outputs
20
ps
UIP-P
EQUALIZATION
DJ1
DJ2
DJ3
DJ4
RJ
Residual Deterministic Jitter
at 10 Gbps
30” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (27-1)
pattern. (Note 6)
0.20
Residual Deterministic Jitter
at 6.4 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (27-1)
pattern. (Note 5, 6)
0.17
0.26
UIP-P
Residual Deterministic Jitter
at 5 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)
pattern. (Note 5, 6)
0.12
0.20
UIP-P
Residual Deterministic Jitter
at 2.5 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)
pattern. (Note 5, 6)
0.1
0.16
UIP-P
Random Jitter
(Note 7, 8)
0.5
5
psrms
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DS64EV400
Symbol
DS64EV400
Symbol
Parameter
Conditions
Min
Typ
(note 2)
Max
Units
SIGNAL DETECT and ENABLE TIMING
tZISD
Input OFF to ON detect — SD
Output High Response Time
tIZSD
Input ON to OFF detect — SD
Output Low Response Time
tOZOED
tZOED
Response time measurement at
VIN to SD output, VIN = 800 mVP-P,
100 Mbps, 40” of 6 mil microstrip
FR4
(Figure 1, 4), (Note 7)
EN High to Output ON Response
Time
Response time measurement at
EN input to VO, VIN = 800 mVP-P,
EN Low to Output OFF Response 100 Mbps, 40” of 6 mil microstrip
FR4
Time
(Figure 1, 5), (Note 7)
35
ns
400
ns
150
ns
5
ns
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 7: Measured with clock-like {11111 00000} pattern.
Note 8: Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see point C of Figure
1; JIN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
Note 9: The VDD2.5 is VDD = 2.5V ± 5% and VDD3.3 is VDD = 3.3V ± 10%.
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6
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
VDD
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SDC
RTERM
External Termination Resistance VDD3.3,
pull to VDD = 2.5V ± 5% OR 3.3V ± (Note 10, 11, 12)
10%
VDD2.5,
(Note 10, 11, 12)
2.1
(Note 10)
4
mA
2.375
3.6
V
-200
+200
µA
-15
(Note 10, 11)
µA
10
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS (Figure 7)
FSMB
Bus Operating Frequency
TBUF
Bus Free Time Between Stop and
Start Condition
(Note 13)
10
4.7
µs
THD:STA
Hold time after (Repeated) Start
At IPULLUP, Max
Condition. After this period, the first
clock is generated.
4.0
µs
TSU:STA
Repeated Start Condition Setup
Time
4.7
µs
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
250
TTIMEOUT
Detect Clock Low Timeout
TLOW
Clock Low Period
THIGH
Clock High Period
(Note 13)
TLOW:SEXT
Cumulative Clock Low Extend
Time (Slave Device)
(Note 13)
tF
Clock/Data Fall Time
tR
Clock/Data Rise Time
tPOR
Time in which a device must be
operational after power-on reset
(Note 13)
(Note 13)
25
100
ns
35
4.7
4.0
kHz
ms
µs
50
µs
2
ms
(Note 13)
300
ns
(Note 13)
1000
ns
500
ms
Note 10: Recommended value. Parameter not tested in production.
Note 11: Recommended maximum capacitance load per bus segment is 400pF.
Note 12: Maximum termination voltage should be identical to the device supply voltage.
Note 13: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
7
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DS64EV400
Electrical Characteristics — Serial Management Bus Interface
DS64EV400
SMBus Transactions
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
Writing a Register
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drive the 8-bit data byte.
7. The Device drives an ACK bit (“0”).
8. The Host drives a STOP condition.
9. The Host de-selects the device by driving its SMBus CS
signal Low.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drives a START condition.
7. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
8. The Device drives an ACK bit “0”.
9. The Device drives the 8-bit data value (register contents).
10. The Host drives a NACK bit “1”indicating end of the
READ transfer.
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS
signal Low.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Please see Table 1 for more information.
System Management Bus (SMBus)
and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the Chip
Select signal is required. Holding the CS pin High enables
the SMBus port allowing access to the configuration registers.
Holding the CS pin Low disables the device's SMBus allowing
communication from the host to other slave devices on the
bus. In the STANDBY state, the System Management Bus
remains active. When communication to other devices on the
SMBus is active, the CS signal for the DS32EV400s must be
driven Low.
The address byte for all DS64EV400s is AC'h. Based on the
SMBus 2.0 specification, the DS64EV400 has a 7-bit slave
address of 1010110'b. The LSB is set to 0'b (for a WRITE),
thus the 8-bit value is 1010 1100'b or AC'h.
The SDC and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon
SMBus loading and speed. Note, these pins are not 5V tolerant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SDC is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SDC is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High
indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
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8
Name
Address Default Type Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Status
0x00
0x00
RO
ID Revision
Status
0x01
0x00
RO
EN1
Boost 1
SD3
SD2
SD1
SD0
EN0
Boost 0
Status
0x02
0x00
RO
EN3
Boost 3
Enable/
Boost
(CH 0, 1)
0x03
0x44
RW
EN1 Output Boost Control for CH1
0:Enable
000 (Min Boost)
1:Disable
001
010
011
100 (Default)
101
110
111 (Max Boost)
EN2
EN0 Output Boost Control for CH0
0:Enable
000 (Min Boost)
1:Disable
001
010
011
100 (Default)
101
110
111 (Max Boost)
Boost 2
Enable/
Boost
(CH 2, 3)
0x04
0x44
RW
EN3 Output Boost Control for CH3
0:Enable
000 (Min Boost)
1:Disable
001
010
011
100 (Default)
101
110
111 (Max Boost)
EN2 Output Boost Control for CH2
0:Enable
000 (Min Boost)
1:Disable
001
010
011
100 (Default)
101
110
111 (Max Boost)
Signal
Detect
0x05
0x00
RW
SD3 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
SD2 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
SD1 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
SD0 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
Signal
Detect
0x06
0x00
RW
SD3 OFF Threshold
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
SD2 OFF Threshold
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
SD1 OFF Threshold
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
SD0 OFF Threshold
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
SMBus
Control
0x07
0x00
RW
Reserved
Output
Level
0x08
0x78
RW
Reserved
SMBus
Enable
Control
0: Disable
1: Enable
Output Level:
00: 400 mVP-P
01: 540 mVP-P
10: 620 mVP-P
(Default)
11: 760 mVP-P
Reserved
Note: RO = Read Only, RW = Read/Write
9
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DS64EV400
TABLE 1. SMBus Register Address
DS64EV400
30032027
FIGURE 1. Test Setup Diagram
30032002
FIGURE 2. CML Output Transition Times
30032003
FIGURE 3. Propagation Delay Timing Diagram
30032004
FIGURE 4. Signal Detect (SD) Delay Timing Diagram
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10
DS64EV400
30032005
FIGURE 5. Enable (EN) Delay Timing Diagram
300320017
FIGURE 6. Simplified Receiver Input Termination Circuit
300320018
FIGURE 7. SMBus Timing Parameters
11
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DS64EV400
DATA CHANNELS
The DS64EV400 provides four data channels. Each data
channel consists of an equalizer stage, a limiting amplifier, a
DC offset correction block, and a CML driver as shown in Figure 8.
DS64EV400 Functional
Descriptions
The DS64EV400 is a programmable quad equalizer optimized for operation up to 10 Gbps for backplane and cable
applications.
30032006
FIGURE 8. Simplified Block Diagram
EQUALIZER BOOST CONTROL
Each data channel support eight programmable levels of
equalization boost. The state of the FEB pin determines how
the boost settings are controlled. If the FEB pin is held High,
then the equalizer boost setting is controlled by the Boost Set
pins (BST_[2:0]) in accordance with Table 2. If this programming method is chosen, then the boost setting selected on the
Boost Set pins is applied to all channels. When the FEB pin
is held Low, the equalizer boost level is controlled through the
SMBus. This programming method is accessed via the appropriate SMBus registers (see Table 1). Using this approach,
equalizer boost settings can be programmed for each channel
individually. FEB is internally pulled High (default setting);
therefore if left unconnected, the boost settings are controlled
by the Boost Set pins (BST_[0:2]). The eight levels of boost
settings enables the DS64EV400 to address a wide range of
media loss and data rates.
DEVICE STATE AND ENABLE CONTROL
The DS64EV400 has an enable feature on each data channel
which provides the ability to control device power consumption. This feature can be controlled either an Enable Pin
(EN_n) with Reg 07 = 00'h (default value), or by the Enable
Control Bit register which can be configured through the SMBus port (see Table 1 and Table 3 for detail register information), which require setting Reg 07 = 01'h and changing
register value of Reg 03, 04. If the Enable is activated using
either the external EN_n pin or SMBUS register, the corresponding data channel is placed in the ACTIVE state and all
device blocks function as described. The DS64EV400 can also be placed in STANDBY mode to save power. In the
STANDBY mode only the control interface including the SMBus port, as well as the signal detection circuit remain active.
TABLE 3. Controlling Device State
Register 07[0] ENn Pin
(SMBus)
(CMOS)
TABLE 2. EQ Boost Control Table
6 mil
24 AWG Channel
Microstri Twin-AX
Loss at
p FR4
cable
3.2 GHz
Trace
length (m)
(dB)
Length
(m)
0
0
0
Channel
Loss at 5
GHz (dB)
BST_N
[2, 1, 0]
0
000
CH 0:
Reg. 03 bit 3
CH 1:
Reg. 03 bit 7
CH 2:
Reg. 04 bit 3
CH 3:
Reg. 04 bit 7
(EN Control)
Device State
5
2
5
6
001
0 : Disable
1
X
ACTIVE
10
3
7.5
10
010
0 : Disable
0
X
STANDBY
15
4
10
14
011
1 : Enable
X
0
ACTIVE
20
5
12.5
18
100
(Default)
1 : Enable
X
1
STANDBY
25
6
15
21
101
30
7
17
24
110
40
10
22
30
111
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SIGNAL DETECT
The DS64EV400 features a signal detect circuit on each data
channel. The status of the signal of each channel can be determined by either reading the Signal Detect bit (SDn) in the
SMBus registers (see Table 1) or by the state of each SDn
12
TABLE 5. Output Level Control Settings
All Channels : Bit All Channels : Bit
3
2
TABLE 4. Signal Detect Threshold Values
Channel 0:
Bit 1
Channel 1:
Bit 3
Channel 2:
Bit 5
Channel 3:
Bit 7
Channel 0:
Bit 0
Channel 1:
Bit 2
Channel 2:
Bit 4
Channel 3:
Bit 6
SD_OFF
Threshold
Register 06
(mV)
SD_ON
Threshold
Register 05
(mV)
0
0
40 (Default)
70 (Default)
0
1
30
55
1
0
55
90
1
1
45
75
Output Level
Register 08
(mVP-P)
0
0
0
1
400
540
1
0
620 (Default)
1
1
760
AUTOMATIC ENABLE FEATURE
It may be desirable to place unused channels in power-saving
Standby mode. This can be accomplished by connecting the
Signal detect (SDn) pin to the Enable (ENn) pin for each
channel (See Figure 9). In order for this option to function
properly, the register value for Reg. 07 should be 00'h (default
value). If an input signal swing applied to a data channel is
above the voltage level threshold as shown in Table 4, then
the SDn output pin is asserted High. If the SDn pin is connected to the ENn pin, this will enable the equalizer, limiting
amplifier, and output buffer on the data channels; thus the
DS64EV400 will automatically enter the ACTIVE state. If the
input signal swing falls below the SD_OFF threshold level,
then the SDn output will be asserted Low, causing the channel
to be placed in the STANDBY state.
OUTPUT LEVEL CONTROL
The output amplitude of the CML drivers for each channel can
be controlled via the SMBus (see Table 1). The default output
13
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DS64EV400
level is 620 mVp-p. The following Table presents the output
level values supported:
pin. An output logic high indicates the presence of a signal
that has exceeded the ON threshold value (called SD_ON).
An output logic Low means that the input signal has fallen
below the OFF threshold value (called SD_OFF). These values are programmed via the SMBus (Table 1). If not programmed via the SMBus, the thresholds take on the default
values as shown in Table 4. The Signal Detect threshold values can be changed through the SMBus. All threshold values
specified are DC peak-to-peak differential signals (positive
signal minus negative signal) at the input of the device.
DS64EV400
DS64EV400 Applications
Information
30032007
FIGURE 9. Automatic Enable Configuration
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01μF bypass capacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the DS64EV400.
Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with capacitance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic and
should be placed as close as possible to the DS64EV400.
UNUSED EQUALIZER CHANNELS
It is recommended to put all unused channels into standby
mode.
GENERAL RECOMMENDATIONS
The DS64EV400 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid
to the details associated with high-speed design as well as
providing a clean power supply. Refer to the LVDS Owner's
Manual for more detailed information on high speed design
tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML lines
exclusively on one layer of the board, particularly for the input
traces. The use of vias should be avoided if possible. If vias
must be used, they should be used sparingly and must be
placed symmetrically for each side of a given differential pair.
Route the CML signals away from other signals and noise
sources on the printed circuit board. See AN-1187 for additional information on LLP packages.
DC COUPLING
The DS64EV400 supports both AC coupling with external ac
coupling capacitor, and DC coupling to its upstream driver, or
downstream receiver. With DC coupling, users must ensure
the input signal common mode is within the range of the electrical specification VICMDC and the device output is terminated
with 50 Ω to VDD.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS64EV400 is provided with an adequate power supply.
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14
DS64EV400
Typical Performance Eye Diagrams and Curves
30032009
30032008
Figure 9. Equalized Signal
(40 In FR4, 5Gbps, PRBS7, 0x07 Setting)
Figure 8. Equalized Signal
(40 In FR4, 2.5Gbps, PRBS7, 0x07 Setting)
30032011
30032010
Figure 11. Equalized Signal
(40 In FR4, 6.4 Gbps, PRBS31, 0x06 Setting)
Figure 10. Equalized Signal
(40 In FR4, 6.4 Gbps, PRBS7, 0x06 Setting)
30032012
Figure 12. Equalized Signal
(30 In FR4, 10 Gbps, PRBS7, 0x06 Setting)
30032013
Figure 13. Equalized Signal
(10m 24 AWG Twin-Ax Cable, 6.4 Gbps, PRBS7, 0x07 Setting)
15
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DS64EV400
30032014
Figure 14. Equalized Signal
(32 In Tyco XAUI Backplane, 6.25 Gbps, PRBS7, 0x06 Setting)
30032015
30032016
Figure 15. DJ vs. EQ Setting (10 Gbps)
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Figure 16. DJ vs EQ Setting (6.4 Gbps)
16
DS64EV400
Physical Dimensions inches (millimeters) unless otherwise noted
48-pin LLP Package (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch)
Order Number DS64EV400SQ
Package Number SQA48D
17
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DS64EV400 Programmable Quad Equalizer
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