UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 DUAL CHANNEL SYNCHRONIZED CURRENT-MODE PWM FEATURES • • • • • • • • • • DESCRIPTION Single Oscillator Synchronizes Two PWMs 150-µA Startup Supply Current 2-mA Operating Supply Current Operation to 1 MHz Internal Soft-Start Full-Cycle Fault Restart Internal Leading-Edge Blanking of the Current Sense Signal 1-A Totem Pole Outputs 75-ns Typical Response from Current Sense to Output 1.5% Tolerance Voltage Reference N PACKAGE (TOP VIEW) SYNC CT RT FB1 COMP1 CS1 OUT1 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC REF ENABLE2 FB2 COMP2 CS2 OUT2 PWRGND The UCC3810 is a high-speed BiCMOS controller integrating two synchronized pulse width modulators for use in off-line and dc-to-dc power supplies. The UCC3810 family provides perfect synchronization between two PWMs by usin g the same oscillator. The oscillator’s sawtooth waveform can be used for slope compensation if required. Using a toggle flip-flop to alternate between modulators, the UCC3810 ensures that one PWM does not slave, interfere, or otherwise affect the other PWM. This toggle flip- flop also ensures that each PWM is limited to 50% maximum duty cycle, insuring adequate off-time to reset magnetic elements. This device contains many of the same elements of the UC3842 current mode controller family, combined with the enhancements of the UCC3802. This minimizes power supply parts count. Enhancements include leading edge blanking of the current sense signals, full cycle fault restart, CMOS output drivers, and outputs which remain low even when the supply voltage is removed. PW PACKAGE (TOP VIEW) SYNC CT RT FB1 COMP1 CS1 OUT1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC REF ENABLE2 FB2 COMP2 CS2 OUT2 PWRGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2007, Texas Instruments Incorporated UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGED DEVICES (1) TJ (1) SOP (DW) PDIP (N) –40°C to 85°C UCC2810DW (16) UCC2810N (16) 0°C to 70°C UCC3810DW (16) UCC3810N (16) All packages are available taped and reeled (indicated by the R suffix on the device type e.g., UCC2810JR) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) UNIT voltage (3) VCC Supply ICC Supply current 11V 20mA Output peak current, OUT1, OUT2, 5% duty cycle ±1A Output energy, OUT1, OUT2, capacitive load 20 µJ 20µJ Analog inputs, FB1, FB2, CS1, CS2, SYNC TJ Operating junction temperature Tstg Storage temperature range –0.3 to 6.3V 150°C –65 to 150°C Lead temperature (soldering, 10 sec) (1) (2) (3) 300°C Currents are positive into, negative out of the specified terminal. All voltages are with respect to GND. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In normal operation, VCC is powered through a current-limiting resistor. Absolute maximum of 11 V applies when driven from a low impedance such that the VCC current does not exceed 20 mA. BLOCK DIAGRAM REF FB1 COMP1 CS1 CS2 VCC 15 15 5 6 11 16 Leading Edge Blanking Leading Edge Blanking Over-Current Comparator 1.5 V VCC OK 12.5 V 2.5 V VCC S Q Error Amp 1 55 kW Voltage Ref REF OK S Q 100 kW 7 OUT1 10 OUT2 R 1V R 4V 0.5 V S Q R Error Amp 2 2.5 V Full Cycle Soft Start + − S Q R R 55 kW τ − 5ms 100 kW 35 mA 2 1V Oscillator 13 12 1 2 3 14 9 8 FB2 COMP2 SYNC CT RT ENABLES PWRGND GND VDG−92062−1 2 Submit Documentation Feedback UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS All parameters are the same for both channels, –40°C ≤ TA ≤ 85°C for the UCC2810, 0°C ≤ TA ≤ 70°C for the UCC3810, VCC = 10 V (1) ; RT = 150 kΩ, CT = 120 pF; no load; TA = TJ; (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX 4.925 5.000 5.075 4.85 5.00 5.10 5 30 UNIT REFERENCE VCC TJ = 25°C Output voltage IO(SC) TJ = full range, 0 mA ≤ IREF ≤ 5 mA Load regulation 0 mA ≤ IREF ≤ 5 mA Line regulation UVLO stop threshold voltage, 0.5 V ≤ VCC ≤ VSHUNT Output noise voltage (2) 10Hz <f< 10 kHz, TJ = 25°C Long term stability (2) TA = 125°C, 1000 hours mV 12 Output short circuit current V 235 µV 5 mV -8 -25 mA OSCILLATOR fOSC Oscillator frequency (3) RT = 30 kΩ, CT = 120 pF 860 980 1100 RT = 150 kΩ, CT = 120 pF 190 220 250 Temperature stability (2) kHz 2.5% Peak voltage 2.5 Valley voltage 0.05 Peak-to-peak amplitude SYNC threshold voltage SYNC input current 2.25 2.45 2.65 0.80 1.65 2.20 SYNC = 5 V 30 V µA ERROR AMPLIFIER VFB FB input voltage IFB FB input bias current COMP = 2.5 V 2.44 Open loop voltage gain 60 2.50 2.56 V ±1 µA 73 dB 2 MHz fGAIN Unity gain bandwidth (2) ISINK Sink current, COMP FB = 2.7 V, COMP = 1 V 0.3 1.4 3.5 ISRCE Source current, COMP FB = 1.8 V, COMP = 4 V -0.2 -0.5 -0.8 Minimum duty cycle COMP = 0 V Soft-start rise time, COMP FB = 1.8 V, Rise from 0.5 V to (REF – 1.5 V) mA 0% 5 ms CURRENT SENSE Gain (4) Maximum input ICS signal (5) COMP = 5 V 1.20 1.55 0.9 1.0 Input bias current, CS CS steps from 0 V to 1.2 V, COMP = 2.5 V Propagation delay time (CS to OUT) COMP-to-CS offset voltage CS = 0 V V nA ns 1.35 1.55 1.85 0.45 0.90 1.35 V For UCC3810, adjust VCC above the start threshold before setting at 10 V. Ensured by design. Not production tested. fOSC = Oscillator frequency is twice the output frequency. A= (4) (5) (6) 1.1 ±200 55 Overcurrent threshold voltage, CS (3) V/V 75 Blank time, CS (6) (1) (2) 1.80 4 RT ´ CT DVCOMP DVCS Current sense gain A is defined by: , 0 V ≤ VCS ≤ 0.8 V. Parameter measured at trip point of latch with FB = 0 V. CS blank time is measured as the difference between the minimum non-zero on-time and the CS-to-OUT delay. Submit Documentation Feedback 3 UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) All parameters are the same for both channels, –40°C ≤ TA ≤ 85°C for the UCC2810, 0°C ≤ TA ≤ 70°C for the UCC3810, VCC = 10 V ; RT = 150 kΩ, CT = 120 pF; no load; TA = TJ; (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM Maximum duty cycle (2) Minimum on-time RT = 150 kΩ, CT = 120 pF 45% 49% 50% RT = 30 kΩ, CT = 120 pF 40% 45% 48% CS = 1.2 V, COMP = 5 V 130 ns OUTPUT VOL Low-level output voltage IOUT = 20 mA 0.12 0.42 IOUT = 200 mA 0.48 1.10 0.7 1.2 IOUT = –20 mA 0.15 0.42 IOUT = –200 mA 1.2 2.3 IOUT = 20 mA, VCC = 0 V VOH High-level output voltage (VCC – OUT) tR Rise time, OUT COUT = 1 nF 20 50 tF Fall time, OUT COUT = 1 nF 30 60 V ns UNDERVOLTAGE LOCKOUT (UVLO) Start threshold voltage 9.6 11.3 13.2 Stop threshold voltage 7.1 8.3 9.5 Start-to-stop hysteresis ENABLE2 input bias current ENABLE2 = 0 V ENABLE2 input threshold voltage V 1.7 3.0 4.7 -20 -35 -55 µA 0.80 1.53 2.00 V 0.15 0.25 2 3 OVERALL Startup current VCC < Start threshold voltage Operating supply current, outputs off VCC = 10 V, FB = 2.75 V VCC = 10 V, CS = 0 V, FB = 0 V, RT = 150 kΩ 3.2 5.1 VCC = 10 V, CS = 0 V, FB = 0 V, RT = 30 kΩ 8.5 14.5 11.0 12.9 14.0 0.4 1.2 Operating supply current, outputs on VCC internal zener voltage ICC = 10 mA VCC internal zener voltage minus start threshold voltage 4 Submit Documentation Feedback mA V UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION COMP1 5 O COMP2 12 O CS1 6 I CS2 11 I CT 2 O The timing capacitor of the oscillator. Recommended values of CT are between 100 pF and 1 nF. Connect the timing capacitor directly across CT and GND. ENABLE2 14 I A logic input which disables PWM 2 when low. This input has no effect on PWM 1. This input is internally pulled high. In most applications it can be left floating. In unusually noisy applications, the input should be bypassed with a 1-nF ceramic capacitor. This input has TTL compatible thresholds. FB1 4 I FB2 13 I GND 8 – OUT1 7 O OUT2 10 O PWRGND 9 – To separate noise from the critical control circuits, this part has two different ground connections: GND and PWRGND. GND and PWRGND must be electrically connected together. REF 15 O The output of the 5-V reference. Bypass REF to GND with a ceramic capacitor ≥ 0.01-µF for best performance. Low impedance output of the error amplifiers. Current sense inputs to the PWM comparators. These inputs have leading edge blanking. For most applications, no input filtering is required. Leading edge blanking disconnects the CS inputs from all internal circuits for the first 55 ns of each PWM cycle. When used with very slow diodes or in other applications where the current sense signal is unusually noisy, a small current-sense R-C filter may be required. The high impedance inverting inputs of the error amplifiers. To separate noise from the critical control circuits, this part has two different ground connections: GND and PWRGND. GND and PWRGND must be electrically connected together. However, use care to avoid coupling noise into GND. The high-current push-pull outputs of the PWM are intended to drive power MOSFET gates through a small resistor. This resistor acts as both a current limiting resistor and as a damping impedance to minimize ringing and overshoot. RT 3 O The oscillator charging current is set by the value of the resistor connected from RT to GND. This pin is regulated to 1 V, but the actual charging current is 10 V/RT. Recommended values of RT are between 10 kΩ and 470 kΩ. For a given frequency, higher timing resistors give higher maximum duty cycle and slightly lower overall power consumption. SYNC 1 I This logic input can be used to synchronize the oscillator to a free running oscillator in another part. This pin is edge triggered with TTL thresholds, and requires at least a 10-ns-wide pulse. If unused, this pin can be grounded, open circuited, or connected to REF. VCC 16 I The power input to the device. This pin supplies current to all functions including the high current output stages and the precision reference. Therefore, it is critical that VCC be directly bypassed to PWRGND with an 0.1-µF ceramic capacitor. Submit Documentation Feedback 5 UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 APPLICATION INFORMATION TIMING RESISTOR Supply current decreases with increased RT by the relationship: DI CC = 11V RT For more information, see the detailed oscillator block diagram. LEADING EDGE BLANKING AND CURRENT SENSE Figure 1 shows how an external power stage is connected to the UCC3810. The gate of an external power N-channel MOSFET is connected to OUT through a small current-limiting resistor. For most applications, a 10-Ω resistor is adequate to limit peak current and also practical at damping resonances between the gate driver and the MOSFET input reactance. Long gate lead length increases gate capacitance and mandates a higher series gate resistor to damp the R-L-C tank formed by the lead, the MOSFET input reactance, and the device’s driver output resistance. The UCC3810 features internal leading edge blanking of the current-sense signal on both current sense inputs. The blank time starts when OUT rises and continues for 55 ns. During that 55 ns period, the signal on CS is ignored. For most PWM applications, this means that the CS input can be connected to the current-sense resistor as shown in Figure 1. However, high speed grounding practices and short lead lengths are still required for good performance. From Oscillator Over−Current Comparator 1.5 V Power Stage − Soft Start + S R + CS Current Sense Resistor + − One Shot Q Gate Driver OUT R − PWM PWM Comparator Latch Error Amp Figure 1. Detailed Block Diagram OSCILLATOR The UCC3810 oscillator generates a sawtooth wave at CT. The sawtooth rise time is set by the resistor from RT to GND. Since RT is biased at 1 V, the current through RT is 1 V/RT. The actual charging current is 10 times higher. The fall time is set by an internal transistor on-resistance of approximately 100 Ω. During the fall time, all outputs are off and the maximum duty cycle is reduced to below 50%. Larger timing capacitors increase the discharge time and reduce frequency. However, the percentage maximum duty cycle is only a function of the timing resistor RT, and the internal 100-Ω discharge resistance. ERROR AMPLIFIER OUTPUT STAGE The UCC3810 error amplifiers are operational amplifiers with low-output resistance and high-input resistance. The output stage of one error amplifier is shown in Figure 3. This output stage allows the error amplifier output to swing close to GND and as high as one diode drop below 5 V with little loss in amplifier performance. 6 Submit Documentation Feedback UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 APPLICATION INFORMATION (continued) VCC 0.2 V + − I 1V R 10I + Q + RON 9 100 − 2.5 V S − One Shot 3 1 2 RT SYNC RT CT Figure 2. Oscillator 5V VCC COMP Figure 3. Error Amplifier Output Stage Submit Documentation Feedback 7 UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS ERROR AMPLIFER GAIN AND PHASE vs FREQUENCY OSCILLATOR FREQUENCY vs TIMING RESISTANCE 80 1M 60 90 Gain 20 45 0 0 −20 1k 10 k 100 k 1M Phase − ° Gain − dB Fhase 40 Oscillator Frequency − Hz 135 100 k 10 k 10 k 10 M f − Frequency − Hz 100 k RT − Timing Resistor − W Figure 4. Figure 5. OSCILLATOR FREQUENCY vs TEMPERATURE MAXIMUM DUTY CYCLE vs TIMING RESISTANCE 1.2 10 M 50 48 1.1 Duty Cycle − % Oscillator Frequency − MHz 1.15 1.05 1 0.95 46 44 0.9 42 0.85 0.8 −55 −35 −15 5 25 45 65 TA − Temperature − C 85 105 125 40 10 k Figure 6. 8 100 k RT − Timing Resistor − W Figure 7. Submit Documentation Feedback 1M UCC2810 UCC3810 www.ti.com SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) MAXIMUM DUTY CYCLE vs FREQUENCY 10 50 8 48 Duty Cycle − % I CC − Input Current − mA INPUT CURRENT vs OSCILLATOR FREQUENCY 6 Switching 4 2 44 42 Outputs Off 10 k 46 CT = 120 pF 100 k 1M 40 10 k 100 k 1M f − Frequency − Hz f − Frequency − Hz Figure 8. Figure 9. DC Input +12 V OUT +5 V OUT 0.1 mF 16 VCC OPTO1 5 COMP1 OUT1 7 2 3 COMP VCC 5 REF 4 FB1 UCC3810 OPTO2 4 E/A+ CS1 6 12 COMP2 0.1 OUT2 10 HV SUP ENABLE OPTO1 8 I 6 SENSE SET UC39432 GND 7 13 FB2 TTL MONITOR SYNC 0.1 COLL 1 CS2 11 High Voltage Out (Monitor Raster) 1 SYNC REF 15 14 ENABLE2 RT 3 PWR CT GND GND 2 8 0.1 9 2 3 COMP VCC 5 REF 4 E/A+ 0.1 0.1 OPTO2 COLL 1 6 SENSE UC39432 ISET 8 GND 7 VDG−94022 Figure 10. Typical Application Submit Documentation Feedback 9 PACKAGE MATERIALS INFORMATION www.ti.com 30-Mar-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC2810DWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1 UCC3810DWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Mar-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2810DWTR SOIC DW 16 2000 346.0 346.0 33.0 UCC3810DWTR SOIC DW 16 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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