TPS53124 www.ti.com ..................................................................................................................................................... SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 Dual Synchronous Step-Down Controller For Low-Voltage Power Rails FEATURES 1 • • • • • • • • 2 • • DESCRIPTION High Efficiency, Low-Power Consumption D-Cap Mode Enables Fast Transient Response High Initial Reference Accuracy Low Output Ripple Wide Input Voltage Range: 4.5 V to 24 V Output Voltage Range: 0.76 V to 5.5 V Low-Side RDS(on) Loss-less Current Sensing Adaptive Gate Drivers with Integrated Boost Diode Internal 1.2-ms Voltage-Servo Soft Start Built-In 5-V Linear Regulator The TPS53124 is a dual, Adaptive on-time DCAP™ mode synchronous controller. The part enables system designers to cost effectively complete the suite of digital TV power bus regulators with the absolute lowest external component count and lowest standby consumption. The main control loop for the TPS53124 uses the D-CAP™ mode that optimized for low ESR output capacitors such as POSCAP or SP-CAP promises fast transient response with no external compensation. The part provides a convenient and efficient operation with conversion voltages from 4.5 V to 24 V and output voltage from 0.76 V to 5.5 V. The TPS53124 is available in the 24-pin RGE package and in the 28-pin PW package and is specified from -40°C to 85°C ambient temperature range. APPLICATIONS • • • Digital TV Power Supply Networking Home Terminal Digital STB TYPICAL APPLICATION DIAGRAM Input Voltage C9 SGND R5 PGND Q3 Q4 2 1 GND VO1 7 EN2 8 VBST2 9 DRVH2 10 LL2 11 DRVL2 DRVL1 20 PGND2 PGND1 19 L2 3.3uH 3 Power PAD TPS53124RGE (QFN24) 15 16 VIN VREG5 TEST2 14 V5FILT TRIP2 13 PGND 24 DRVH1 22 LL1 21 C3 C2 0.1uF 4.7uF Q1 L1 VO1 3.3uH C4 12 EN1 VBST1 23 17 R6 Q2 1.05 V C1 TRIP1 C6 4.7uF 4 VFB1 VO2 C5 0.1uF 5 VFB2 R1 6 VO2 1.8V R2 R4 TEST1 SGND 18 R3 PGND C7 4.7 uF C8 1 uF PGND SGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DCAP is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPS53124 SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ..................................................................................................................................................... www.ti.com TSSOP-28 APPLICATION DIAGRAM DRVH VIN C3 C2 0.1uF 1 VBST1 2 NC LL1 3 EN1 DRVL1 26 4 VO1 PGND 1 25 5 VFB1 TRIP 1 24 6 NC VIN 23 7 GND Q1 DRVH1 28 4.7uF VO1 27 L1 3.3uH Q2 C1 R1 R3 R2 TPS53124PW VIN C9 VREG 5 22 C7 4.7uF (TSSOP28) 8 TEST1 V5 FILT 21 9 NC TEST2 20 10 VFB2 TRIP2 19 11 VO2 PGND 2 18 EN2 DRVL 2 17 R5 R4 C8 1uF R6 12 LL 2 13 NC 14 VBST2 C4 Q4 3.3uH 16 L2 DRVH 2 15 Q3 C5 0.1uF VO2 4.7uF C6 VIN ORDERING INFORMATION (1) TA -40°C to 85°C (1) 2 PACKAGE ORDERING PART NUMBER PINS OUTPUT SUPPLY Plastic quad TPS53124RGET 24 Tape and Reel Flat pack (QFN) TPS53124RGER 24 Tape and Reel TSSOP TPS53124PWR 28 Tape and Reel TSSOP TPS53124PW 28 Tube ECO PLAN Green (RoHS & no Sb/Br) All packaging options have Cu NIPDAU lead/ball finish. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 TPS53124 www.ti.com ..................................................................................................................................................... SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER Input Voltage Range Output Voltage Range VALUE UNIT VIN,EN1,EN2 -0.3 to 26 VBST1,VBST2 -0.3 to 32 VBST1,VBST2(wrt LLx) -0.3 to 6 V5FILT,VFB1,VFB2,TRIP1,TRIP2,VO1,VO2, TEST1,TEST2 -0.3 to 6 DRVH1, DRVH2 -1 to 32 DRVH1, DRVH2 (wrt LLx) -0.3 to 6 LL1,LL2 -2 to 26 DRVL1,DRVL2,VREG5 -0.3 to 6 PGND1, PGND2 V -0.3 to 0.3 Operating ambient temperature range, TA -40 to 85 Storage Temperature Range, TSTG -55 to 150 Junction Temperature Range, TJ -40 to 150 (1) V °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (2 oz. trace and copper pad with solder) PACKAGE TA <25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING 24-pin QFN 2.33 W 23.3 mW/°C 0.93 W 28-pin TSSOP 0.78 W 7.8 mW/°C 0.31 W RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER Supply Input Voltage Range Input Voltage Range Output Voltage Range MIN MAX UNIT VIN 4.5 24 V5FILT 4.5 5.5 VBST1, VBST2 -0.1 30 VBST1, VBST2 (wrt LLx) -0.1 5.5 VFB1,VFB2,VO1,VO2 -0.1 5.5 TRIP1,TRIP2 -0.1 0.3 EN1,EN2 -0.1 24 DRVH1,DRVH2 -0.1 30 VBST1, VBST2 (wrt LLx) -0.1 5.5 LL1,LL2 1.8 24 DRVL1,DRVL2, VREG5 -0.1 5.5 PGND1, PGND2 -0.1 0.1 Operating Free-Air Temperature, TA -40 85 Operating Junction Temperature, TJ -40 125 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 V V V °C 3 TPS53124 SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ..................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, , VIN = 12 V, (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT Supply Current IIN VIN supply current VIN current, TA = 25°C, VREG5 tied to V5FLT, EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.8 V, LL1 = LL2 = 0.5 V IVINSDN VIN shutdown current VIN current, TA = 25°C, no load, EN1 = EN2 = 0 V 450 800 µA 10 VFB Voltage and Discharge Resistance VBG Bandgap initial regulation accuracy VVFBTH TA = 25°C -1% VFB threshold voltage TA = 25°C 755 TA = -40°C to 85°C 752 IVFB VFB input current VFBx = 0.8 V, TA = 25°C RDISCHG VO discharge resistance ENx = 0 V, VOx = 0.5 V,TA = 25°C 1% 765 775 778 mV -0.01 +/-0.1 µA 40 80 Ω 5 5.2 V VREG5 Output VVREG5 VREG5 output voltage TA = 25°C ,5.5 V < VIN < 24 V, 0 < IVREG5 < 10 mA VLN5 Line regulation 5.5 V < VIN < 24 V, IVREG5 = 10 mA 4.8 20 VLD5 Load regulation 1 mA < IVREG5 < 10 mA 40 IVREG5 Output current VIN = 5.5 V, VREG5 = 4.0 V, TA = 25°C 170 mV mA Output: N-Channel MOSFET Gate Drivers RDRVH DRVH resistance RDRVL DRVL resistance TD Dead time Source, IDRVHx = -100 mA 5.5 11 Sink, IDRVHx = 100 mA 2.5 5 Source, IDRVLx = - 100 mA 4 8 Sink, IDRVLx = 100 mA 2 4 Ω Ω DRVHx-low to DRVLx-on 20 50 80 DRVLx-low to DRVHx-on 20 40 80 0.7 0.8 0.9 V 1 µA ns Internal BST Diode VFBST Forward voltage VVREG5-VBSTx, IF = 10 mA, TA = 25°C IVBSTLK VBST leakage current VBST = 29 V, LL = 24 V, TA = 25°C 0.1 ON-Time Timer Control TON1 CH1 ON time LL1 = 12 V, VO1 = 1.5 V 390 TON2 CH2 ON time LL2 = 12 V, VO2 = 1.05 V 210 TON(min) CH2 ON time LL2 = 12 V, VO2 = 0.76 V 160 TOFF(min) CH1/CH2 min OFF time LL = 0.7 V TA = 25°C, VFB = 0.7 V 390 Internal SS time Internal soft start VFB = 0.735 V ns Soft Start TSS 4 Submit Documentation Feedback 0.85 1.2 1.4 ms Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 TPS53124 www.ti.com ..................................................................................................................................................... SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, , VIN = 12 V, (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT UVLO VUV5VFILT V5FILT UVLO threshold Wake up 3.7 4 4.3 Hysteresis 0.2 0.3 0.4 V LOGIC Threshold VENH ENx H-level input voltage EN 1/2 VENL ENx L-level input voltage EN 1/2 2 0.3 V Current Sense ITRIP TRIP source current VTRIPx = 0.1 V, TA = 25°C TCITRIP ITRIP temperature coefficient On the basis of 25°C VOCL(off) OCP compensation offset VR(trip) Current limit threshold setting range 8.5 10 11.5 4000 (VTRIPx-GND - VPGNDx-LLx) voltage,VTRIPx-GND = 60 mV, TA = 25°C -10 (VTRIPx-GND - VPGNDx-LLx) voltage, VTRIPx-GND = 60 mV -15 15 30 200 VTRIPx-GND voltage 0 µA ppm/°C 10 mV Output Undervoltage and Overvoltage Protection VOVP Output OVP trip threshold TOVPDEL Output OVP prop delay OVP detect 110% 115% 120% µs 1.5 UVP detect 65% 70% 75% VUVP Output UVP trip threshold TUVPDEL Output UVP delay 17 30 40 µs TUVPEN Output UVP enable delay 1.2 2 2.5 ms Hysteresis (recovery < 20 µs) 10% Thermal Shutdown TSDN (1) Thermal shutdown threshold Shutdown temperature (1) Hysteresis (1) 150 20 °C Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 5 TPS53124 SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ..................................................................................................................................................... www.ti.com DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 1, 14 I Supply input for high-side NFET driver (boost terminal). Connect capacitor from this pin to respective LL terminals. An internal PN diode is connected between VREG5 to each of these pins. User can add external schottky diode if forward drop is critical to drive the NFET. 24, 7 3, 12 I Channel 1 and Channel 2 enable pins. VO1, VO2 1, 6 4, 11 I Output connections to SMPS. These terminals serve ON-time adjustment, output discharge. VFB1, VFB2 2, 5 5, 10 I SMPS feedback inputs. Connect with feedback resistor divider. 3 7 I Signal ground pin. DRVH1, DRVH2 22, 9 28, 15 O High-side NFET driver outputs. LL referenced floating drivers. The gate drive voltage is defined by the voltage across VBST to LL node flying capacitor. LL1, LL2 21, 10 27, 16 I/O Switch-node connections for high-side drivers. Also serve as input to current comparators. DRVL1, DRVL2 20, 11 26, 17 O Synchronous NFET driver outputs. PGND referenced drivers. The gate drive voltage is defined by VREG5 voltage. PGND1, PGND2 19, 12 25, 18 I/O Ground returns for DRVL1 and DRVL2. Also serve as input of current comparators. Connect PGND1, PGND2 and GND strongly together near the device. TRIP1, TRIP2 18, 13 24, 19 I Over-current trip point set input. Connect resistor from this pin to GND to set threshold for synchronous RDS(on) sense. Voltage across this pin and GND is compared to voltage across PGND and LL at over current comparator. VIN 17 23 I Supply Input for 5-V linear regulator. V5FILT 15 21 I 5-V supply input for the entire control circuit except the NFET drivers. Connect capacitor (typical 1 µF) from GND to V5FILT. V5FILT is connected to VREG5 via internal resistor. VREG5 16 20 O 5-V power supply output. VREG5 is connected to V5FILT via internal resistor. TEST1, TEST2 4, 14 8, 20 I/O Used for test only. Pin should be connected to GND NAME GFN24 TSSOP28 VBST1, VBST2 23, 8 EN1, EN2 GND 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 TPS53124 www.ti.com ..................................................................................................................................................... SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 Pinout Diagrams 20 19 16 VREG5 4 5 15 V5FILT 14 13 TEST2 TRIP2 6 EN2 VBST2 DRVH2 LL2 DRVL2 PGND2 11 12 TRIP1 VIN 7 8 9 VO2 18 17 VBST1 NC EN1 VO1 VFB1 NC GND TEST1 NC VFB2 VO2 EN2 NC VBST2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TPS53124 VFB1 GND TEST1 VFB2 1 2 3 10 VO1 TSSOP Package (Top View) LL1 DRVL1 PGND1 VBST1 DRVH1 24 23 22 21 EN1 QFN Package (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DRVH1 LL1 DRVL1 PGND1 TRIP1 VIN VREG5 V5FILT TEST2 TRIP2 PGND2 DRVL2 LL2 DRVH2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 7 TPS53124 SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ..................................................................................................................................................... www.ti.com Functional Block Diagram 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 TPS53124 www.ti.com ..................................................................................................................................................... SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 DETAILED DESCRIPTION PWM Operation The main control loop of the switching mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAP™ Mode. D-CAP™ Mode uses internal compensation circuit and is suitable for low external component count configuration with appropriate amount of ESR at the output capacitor(s). The output ripple bottom voltage is monitored at a feedback point voltage. At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after internal one-shot timer expires. This one shot is determined by the converter’s input voltage ,VIN, and the output voltage ,VOUT, to keep frequency fairly constant over the input voltage range, hence it is called adaptive on-time control. The high-side MOSFET is turned on again when feedback information indicates insufficient output voltage. Repeating operation in this manner, the controller regulates the output voltage. Low-Side Driver The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is represented by its internal resistance. A dead time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from internal regulator VREG5 output. The instantaneous drive current is supplied by an input capacitor connected between VREG5 and GND. The average drive current is equal to the gate charge at VGS = 5 V times switching frequency. This gate drive current as well as the high-side gate drive current times 5 V makes the driving power which need to be dissipated from TPS53124 package. High-Side Driver The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by the gate charge at VGS = 5 V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance. PWM Frequency and Adaptive On-Time Control TPS53124 employs adaptive on-time control scheme and does not have a dedicated oscillator on board. However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio will be kept as VOUT/VIN technically with the same cycle time. Soft Start The TPS53124 has an internal, 1.2 ms, voltage servo softstart for each channel. When the ENx pin becomes high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start up. As TPS53124 shares one DAC with both channels, if ENx pin is set to high while another channel is starting up, soft start is postponed until another channel soft start has completed. If both of EN1 and EN2 are set high at a same time, both channels start up at same time. Output Discharge Control TPS53124 discharges the output when ENx is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO, and thermal shutdown). TPS53124 discharges outputs using an internal 40-Ω MOSFET which is connected to VOx and PGNDx. The external low-side MOSFET is not turned on for the output discharge operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that, on start, the regulated voltage always start from zero volts. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 9 TPS53124 SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ..................................................................................................................................................... www.ti.com Current Protection TPS53124 has cycle-by-cycle over current limiting control. The inductor current is monitored during the ‘OFF’ state and the controller keeps the OFF state during the inductor current is larger than the over-current trip level. In order to provide both good accuracy and cost effective solution, TPS53124 supports temperature compensated MOSFET RDS(on) sensing. TRIPx pin should be connected to GND through the trip voltage setting resistor, RTRIP. TRIPx terminal sources 10-µA ITRIP current at the ambient temperature and the trip level is set to the OCL trip voltage VTRIP as below: VTRIP ( mV ) = RTRIP ( k W ) ´10( m A ) (1) The trip level should be in the range of 30 mV to 200 mV over all operational temperature. The inductor current is monitored by the voltage between PGNDx pin and LLx pin. ITRIP has 4000ppm/°C temperature slope to compensate the temperature dependency of the RDS(on). PGNDx is used as the positive current sensing node so that PGNDx should be connected to the source terminal of the bottom MOSFET. As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load current at over-current threshold, IOCP, can be calculated as follows: I OCP = (V - VOUT ) ´ VOUT VTRIP I V 1 + RIPPLE = TRIP + ´ IN RDS ( on ) RDS ( on ) 2 ´ L ´ f VIN 2 (2) In an over-current condition, the current to the load exceeds the current to the output capacitor; thus the output voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and shutdown. Over/Under Voltage Protection TPS53124 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 30 µs, TPS53124 latches OFF both top and bottom MOSFET drivers, and shut off both drivers of another channel. This function is enabled approximately 2.0 ms. UVLO Protection TPS53124 has V5FILT Under Voltage Lock Out protection (UVLO). When the V5FILT voltage is lower than UVLO threshold voltage TPS53124 is shut off. This is non-latch protection. Thermal Shutdown TPS53124 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150°C), the switchers will be shut off as both DRVH and DRVL at low, the output discharge function enabled. Then TPS53124 is shut off. This is non-latch protection. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 TPS53124 www.ti.com ..................................................................................................................................................... SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 Typical Characteristics VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 8 600 IVIN(SDN)- Shutdown Current - mA IIN - Supply Current - mA 500 400 300 200 6 4 2 100 0 0 -50 0 50 100 150 -50 0 TJ Junction Temperature - °C Figure 1. 100 150 Figure 2. ITRIP SOURCE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY IO = 1A vs JUNCTION TEMPERATURE 20 500 fSW - Switching Frequency - kHz ITRIP- Source Current - mA 50 TJ Junction Temperature - °C 15 10 5 0 400 CH2 300 CH1 200 100 0 -50 0 50 100 150 0 TJ Junction Temperature - °C Figure 3. 5 10 15 20 25 VIN - Input Voltage - V Figure 4. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 11 TPS53124 SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ..................................................................................................................................................... www.ti.com Typical Characteristics (continued) SWITCHING FREQUENCY IO = 1A vs OUTPUT CURRENT 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT 1100 CH2 400 VOUT1 - Output Voltage - V fSW - Switching Frequency - kHz 500 300 CH1 200 1075 VI = 24 V 1050 VI = 5.5 V VI = 12 V 1025 100 0 1000 0 1.0 2.0 3.0 4.0 0 1.0 IOUT - Output Current - A 2.0 3.0 4.0 IOUT1 - Output Current - A Figure 5. Figure 6. 1.8-V OUTPUT VOLTAGE vs OUTPUT CURRENT 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE 1100 1.875 VOUT1 - Output Voltage - V VOUT2 - Output Voltage - V 1.850 VI = 24 V 1.825 1.800 VI = 5.5 V 1.775 VI = 12 V 1075 IO = 0 A 1050 IO = 2 A 1025 1.750 1.725 1000 0 1.0 2.0 3.0 4.0 0 IOUT2 - Output Current - A 10 15 20 25 VIN - Input Voltage - V Figure 7. 12 5 Figure 8. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 TPS53124 www.ti.com ..................................................................................................................................................... SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 Typical Characteristics (continued) 1.8-V OUTPUT VOLTAGE vs INPUT VOLTAGE 1.8-V LOAD TRANSIENT RESPONSE 1.875 VOUT2 (100 mV/div) VOUT2 - Output Voltage - V 1.850 IO = 0 A 1.825 1.800 IOUT2 (2 A/div) IO = 2 A 1.775 1.750 1.725 0 5 10 15 20 25 t - Time - 20 ms/div VIN - Input Voltage - V Figure 9. Figure 10. 1.05-V LOAD TRANSIENT RESPONSE VOUT1 (100 mV/div) IOUT1 (2 A/div) t - Time - 20 ms/div Figure 11. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 13 TPS53124 SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 ..................................................................................................................................................... www.ti.com APPLICATION INFORMATION Loop Compensation and External Parts Selection A buck converter system using D-CAP™ Mode can be simplified as below. Voltage Devider R1 R2 Vin PWM Ref Logic control Driver DRVH Lx DRVL ESR Vc Co Switching Modulator Figure 12. Simplifying the Modulator The output voltage is compared with internal reference voltage after divider resistors,R1 and R2. The PWM comparator determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The dc output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. For the loop stability, the 0dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency. fO = f 1 £ SW 2p ´ ESR ´ CO 3 (3) Although D-CAP™ Mode provides many advantages such as ease-of-use, minimum external components configuration and extremely short response time, a sufficient amount of feedback signal needs to be provided by external circuit to reduce jitter level. This is due to not employing an error amplifier in the loop. The required signal level is approximately 10 mV at the comparing point(VFB terminal). This gives Vripples at the output node becomes Equation 4. The output capacitor’s ESR should meet this requirement. VRIPPLE = 14 VOUT ´10 [mV ] VFBx (4) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 TPS53124 www.ti.com ..................................................................................................................................................... SLUS825B – FEBRUARY 2008 – REVISED MAY 2008 The external components selection is much simpler in D-CAP™ Mode. 1. Choose inductor. The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. Larger ripple current increases output ripple voltage, improves S/N ratio and contributes to a stable operation. L= 1 I IND( ripple ) ´f × (V IN (max) ) -V OUT ´V OUT V IN (max) = 3 I OUT (max) ´f ´ (V IN (max) ) -V OUT ´V OUT V IN (max) (5) The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as follows. V I IND( peak ) = R TRIP DS ( on ) + (VIN (max) - VOUT ) ´ VOUT 1 ´ L´ f VIN (max) (6) 2. Choose output capacitor. Polymer aluminum capacitor, organic semiconductor capacitor or specialty polymer capacitor are recommended. Determine ESR to meet required ripple voltage indicated previously. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS53124 15 PACKAGE MATERIALS INFORMATION www.ti.com 9-May-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS53124RGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TPS53124RGET VQFN RGE 24 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-May-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53124RGER VQFN RGE 24 3000 346.0 346.0 29.0 TPS53124RGET VQFN RGE 24 250 190.5 212.7 31.8 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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