HM5112805FLTD-6, HM5113805FLTD-6 EO 128M EDO DRAM (16-Mword × 8-bit) 8k refresh/4k refresh E0176H10 (Ver. 1.0) Jul. 12, 2001 Description L The HM5112805F L, HM5113805F L ar e 128M-bit dynamic R AMs orga nized as 16, 777,216-w ord × 8-bit. The y have re alize d high per forma nce and low powe r by employing C MOS proc ess tec hnology. HM5112805F L, HM5113805F L off er Extende d Da ta Out (ED O) P age Mode as a high spee d ac ce ss mode. They are packaged in 32-pin plastic TSOPII. Pr Features t uc od • Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 60 ns (max) • Power dissipation Active: 720 mW (max) (HM5112805F) 792 mW (max) (HM5113805F) Standby : 1.8 mW (max) (CMOS interface) (L-version) • EDO page mode capability • Refresh cycles RAS-only refresh 8192 cycles/64 ms (HM5112805F) 4096 cycles/64 ms (HM5113805F) CBR/Hidden refresh 4096 cycles/64 ms (HM5112805F, HM5113805F) This product became EOL in December, 2006. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HM5112805FLTD-6, HM5113805FLTD-6 EO • 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) • Battery backup operation (L-version) Ordering Information Access time Package HM5112805FLTD-6 60 ns 400-mil 32-pin plastic TSOP II (TTP-32DF) HM5113805FLTD-6 60 ns L Type No. t uc od Pr Data Sheet E0176H10 2 HM5112805FLTD-6, HM5113805FLTD-6 Pin Arrangement (HM5112805F) EO 32-pin TSOP 1 32 VSS I/O0 2 31 I/O7 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O3 5 28 I/O4 NC 6 27 VSS VCC 7 26 CAS WE 8 25 OE RAS 9 24 A12 A0 10 23 A11 A1 11 22 A10 A2 12 21 A9 A3 13 20 A8 A4 14 19 A7 A5 15 18 A6 VCC 16 17 VSS L VCC Pr (Top view) Pin name Function A0 to A12 Address input — Row/Refresh address A0 to A12 — Column address A0 to A10 I/O0 to I/O7 Data input/output RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable VCC Power supply VSS Ground NC No connection t uc od Pin Description Data Sheet E0176H10 3 HM5112805FLTD-6, HM5113805FLTD-6 Pin Arrangement (HM5113805F) EO 32-pin TSOP VCC 1 32 VSS I/O0 2 31 I/O7 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O3 5 28 I/O4 NC 6 27 VSS L 7 26 CAS WE 8 25 OE RAS 9 24 NC A0 10 23 A11 A1 11 22 A10 A2 12 21 A9 A3 13 20 A8 A4 14 19 A7 A5 15 18 A6 VCC 16 17 VSS Pr VCC (Top view) Pin name Function A0 to A11 Address input — Row/Refresh address A0 to A11 — Column address A0 to A11 I/O0 to I/O7 Data input/output RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable VCC Power supply VSS Ground NC No connection t uc od Pin Description Data Sheet E0176H10 4 HM5112805FLTD-6, HM5113805FLTD-6 Block Diagram (HM5112805F) EO A0 A1 to • • • Upper pellet Column decoder Column address buffers 16M array A10 Row decoder 16M array I/O buffers L 16M array Row address buffers A11 I/O1 I/O3 I/O4 I/O6 16M array A12 Pr Timing and control RAS CAS WE OE Lower pellet Timing and control uc od Column decoder Column address buffers Row address buffers Row decoder • • • 16M array 16M array I/O buffers 16M array I/O0 I/O2 I/O5 I/O7 16M array t Data Sheet E0176H10 5 HM5112805FLTD-6, HM5113805FLTD-6 Block Diagram (HM5113805F) EO A0 to A10 • • • Column address buffers 16M array 16M array Row decoder A1 I/O buffers L Row address buffers A11 Upper pellet Column decoder 16M array I/O1 I/O3 I/O4 I/O6 16M array Pr Timing and control RAS CAS WE OE Lower pellet Timing and control uc od Column decoder Column address buffers Row address buffers Row decoder • • • 16M array 16M array I/O buffers 16M array I/O0 I/O2 I/O5 I/O7 16M array t Data Sheet E0176H10 6 HM5112805FLTD-6, HM5113805FLTD-6 Operation Table EO RAS CAS WE OE I/O 0 to I/O 7 Operation H × × × High-Z Standby L L H L L L Dout Read cycle L* 2 × Din Early write cycle 2 H Din Delayed write cycle L L* L L H to L L to H Dout/Din Read-modify-write cycle L H × × High-Z RAS-only refresh cycle H to L L H × High-Z CAS-before-RAS refresh cycle or Self refresh cycle (L-Version) L L High-Z Read cycle (Output disabled) L L H H Notes: 1. H: VIH (inactive), L: VIL (active), ×: VIH or VIL 2. t WCS ≥ 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle Parameter Pr Absolute Maximum Ratings Value Unit Terminal voltage on any pin relative to VSS VT –0.5 to VCC + 0.5 (≤ 4.6 V (max)) V Power supply voltage relative to VSS VCC –0.5 to +4.6 V Iout 50 mA PT 1.0 W –55 to +125 °C Short circuit output current Power dissipation Storage temperature Tstg DC Operating Conditions uc od Symbol Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC 3.0 3.3 3.6 V 1, 2 VSS 0 0 0 V 2 Input high voltage VIH 2.0 — VCC + 0.3 V 1 Input low voltage VIL –0.3 — 0.8 V 1 Ambient temperature range Ta 0 — 70 ˚C Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. t Data Sheet E0176H10 7 HM5112805FLTD-6, HM5113805FLTD-6 DC Characteristics (HM5112805FL) EO HM5112805FL Symbol Min Max Unit Test conditions I CC1 — 200 mA t RC = min I CC2 — 500 µA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 200 mA t RC = min I CC5 — 10 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 200 mA t RC = min I CC7 — 200 mA RAS = VIL , CAS cycle, t HPC = t HPC min Battery backup current* 4 (Standby with CBR refresh) (L-version) I CC10 — 2.5 mA CMOS interface Dout = High-Z CBR refresh: t RC = 15.6 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 Input leakage current I LI Output leakage current I LO Output high voltage VOH 2.4 Output low voltage VOL 0 Parameter 1, Operating current* * 2 Standby current (L-version) RAS-only refresh current* 2 Standby current* 1 -6 L 1, EDO page mode current* * 3 Pr — 1.6 mA CMOS interface RAS, CAS ≤ 0.2 V Dout = High-Z –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V –5 5 µA 0 V ≤ Vout ≤ VCC Dout = disable uc od VCC V High Iout = –2 mA 0.4 V Low Iout = 2 mA Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. t Data Sheet E0176H10 8 HM5112805FLTD-6, HM5113805FLTD-6 DC Characteristics (HM5113805FL) EO HM5113805FL Symbol Min Max Unit Test conditions I CC1 — 220 mA t RC = min I CC2 — 500 µA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 220 mA t RC = min I CC5 — 10 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 220 mA t RC = min I CC7 — 200 mA RAS = VIL , CAS cycle, t HPC = t HPC min Battery backup current*4 (Standby with CBR refresh) (L-version) I CC10 — 2.5 mA CMOS interface Dout = High-Z CBR refresh: t RC = 15.6 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 Input leakage current I LI Output leakage current I LO Output high voltage VOH 2.4 Output low voltage VOL 0 Parameter 1, Operating current* * 2 Standby current (L-version) RAS-only refresh current* 2 Standby current* 1 -6 L 1, EDO page mode current* * 3 Pr — 1.6 mA CMOS interface RAS, CAS ≤ 0.2 V Dout = High-Z –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V –5 5 µA 0 V ≤ Vout ≤ VCC Dout = disable uc od VCC V High Iout = –2 mA 0.4 V Low Iout = 2 mA Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC . 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V) Parameter Symbol Input capacitance (Address) CI1 Input capacitance (Clocks) CI2 Output capacitance (Data-in, Data-out) CI/O Typ Max Unit Notes — 7 pF 1 — 7 pF 1 — 8 pF 1, 2 t Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout. Data Sheet E0176H10 9 HM5112805FLTD-6, HM5113805FLTD-6 AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *19 EO Test Conditions • • • • • Input rise and fall time: 2 ns Input pulse levels: VIL = 0 V, VIH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) L Parameter HM5112805FL/HM5113805FL -6 Min Max Unit Random read or write cycle time t RC 104 — ns RAS precharge time t RP 40 — ns t CP 10 — ns t RAS 60 10000 ns t CAS 10 10000 ns t ASR 0 — ns t RAH 10 — ns t ASC 0 — ns Column address hold time t CAH 10 — ns RAS to CAS delay time t RCD 14 45 ns 3 RAS to column address delay time t RAD 12 30 ns 4 RAS hold time t RSH 15 — ns CAS hold time t CSH 40 — ns CAS to RAS precharge time t CRP 5 — ns OE to Din delay time t OED 15 — ns 5 OE delay time from Din t DZO 0 — ns 6 CAS delay time from Din t DZC 0 — ns 6 Transition time (rise and fall) tT 2 50 ns 7 CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Notes t uc od Pr Symbol Data Sheet E0176H10 10 HM5112805FLTD-6, HM5113805FLTD-6 Read Cycle EO HM5112805FL/HM5113805FL -6 Symbol Min Max Unit Notes Access time from RAS t RAC — 60 ns 8, 9 Access time from CAS t CAC — 15 ns 9, 10, 17 Access time from address t AA — 30 ns 9, 11, 17 Access time from OE t OEA — 15 ns 9 Read command setup time t RCS 0 — ns Read command hold time to CAS t RCH 0 — ns Read command hold time from RAS t RCHR 60 — ns Read command hold time to RAS t RRH 0 — ns Column address to RAS lead time t RAL 30 — ns Column address to CAS lead time t CAL 18 — ns CAS to output in low-Z t CLZ 0 — ns t OH 3 — ns t OHO 3 — ns t OFF — 15 ns 13, 21 t OEZ — 15 ns 13 t CDD 15 — ns 5 t OHR 3 — ns 21 Output buffer turn-off to RAS t OFR — 15 ns 13, 21 Output buffer turn-off to WE t WEZ — 15 ns 13 WE to Din delay time t WED 15 — ns RAS to Din delay time t RDD 15 — ns L Parameter Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time 12 21 t uc od Output data hold time from RAS Pr Output data hold time 12 Data Sheet E0176H10 11 HM5112805FLTD-6, HM5113805FLTD-6 Write Cycle EO HM5112805FL/HM5113805FL -6 Symbol Min Max Unit Notes Write command setup time t WCS 0 — ns 14 Write command hold time t WCH 10 — ns Write command pulse width t WP 10 — ns Write command to RAS lead time t RWL 15 — ns Write command to CAS lead time t CWL 10 — ns Data-in setup time t DS 0 — ns 15 t DH 10 — ns 15 Notes Data-in hold time L Parameter Read-Modify-Write Cycle Pr HM5112805FL/HM5113805FL -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time OE hold time from WE Min Max Unit t RWC 140 — ns t RWD 79 — ns 14 t CWD 34 — ns 14 t AWD 49 — ns 14 t OEH 15 — ns Refresh Cycle uc od Column address to WE delay time Symbol HM5112805FL/HM5113805FL -6 Parameter Symbol Min CAS setup time (CBR refresh cycle) t CSR 5 CAS hold time (CBR refresh cycle) t CHR 10 WE setup time (CBR refresh cycle) t WRP 0 WE hold time (CBR refresh cycle) t WRH 10 RAS precharge to CAS hold time t RPC 5 Max Unit — ns — ns — ns — ns — ns Notes t Data Sheet E0176H10 12 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Cycle EO HM5112805FL/HM5113805FL -6 Symbol Min Max Unit Notes EDO page mode cycle time t HPC 25 — ns 20 EDO page mode RAS pulse width t RASP — 100000 ns 16 Access time from CAS precharge t CPA — 35 ns 9, 17 RAS hold time from CAS precharge t CPRH 35 — ns Output data hold time from CAS low t DOH 3 — ns CAS hold time referred OE t COL 10 — ns CAS to OE setup time t COP 5 — ns t RCHC 35 — ns Write pulse width during CAS precharge t WPE 10 — ns OE precharge time 10 — ns L Parameter Read command hold time from CAS precharge t OEP 9, 22 Pr EDO Page Mode Read-Modify-Write Cycle HM5112805FL/HM5113805FL -6 Parameter Symbol Min 68 WE delay time from CAS precharge 54 t CPW Refresh(HM5112805F) Unit Notes uc od EDO page mode read-modify-write cycle t HPRWC time Max — ns — ns 14 Parameter Symbol Max Unit Notes Refresh period (L-version) t REF 64 ms 8192 cycles Parameter Symbol Max Unit Notes Refresh period (L-version) t REF 64 ms 4096 cycles Refresh(HM5113805F) t Data Sheet E0176H10 13 HM5112805FLTD-6, HM5113805FLTD-6 Self Refresh Mode (L-version) EO HM5112805FL/HM5113805FL -6 Parameter Symbol Min Max Unit Notes RAS pulse width (self refresh) t RASS 100 — µs 25 RAS precharge time (self refresh) t RPS 110 — ns 25 CAS hold time (self refresh) t CHS –50 — ns L Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is controlled exclusively by t CAC . 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA . 5. Either t OED or t CDD must be satisfied. 6. Either t DZO or t DZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max). 11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max). 12. Either t RCH or t RRH must be satisfied for a read cycles. 13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min), t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/V SS line noise, which causes to degrade VIH min/VIL max level. t uc od Pr Data Sheet E0176H10 14 HM5112805FLTD-6, HM5113805FLTD-6 L EO 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between t OFR and t OFF. 22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6µs after exiting from self refresh mode. 24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 23. 25 At t RASS > 100 µs, self refresh mode is activated, and not activated at t RASS < 10 µs. It is undefined within the range of 10 µs ≤ t RASS ≤ 100 µs. For t RASS ≥ 10 µs, it is necessary to satisfy t RPS. 26. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. t uc od Pr Data Sheet E0176H10 15 HM5112805FLTD-6, HM5113805FLTD-6 Timing Waveforms*26 EO Read Cycle tRC tRAS tRP RAS tT tRAD tASR Row tASC tRAH tCAS tRAL tCAL tCAH Pr Address tCRP tRSH L CAS tCSH tRCD Column tRRH tRCHR tRCS WE tRCH uc od tDZC tCDD tWED tRDD High-Z ; Din tDZO tOEA OE tCAC tAA tRAC tCLZ tOED tOEZ tOHO tOFF tOH tOFR tOHR tWEZ Data Sheet E0176H10 16 t Dout Dout HM5112805FLTD-6, HM5113805FLTD-6 Early Write Cycle EO tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT L CAS tASR Row tASC tCAH Pr Address tRAH Column tWCS tDS Din Dout tDH Din uc od WE tWCH High-Z* * t WCS t WCS (min) t Data Sheet E0176H10 17 HM5112805FLTD-6, HM5113805FLTD-6 Delayed Write Cycle*18 EO tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT L CAS tASR Address tRAH tASC Row tCAH Column Pr tCWL tRWL tWP tRCS WE High-Z tDH Din ; Din uc od tDS tDZC tOED tDZO tOEH tOEP OE tOEZ tCLZ Dout High-Z Data Sheet E0176H10 18 t Invalid Dout HM5112805FLTD-6, HM5113805FLTD-6 Read-Modify-Write Cycle*18 EO tRWC tRAS tRP RAS tT tCAS L CAS tRCD tCRP tRAD tASR Address tASC tRAH Row tCAH Column Pr tCWL tCWD tRCS tRWL tWP tAWD tRWD WE tDS High-Z Din ; Din tDH uc od tDZC tOED tDZO tOEH tOEA OE tCAC tAA tRAC tOEP tOEZ tOHO Dout Dout tCLZ High-Z t Data Sheet E0176H10 19 HM5112805FLTD-6, HM5113805FLTD-6 RAS-Only Refresh Cycle EO tRC tRAS tRP RAS tT tRPC tCRP tCRP CAS L tASR Address tRAH Row tOFR High-Z t uc od ; Dout Pr tOFF Data Sheet E0176H10 20 HM5112805FLTD-6, HM5113805FLTD-6 CAS-Before-RAS Refresh Cycle EO tRP tRC tRC tRP tRAS tRAS tRP RAS tT tRPC tCP tCSR tRPC tCHR L CAS tWRP tCRP tCSR tCP tWRH tWRP tCHR tWRH WE tOFR tOFF uc od Pr Address High-Z t ; Dout Data Sheet E0176H10 21 HM5112805FLTD-6, HM5113805FLTD-6 Hidden Refresh Cycle EO tRC tRAS tRC tRAS tRP tRC tRP tRAS tRP RAS tT tRSH tCHR tCRP tRCD L CAS tRAD tASR Address tRAH tRAL tASC Row tCAH Column WE tDZC tRRH tRCH tWED uc od Pr tRCS tCDD tRDD High-Z Din tDZO tOED tOEA OE tCAC tAA tRAC tOFF ; tCLZ Dout tOH Dout tOFR tOHR t Data Sheet E0176H10 22 tOEZ tWEZ tOHO HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Read Cycle (1) EO t RP RAS tT t CSH t CP t HPC t CAS CAS t RCHR t RCS t HPC t RASP t CP t HPC t CPRH t CP t t CRP RSH t CAS tCAS tCAS t RCHC t RCH t RCS t RRH t RCH WE Address t WPE t ASC t CAH t ASC t CAH Column 2 Column 3 L tASR tRAH tASC Row tCAH Column 1 t CAL t CAL t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC Pr High-Z Din tCOL tDZO t OEP OE tCPA tOEA tAA tCAC tOED tCPA tAA tCAC tOEZ tOHO tOEZ tOFR tOHR tOEZ tCPA tAA ; tCAC tAA tCOP tOEP tOEA tRAC Dout tDOH Dout 1 Dout 2 tOHO tOFF tOH uc od tWEZ tCAC Dout 2 tOHO Dout 3 tOEA Dout 4 t Data Sheet E0176H10 23 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Read Cycle (2) EO t RP t RASP RAS tT t CSH t CP t HPC t CAS CAS tHPC t CP t HPC t CP t CAS t CAS t CRP tRSH tCAS t RCHC t RRH t RCH t RCS WE Address tRAH tASC Row L tASR tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 t CAL t RAL t CAH tASC Column 3 t CAL t WED Column 4 t CAL tRDD t CAL tDZC tCDD Pr High-Z Din tCOL tDZO t OEP OE tOEA tOED tOEZ tOFR tOHR tOEZ tCPA tAA ; tCAC tAA tCPA tAA tCAC tCPA tAA tCAC tCOP tOEP tOEZ tOEA tDOH tOHO Dout 1 Dout 2 tCAC tOHO tOFF tOH uc od tDOH tRAC Dout tOHO Dout 2 Dout 3 tOEA Dout 4 t Data Sheet E0176H10 24 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Early Write Cycle EO tRASP tRP RAS tT tCSH tRCD tHPC tCAS tCP tRSH tCAS tCP tCAS tCRP CAS Address Row L tASR tRAH tASC Column 1 WE Dout tCAH Column 2 tASC tWCH tDH Din 1 tWCH tWCS tDS tCAH Column N tWCS tWCH uc od tDS tASC Pr tWCS Din tCAH tDH Din 2 tDS tDH Din N High-Z* * t WCS t WCS (min) t Data Sheet E0176H10 25 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Delayed Write Cycle*18 EO tRASP tRP RAS tT tCP tRCD tHPC tCAS tCAS L CAS tCRP tCP tCSH tRSH tCAS tRAD tASR tASC tCAH tASC tCAH Column 1 Column 2 tRAH Address Row tASC tCAH tCWL tCWL Pr tCWL Column N tRCS tRCS WE tWP tDZC tDS tWP tDZC tDS tDH Din 1 Din tDZO tOED tWP tDZC tDS tDH uc od tDH tRWL tRCS Din 2 tDZO tOED tOEP tOEH tDZO tOED tOEP tOEH ; tOEP tOEH Din N OE tCLZ tCLZ tOEZ Dout Invalid Dout Invalid Dout tOEZ High-Z Invalid Dout t Data Sheet E0176H10 26 tCLZ tOEZ HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Read-Modify-Write Cycle*18 EO t RASP t RP RAS tT t RCD t HPRWC t CP t CAS t CAS L CAS t RSH t CP t CRP t CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t AWD Column 2 t CWL t RCS t CPW t WP t t DZC DS Din 2 t OED t DZO t OEP t OEH OE Din N t OED t DZO t OEP t OEH t OHO t OHO ; ; t OHO t DH uc od t OEP t OEH t RWL t CWD t DH Din 1 t OED t CWL t AWD t WP t t DZC DS t DH t DZO t CPW t RCS t CWD t WP t t DZC DS Din t CWL t AWD t RCS t CWD WE Column N Pr t RWD t ASC t CAH t OEA t CAC t OEA t CAC t AA t AA t CPA t RAC t OEZ t CLZ t CLZ t OEA t CAC t AA t CPA t OEZ t OEZ t CLZ High-Z Dout Dout 1 Dout 2 Dout N t Data Sheet E0176H10 27 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Mix Cycle (1)* 20 EO t RP t RASP RAS tT t CAS CAS t CRP t CP t CP t CP t CAS tCAS t CSH tCAS tCWL tRSH t RCD t WCS t ASC tRAH tASR Address Row tCAH Column 1 t RRH t RCH t RCS t RCS tCPW tAWD L WE t WCH t ASC t CAH tASC t CAH Column 2 Column 3 tWP tASC t RAL t CAH Column 4 t CAL Din Din 1 tRDD tCDD t CAL t DH t DS Pr t DS t DH High-Z Din 3 ; tOED tOEP OE tCAC Dout tCPA tAA t OEZ tOFR tWEZ tCPA tAA tOEZ tCAC uc od tCPA tAA tOEA tWED t DOH Dout 2 tCAC t OHO Dout 3 tOHO tOEA tOFF tOH Dout 4 t Data Sheet E0176H10 28 HM5112805FLTD-6, HM5113805FLTD-6 EDO Page Mode Mix Cycle (2) *20 EO t RP t RASP RAS tT t CSH t CAS CAS t RCD t CAS tCAS t RCHR t RCS t RCH tWCS t WCH tCWL Address Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 tRSH t RCS t RRH t RCH tWP tCPW L t ASC tRAH tCAS t RCS WE tASR t CRP t CP t CP t CP t RAL t CAH tASC Column 4 t CAL t CAL t DS High-Z Din t DH tRDD tCDD t DH Pr t DS Din 2 Din 3 t OEP t OEP tOED tOED tCOP tWED tCOL OE t OEA tAA tOEZ tCAC tRAC t OHO Dout tCPA tAA Dout 1 tAA tCAC tOEZ tOEA tOFF tOH uc od tOEA tCAC tOFR tWEZ tCPA tOEZ t OHO Dout 3 tOHO Dout 4 t Data Sheet E0176H10 29 HM5112805FLTD-6, HM5113805FLTD-6 Self Refresh Cycle (L-version)* 23, 24, 25 EO tRASS tRP tRPS RAS tT ; ; tRPC tCP tCRP tCHS tCSR CAS L tWRP WE ; Pr tOFR tWRH tOFF Dout High-Z t uc od Data Sheet E0176H10 30 HM5112805FLTD-6, HM5113805FLTD-6 Package Dimensions EO HM5112805FLTD HM5113805FLTD (TTP-32DF) As of January, 2001 Unit: mm 20.95 21.35 Max L 1.27 0.21 M 0.80 Pr 0.10 Hitachi Code JEDEC EIAJ Mass (reference value) TTP-32DF — — 0.54 g t uc od *Dimension including the plating thickness Base material dimension 0° – 5° 0.50 ± 0.10 0.45 11.76 ± 0.20 1.15 Max 0.05 ± 0.05 *0.42 ± 0.08 0.40 ± 0.06 16 *0.12 ± 0.05 0.10 ± 0.04 1 1.20 Max 17 10.16 32 Data Sheet E0176H10 31 HM5112805FLTD-6, HM5113805FLTD-6 Cautions EO L 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. t uc od Pr Data Sheet E0176H10 32