EP5388QI 800mA Synchronous Buck Regulator With Integrated Inductor 3mm x 3mm x 1.1mm Package July 2008 RoHS Compliant Halogen Free Product Overview Product Highlights The EP5388QI is a synchronous buck converter with integrated Inductor, PWM controller, MOSFETS, and Compensation providing the smallest possible solution size. The EP5388QI requires only two small MLCC capacitors to make a complete solution. Integration of the inductor greatly simplifies design, contains noise, reduces part count, and reduces solution footprint. Low output ripple ensures compatibility with RF systems. The EP5388QI operates at a switching frequency of 4 MHz, enabling this unprecedented level of integration and small external components. Type III voltage mode control is used to provide high noise immunity and wide control loop bandwidth. The small footprint makes this part ideal for space constrained portable applications. Shutdown current of <1uA extends battery life Output voltage level is programmed via a 3-pin VID selector providing seven pre-programmed output voltages along with an option for external resistor divider. Applications • • • • • • Noise Sensitive RF Applications Area Constrained Applications Wireless Data Applications Portable Gaming Devices Personal Media Players Advanced Mobile Processors, DSP, IO, Memory, Video, Multimedia Engines Featuring Integrated Inductor Technology • 3mm x 3mm x 1.1mm QFN package • Only two low cost MLCC caps required • 4 MHz switching frequency • High efficiency, up to 94% • Up to 800mA continuous output current • Wide 2.4V to 5.5V input range • VOUT range 0.6V to VIN – 0.5V • 3-Pin VID output voltage programming • 100% duty cycle capable • Less than 1 µA standby current • Low VOUT ripple for RF compatibility • Short circuit and over current protection • UVLO and thermal protection • RoHS compliant; MSL 3 260°C reflow Typical Application Circuit Part Number Temp Rating (°C) Vin 4.7µF 0603 Voltage Select Ordering Information EP5388QI-T EP5388QI-E VSense ENABLE VIN EP5388QI VFB VS0 VS1 VS2 GND Package -40 to +85 16-pin QFN T&R EP5388QI Evaluation Board Figure 1. Typical application circuit. www.enpirion.com VOUT Vout 47uF 1206 July 2008 EP5388QI Pin Description Figure 2. EP5388QI Package Pin-out. PIN 1, 15, 16 2,3 4 5 6 7,8 9 10, 11, 12 13 14 NAME FUNCTION No Connect. These pins are internally connected to the common switch node of the internal MOSFETs. NC(SW) pins are not to be electrically NC(SW) connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. PGND Power Ground. Feed back pin for external divider option. When using the external divider option (VS2=VS1=VS0= high) connect this pin to the center of VFB the external divider. Set the divider such that VFB = 0.603V. The “ground” side of the external divider should be connected to AGND. VSENSE Sense pin for preset output voltages. Connect at the output capacitor. AGND Analog ground. This is the quiet ground for the internal control circuitry Regulated Output Voltage. Refer to application section for proper layout VOUT and decoupling. No Connect. This pin should not be electrically connected to any NC external signal, voltage, or ground.. This pin must be soldered to the PCB. Output voltage select. VS2=pin10 VS1=pin11, VS0=pin12. Selects one of seven preset output voltages or choose external divider by connecting VS2,VS1,VS0 pins to logic high or low. (refer to section on output voltage select for more detail). ENABLE Output enable. Enable = logic high, disable = logic low. VIN Input voltage pin. ©Enpirion 2008 all rights reserved, E&OE 2 www.enpirion.com July 2008 EP5388QI Functional Block Diagram VIN UVLO Thermal Limit Current Limit ENABLE NC(SW) Soft Start P-Drive (-) Logic VOUT PWM Comp (+) N-Drive PGND VSENSE Sawtooth Generator Compensation Network (-) Switch Error Amp VFB (+) DAC Voltage Select VREF Package Boundry VS0 VS1 VS2 AGND Figure 3. EP5388QI Functional block diagram. Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER Input Supply Voltage Voltages on: ENABLE, VSENSE, VS0-VS2 Voltage on: VFB Storage Temperature Range Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C ESD Rating (based on Human Body Model) ©Enpirion 2008 all rights reserved, E&OE SYMBOL MIN MAX UNITS VIN -0.3 -0.3 -0.3 -65 7.0 VIN + 0.3 2.7 150 260 2000 V V V °C °C V TSTG 3 www.enpirion.com July 2008 EP5388QI Recommended Operating Conditions PARAMETER Input Voltage Range Output Voltage Range Output Current Operating Ambient Temperature Operating Junction Temperature SYMBOL MIN MAX UNITS VIN VOUT IOUT TA TJ 2.4 0.603 0 -40 -40 5.5 VIN – 0.5 800 +85 +125 V V mA °C °C Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient (0 LFM)* θJA 100 Thermal Shutdown Trip Point TJ-TP +150 Thermal Shutdown Trip Point Hysteresis 15 * Based on a 2 oz. copper board and proper thermal design in line with JEDEC EIJ-JESD51 standards. °C/W °C °C Electrical Characteristics NOTE: VIN = 3.6V, CIN = 4.7µF 0603 MLCC, COUT = 47uF 1206 MLCC. TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C. PARAMETER Under-Voltage Lockout UVLO Hysteresis VOUT Initial Accuracy Line Regulation Load Regulation Temperature Variation Overall VOUT Accuracy (Line, Load, and Temperature combined) Dynamic Voltage Slew Rate† Continuous Output Current Shut-Down Current PFET OCP Threshold SYMBOL VUVLO ∆VOUT_Initl ∆VOUT_linel ∆VOUT_load ∆VOUT_templ ∆VOUT_All MIN TA = 25C, 2.4V ≤ VIN ≤ 5.5V 2.4V ≤ VIN ≤ 5.5V 0A ≤ ILOAD ≤ 800mA -40°C ≤ TA ≤ +85°C 2.4V ≤ VIN ≤ 5.5V -40°C ≤ TA ≤ +85°C 0A ≤ ILOAD ≤ 800mA -2 IOUT ISD ILIM VFB Feedback Pin Input Current IFB VS2-VS0 Threshold VSX_TH -20°C ≤ TA ≤ +85°C -40°C ≤ TA ≤ +85°C Enable = Low 2.4V ≤ VIN ≤ 5.5V -20°C ≤ TA ≤ +85°C 0A ≤ ILOAD ≤ 800mA -3 IEN FOSC RDS(ON) RDS(ON) RDROPOUT ©Enpirion 2008 all rights reserved, E&OE MAX 2.3 +2 UNITS V V % %/V %/mA %/°C +3 % 1.5 1.875 V/mS 800 750 mA µA mA 0.75 1000 0.585 0.603 0.621 10 Pin = Low Pin = High 0.0 1.4 Pin = Low Pin = High ENABLE = Vin = 3.6V 0.4 VIN 4 2 4 340 270 450 V nA 0.2 VIN 0.0 1.4 V nA 1 IVSX VEN_TH TYP 2.2 0.145 0.06 0.0003 0.008 1.125 Vslew Feedback Pin Voltage VS2-VS0 Pin Input Current Enable Pin Voltage Thresholds Enable Pin Input Current Operating Frequency PFET On Resistance NFET On Resistance Dropout Resistance TEST CONDITIONS VIN going low to high V µA MHz mΩ mΩ mΩ www.enpirion.com July 2008 EP5388QI SYMBOL PARAMETER Soft-Start Operation Soft-Start Slew Rate† Vss Time to 90% Vout Tss † Parameter guaranteed by design. TEST CONDITIONS MIN TYP MAX UNITS 1.125 1.5 2 1.875 V/mS mS Vout = 3.3V Typical Performance Characteristics Typical performance characteristics are measured using the application circuit in Figure 1. All measurements made at 25ºC. 95 95 90 90 85 85 80 Efficiency (%) Efficiency (%) 80 75 70 75 70 65 65 60 60 55 55 50 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 50 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 Load Current (A) Load Current (A) Efficiency, VIN = 3.3V, VOUT = 2.5V,1.8V,1.5V, 1.2V, Efficiency, VIN = 3.7V, VOUT = 2.5V,1.8V,1.5V, 1.2V, top to bottom. top to bottom. 95 90 85 Efficiency (%) 80 75 70 65 60 55 50 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 Load Current (A) Efficiency, VIN = 5V, VOUT = 3.3V, 2.5V,1.8V,1.5V, 1.2V, top to bottom. ©Enpirion 2008 all rights reserved, E&OE Output Ripple, VIN = 5V, VOUT = 1.2V; Load = 500mA. 5 www.enpirion.com July 2008 EP5388QI Output Ripple, VIN = 5V, VOUT = 3.3V; Load = 500mA. Output Ripple, VIN = 3.3V, VOUT = 1.2V; Load = 500mA. Output Ripple, VIN = 3.3V, VOUT = 1.8V; Load = 500mA. Output Ripple, VIN = 3.3V, VOUT = 2.5V; Load = 500mA. Transient, VIN = 5.0V, VOUT = 1.2V, Load = 0-800mA. ©Enpirion 2008 all rights reserved, E&OE Transient, VIN = 5.0V, VOUT = 3.3V, Load = 0-800mA. 6 www.enpirion.com July 2008 EP5388QI Transient, VIN =3.3V, VOUT = 1.2V, Load = 0-800mA. Transient, VIN = 3.3V, VOUT = 1.8V, Load = 0-800mA. Startup, VIN = 3.6V, VOUT = 1.5V, Load = 500mA. Enable in light blue; VOUT in Dark blue. Shutdown, VIN = 3.6V, VOUT = 1.5V, Load = 500mA. Enable in light blue; VOUT in Dark blue. Detailed Description bandwidth providing excellent transient performance. The high switching frequency further enables the use of very small components making possible this unprecedented level of integration. Functional Overview The EP5388QI is a complete DCDC converter solution requiring only two low cost MLCC capacitors. MOSFET switches, PWM controller, Gate-drive, compensation, and inductor are integrated into the tiny 3mm x 3mm x 1.1mm package to provide the smallest footprint possible while maintaining high efficiency, low ripple, and high performance. The converter uses voltage mode control to provide the simplest implementation and high noise immunity. The device operates at a 4MHz switching frequency. The high switching frequency allows for a wide control loop ©Enpirion 2008 all rights reserved, E&OE Enpirion’s proprietary power MOSFET technology provides very low switching loss at frequencies of 4 MHz and higher, allowing for the use of very small internal components, and high performance. Integration of the magnetics virtually eliminates the design/layout issues normally associated with switch-mode DCDC converters. All of this enables much easier and faster incorporation into various applications to meet demanding requirements. 7 www.enpirion.com July 2008 EP5388QI Output voltage is chosen from seven preset values via a three pin VID voltage select scheme. An external divider option enables the selection of any voltage in 0.603V to VIN-0.5V range. This reduces the number of components that must be qualified and reduces inventory burden. The VID pins can be toggled on the fly to implement glitch free dynamic voltage scaling between any two of the seven preset VID voltage levels. Soft Start Protection features include under-voltage lockout (UVLO), over-current protection (OCP), short circuit protection, and thermal overload protection. Over Current/Short Circuit Protection Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the “ENABLE” pin is asserted “high”. Digital control circuitry limits the VOUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The soft start ramp rate is nominally 1.5V/mS. When an over current condition occurs, VOUT is pulled low. This condition is maintained for a period of approximately 1.2 ms and then a normal soft start cycle is initiated. If the over current condition still persists, this cycle will repeat. Integrated Inductor Enpirion has introduced the world’s first product family featuring integrated inductors. The EP5388QI utilizes a proprietary low loss integrated inductor. The use of an internal inductor localizes the noises associated with the output loop currents. The inherent shielding and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board. Further, the package layout is optimized to reduce the electrical path length for the AC ripple currents that are a major source of radiated emissions from DCDC converters. The integrated inductor significantly reduces parasitic effects that can harm loop stability, and makes layout very simple. Under Voltage Lockout During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. Enable The ENABLE pin provides a means to shut down the converter or enable normal operation. Transitioning from low to high will cause the converter to go through a soft start cycle. Transitioning from high to a low will cause the device to discharge the output and then shutdown. In shutdown mode, the device quiescent current will be less than 1 uA. Stable Over Wide Range of Operating Conditions The EP5388QI utilizes an internal type III compensation network and is designed to provide a high degree of stability over a wide range of operating conditions. The device operates over the entire input and output voltage range with no external modifications required. The very high switching frequency allows for a very wide control loop bandwidth. ©Enpirion 2008 all rights reserved, E&OE NOTE: This pin must not be left floating. 8 www.enpirion.com July 2008 EP5388QI shutdown temperature the thermal shutdown circuit turns off the converter thus allowing the device to cool. When the junction temperature decreases by 15°C, the device will go through the normal startup process. Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal Application Information Table 2. VID voltage select settings. VS2 0 0 0 0 1 1 1 1 VS1 0 0 1 1 0 0 1 1 VS0 0 1 0 1 0 1 0 1 External Voltage Divider VOUT 3.3V 2.5V 1.8V 1.5V 1.25V 1.2V 0.8V User Selectable As described above, the external voltage divider option is chosen by connecting the VS0, VS1, and VS2 pins to VIN or logic high. The EP5388QI uses a separate feedback pin, VFB, when using the external divider. VSENSE must be connected to VOUT as indicated in Figure 4. Output Voltage Select VOUT Vout Ra EP5388QI VS2 47µF 1206 VFB VS0 VS1 Rb GND Figure 4. External Divider application circuit. The output voltage is nominally selected by the following formula: Ra VOUT = 0.603V(1 + Rb ) Then Rb is given as: Table 1 shows the various VS2-VS0 pin logic states and the associated output voltage levels. A logic “1” indicates a connection to VIN or to a “high” logic voltage level. A logic “0” indicates a connection to ground or to a “low” logic voltage level. These pins can be either hardwired to VIN or GND or alternatively can be driven by standard logic levels. Logic low is defined as VSX ≤ 0.4V. Logic high is defined as 1.4V ≤ VSX ≤ VIN. Any level between these two values is indeterminate. These pins must not be left floating. ©Enpirion 2008 all rights reserved, E&OE Vin 4.7uF 0603 To provide the highest degree of flexibility in choosing output voltage, the EP5388QI uses a 3 pin VID, or Voltage ID, output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage divider. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. VSense ENABLE VIN 0.603 xR a Ω VOUT − 0.603 Ra must be chosen as nominally 200KΩ to maintain loop gain. VOUT can be programmed over the range of 0.603V to VIN-0.5V. R b = Dynamically Adjustable Output The EP5388QI is designed to allow for dynamic switching between the seven predefined VID voltage levels. The inter- 9 www.enpirion.com July 2008 EP5388QI voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. The slew rate is identical to the soft-start slew rate of 1.5V/mS. 5. Note that in this configuration, VSENSE should NOT be connected to VOUT. Ra and Rb values are calculated as shown in the external voltage divider section. Dynamic transitioning between internal VID settings and the external divider is not allowed. The Input and the output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias voltage, and temperature and are not suitable for switch-mode DC-DC converter output filter applications. Input and Output Capacitors The input capacitance requirement is 4.7uF 0603 MLCC. Enpirion recommends that a low ESR MLCC capacitor be used. Contact Enpirion Applications for information on other output capacitor usage. A variety of output capacitor configurations are possible depending on footprint and ripple requirements. For typical applications, it is recommended to use a single 47uF 1206 MLCC capacitor. Ripple performance can be improved by using 2 x 22uF 0805 MLCC capacitors. VSense ENABLE VIN Vin 4.7uF 0603 VFB VS0 VS1 A single 10uF 0805 MLCC can be used if VOUT programming is accomplished using an external resistor divider, with the addition of a 10pF phase lead capacitor as shown in Figure 10µF 0805 Ra EP5388QI VS2 VOUT Vout Rb 10pF GND Figure 5. Applications circuit for COUT = 1 x 10uF 0805. Layout Considerations* *Optimized PCB layout file is downloadable from the Enpirion website to assure first pass design success. Refer to figure 6 for the following layout recommendations. Recommendation 1: The input and output filter capacitors should be placed as close to the EP5388QI as possible to reduce EMI from input and output loop AC currents. This reduces the physical area of these AC current loops. Recommendation 2: The system ground plane should be the first layer immediately below the surface layer (PCB layer 2). If it is not possible to make PCB layer 2 the system ground plane, a local ground island should be created on PCB layer 2 under the Enpirion device and including the area under the input and output filter capacitors. This ground plane, or ground island, should be continuous and uninterrupted underneath the Enpirion device and the input and output filter capacitors. Recommendation 3: The surface layer ground pour should include a “slit” as shown in figure 6 to separate the input and output AC loop currents. This will help reduce noise coupling from the input current loop to the output current loop. ©Enpirion 2008 all rights reserved, E&OE 10 www.enpirion.com July 2008 EP5388QI Recommendation 4: Multiple small vias (approximately 0.25mm finished diameter) should be used to connect the ground terminals of the input and output capacitors, and the surface ground pour under the device, to the system ground plane. If a local ground island is used on PCB layer 2, the vias should connect to the ground island and continue down to the PCB system ground plane. Recommendation 5: The AGND pin should be connected to the system ground plane using a via as described in recommendation 4. AGND must NOT be connected to the surface layer ground pour. Recommendation 6: As with any switch-mode DC-DC converter, do not run any sensitive signal or control lines under the converter package. Vias Slit Figure 6. PCB layout recommendation. Recommended PCB Footprint ©Enpirion 2008 all rights reserved, E&OE 11 www.enpirion.com July 2008 ©Enpirion 2008 all rights reserved, E&OE EP5388QI 12 www.enpirion.com July 2008 EP5388QI Package Dimensions ©Enpirion 2008 all rights reserved, E&OE 13 www.enpirion.com July 2008 EP5388QI Contact Information Enpirion, Inc. 685 US Route 202/206 Suite 305 Bridgewater, NJ 08807 Phone: +1 908-575-7550 Fax: +1 908-575-0775 Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion. ©Enpirion 2008 all rights reserved, E&OE 14 www.enpirion.com